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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/arch/sparc/lib/NG4memset.S
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/* SPDX-License-Identifier: GPL-2.0 */

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/* NG4memset.S: Niagara-4 optimized memset/bzero.

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 *

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 * Copyright (C) 2012 David S. Miller ([email protected])

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 */

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#include <asm/asi.h>

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	.register	%g2, #scratch

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	.register	%g3, #scratch

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	.text

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	.align		32

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	.globl		NG4memset

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NG4memset:

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	andcc		%o1, 0xff, %o4

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	be,pt		%icc, 1f

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	 mov		%o2, %o1

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	sllx		%o4, 8, %g1

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	or		%g1, %o4, %o2

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	sllx		%o2, 16, %g1

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	or		%g1, %o2, %o2

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	sllx		%o2, 32, %g1

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	ba,pt		%icc, 1f

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	 or		%g1, %o2, %o4

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	.size		NG4memset,.-NG4memset

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	.align		32

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	.globl		NG4bzero

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NG4bzero:

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	clr		%o4

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1:	cmp		%o1, 16

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	ble		%icc, .Ltiny

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	 mov		%o0, %o3

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	sub		%g0, %o0, %g1

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	and		%g1, 0x7, %g1

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	brz,pt		%g1, .Laligned8

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	 sub		%o1, %g1, %o1

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1:	stb		%o4, [%o0 + 0x00]

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	subcc		%g1, 1, %g1

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	bne,pt		%icc, 1b

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	 add		%o0, 1, %o0

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.Laligned8:

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	cmp		%o1, 64 + (64 - 8)

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	ble		.Lmedium

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	 sub		%g0, %o0, %g1

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	andcc		%g1, (64 - 1), %g1

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	brz,pn		%g1, .Laligned64

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	 sub		%o1, %g1, %o1

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1:	stx		%o4, [%o0 + 0x00]

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	subcc		%g1, 8, %g1

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	bne,pt		%icc, 1b

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	 add		%o0, 0x8, %o0

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.Laligned64:

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	andn		%o1, 64 - 1, %g1

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	sub		%o1, %g1, %o1

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	brnz,pn		%o4, .Lnon_bzero_loop

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	 mov		0x20, %g2

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1:	stxa		%o4, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P

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	subcc		%g1, 0x40, %g1

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	stxa		%o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P

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	bne,pt		%icc, 1b

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	 add		%o0, 0x40, %o0

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.Lpostloop:

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	cmp		%o1, 8

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	bl,pn		%icc, .Ltiny

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	 membar		#StoreStore|#StoreLoad

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.Lmedium:

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	andn		%o1, 0x7, %g1

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	sub		%o1, %g1, %o1

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1:	stx		%o4, [%o0 + 0x00]

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	subcc		%g1, 0x8, %g1

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	bne,pt		%icc, 1b

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	 add		%o0, 0x08, %o0

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	andcc		%o1, 0x4, %g1

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	be,pt		%icc, .Ltiny

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	 sub		%o1, %g1, %o1

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	stw		%o4, [%o0 + 0x00]

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	add		%o0, 0x4, %o0

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.Ltiny:

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	cmp		%o1, 0

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	be,pn		%icc, .Lexit

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1:	 subcc		%o1, 1, %o1

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	stb		%o4, [%o0 + 0x00]

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	bne,pt		%icc, 1b

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	 add		%o0, 1, %o0

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.Lexit:

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	retl

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	 mov		%o3, %o0

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.Lnon_bzero_loop:

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	mov		0x08, %g3

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	mov		0x28, %o5

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1:	stxa		%o4, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P

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	subcc		%g1, 0x40, %g1

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	stxa		%o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P

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	stxa		%o4, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P

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	stxa		%o4, [%o0 + %o5] ASI_BLK_INIT_QUAD_LDD_P

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	add		%o0, 0x10, %o0

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	stxa		%o4, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P

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	stxa		%o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P

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	stxa		%o4, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P

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	stxa		%o4, [%o0 + %o5] ASI_BLK_INIT_QUAD_LDD_P

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	bne,pt		%icc, 1b

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	 add		%o0, 0x30, %o0

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	ba,a,pt		%icc, .Lpostloop

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	 nop

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	.size		NG4bzero,.-NG4bzero

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