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torvalds
GitHub Repository: torvalds/linux
Path: blob/master/arch/x86/boot/startup/gdt_idt.c
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/linkage.h>
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#include <linux/types.h>
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#include <asm/desc.h>
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#include <asm/init.h>
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#include <asm/setup.h>
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#include <asm/sev.h>
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#include <asm/trapnr.h>
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/*
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* Data structures and code used for IDT setup in head_64.S. The bringup-IDT is
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* used until the idt_table takes over. On the boot CPU this happens in
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* x86_64_start_kernel(), on secondary CPUs in start_secondary(). In both cases
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* this happens in the functions called from head_64.S.
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*
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* The idt_table can't be used that early because all the code modifying it is
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* in idt.c and can be instrumented by tracing or KASAN, which both don't work
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* during early CPU bringup. Also the idt_table has the runtime vectors
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* configured which require certain CPU state to be setup already (like TSS),
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* which also hasn't happened yet in early CPU bringup.
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*/
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static gate_desc bringup_idt_table[NUM_EXCEPTION_VECTORS] __page_aligned_data;
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/* This may run while still in the direct mapping */
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void __head startup_64_load_idt(void *vc_handler)
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{
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struct desc_ptr desc = {
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.address = (unsigned long)rip_rel_ptr(bringup_idt_table),
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.size = sizeof(bringup_idt_table) - 1,
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};
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struct idt_data data;
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gate_desc idt_desc;
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/* @vc_handler is set only for a VMM Communication Exception */
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if (vc_handler) {
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init_idt_data(&data, X86_TRAP_VC, vc_handler);
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idt_init_desc(&idt_desc, &data);
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native_write_idt_entry((gate_desc *)desc.address, X86_TRAP_VC, &idt_desc);
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}
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native_load_idt(&desc);
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}
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/*
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* Setup boot CPU state needed before kernel switches to virtual addresses.
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*/
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void __head startup_64_setup_gdt_idt(void)
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{
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struct gdt_page *gp = rip_rel_ptr((void *)(__force unsigned long)&gdt_page);
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void *handler = NULL;
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struct desc_ptr startup_gdt_descr = {
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.address = (unsigned long)gp->gdt,
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.size = GDT_SIZE - 1,
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};
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/* Load GDT */
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native_load_gdt(&startup_gdt_descr);
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/* New GDT is live - reload data segment registers */
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asm volatile("movl %%eax, %%ds\n"
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"movl %%eax, %%ss\n"
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"movl %%eax, %%es\n" : : "a"(__KERNEL_DS) : "memory");
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if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT))
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handler = rip_rel_ptr(vc_no_ghcb);
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startup_64_load_idt(handler);
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}
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