CoCalc -- sm4-aesni-avx-asm

GitHub Repository: torvalds/linux
Path: blob/master/arch/x86/crypto/sm4-aesni-avx-asm_64.S
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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 * SM4 Cipher Algorithm, AES-NI/AVX optimized.
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 * as specified in
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 * https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html
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 *
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 * Copyright (C) 2018 Markku-Juhani O. Saarinen <[email protected]>
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 * Copyright (C) 2020 Jussi Kivilinna <[email protected]>
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 * Copyright (c) 2021 Tianjia Zhang <[email protected]>
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 */
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/* Based on SM4 AES-NI work by libgcrypt and Markku-Juhani O. Saarinen at:
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 *  https://github.com/mjosaarinen/sm4ni
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 */
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#include <linux/linkage.h>
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#include <linux/cfi_types.h>
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#include <asm/frame.h>
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#define rRIP         (%rip)
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#define RX0          %xmm0
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#define RX1          %xmm1
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#define MASK_4BIT    %xmm2
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#define RTMP0        %xmm3
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#define RTMP1        %xmm4
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#define RTMP2        %xmm5
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#define RTMP3        %xmm6
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#define RTMP4        %xmm7
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#define RA0          %xmm8
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#define RA1          %xmm9
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#define RA2          %xmm10
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#define RA3          %xmm11
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#define RB0          %xmm12
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#define RB1          %xmm13
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#define RB2          %xmm14
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#define RB3          %xmm15
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#define RNOT         %xmm0
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#define RBSWAP       %xmm1
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/* Transpose four 32-bit words between 128-bit vectors. */
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#define transpose_4x4(x0, x1, x2, x3, t1, t2) \
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	vpunpckhdq x1, x0, t2;                \
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	vpunpckldq x1, x0, x0;                \
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	                                      \
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	vpunpckldq x3, x2, t1;                \
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	vpunpckhdq x3, x2, x2;                \
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	                                      \
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	vpunpckhqdq t1, x0, x1;               \
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	vpunpcklqdq t1, x0, x0;               \
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	                                      \
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	vpunpckhqdq x2, t2, x3;               \
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	vpunpcklqdq x2, t2, x2;
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/* pre-SubByte transform. */
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#define transform_pre(x, lo_t, hi_t, mask4bit, tmp0) \
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	vpand x, mask4bit, tmp0;                     \
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	vpandn x, mask4bit, x;                       \
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	vpsrld $4, x, x;                             \
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	                                             \
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	vpshufb tmp0, lo_t, tmp0;                    \
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	vpshufb x, hi_t, x;                          \
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	vpxor tmp0, x, x;
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/* post-SubByte transform. Note: x has been XOR'ed with mask4bit by
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 * 'vaeslastenc' instruction.
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 */
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#define transform_post(x, lo_t, hi_t, mask4bit, tmp0) \
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	vpandn mask4bit, x, tmp0;                     \
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	vpsrld $4, x, x;                              \
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	vpand x, mask4bit, x;                         \
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	                                              \
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	vpshufb tmp0, lo_t, tmp0;                     \
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	vpshufb x, hi_t, x;                           \
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	vpxor tmp0, x, x;
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.section	.rodata.cst16, "aM", @progbits, 16
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.align 16
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/*
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 * Following four affine transform look-up tables are from work by
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 * Markku-Juhani O. Saarinen, at https://github.com/mjosaarinen/sm4ni
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 *
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 * These allow exposing SM4 S-Box from AES SubByte.
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 */
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/* pre-SubByte affine transform, from SM4 field to AES field. */
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.Lpre_tf_lo_s:
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	.quad 0x9197E2E474720701, 0xC7C1B4B222245157
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.Lpre_tf_hi_s:
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	.quad 0xE240AB09EB49A200, 0xF052B91BF95BB012
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/* post-SubByte affine transform, from AES field to SM4 field. */
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.Lpost_tf_lo_s:
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	.quad 0x5B67F2CEA19D0834, 0xEDD14478172BBE82
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.Lpost_tf_hi_s:
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	.quad 0xAE7201DD73AFDC00, 0x11CDBE62CC1063BF
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/* For isolating SubBytes from AESENCLAST, inverse shift row */
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.Linv_shift_row:
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	.byte 0x00, 0x0d, 0x0a, 0x07, 0x04, 0x01, 0x0e, 0x0b
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	.byte 0x08, 0x05, 0x02, 0x0f, 0x0c, 0x09, 0x06, 0x03
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/* Inverse shift row + Rotate left by 8 bits on 32-bit words with vpshufb */
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.Linv_shift_row_rol_8:
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	.byte 0x07, 0x00, 0x0d, 0x0a, 0x0b, 0x04, 0x01, 0x0e
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	.byte 0x0f, 0x08, 0x05, 0x02, 0x03, 0x0c, 0x09, 0x06
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/* Inverse shift row + Rotate left by 16 bits on 32-bit words with vpshufb */
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.Linv_shift_row_rol_16:
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	.byte 0x0a, 0x07, 0x00, 0x0d, 0x0e, 0x0b, 0x04, 0x01
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	.byte 0x02, 0x0f, 0x08, 0x05, 0x06, 0x03, 0x0c, 0x09
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/* Inverse shift row + Rotate left by 24 bits on 32-bit words with vpshufb */
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.Linv_shift_row_rol_24:
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	.byte 0x0d, 0x0a, 0x07, 0x00, 0x01, 0x0e, 0x0b, 0x04
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	.byte 0x05, 0x02, 0x0f, 0x08, 0x09, 0x06, 0x03, 0x0c
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/* For CTR-mode IV byteswap */
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.Lbswap128_mask:
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	.byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
127

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/* For input word byte-swap */
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.Lbswap32_mask:
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	.byte 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12
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.align 4
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/* 4-bit mask */
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.L0f0f0f0f:
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	.long 0x0f0f0f0f
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/* 12 bytes, only for padding */
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.Lpadding_deadbeef:
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	.long 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
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141

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.text
143

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/*
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 * void sm4_aesni_avx_crypt4(const u32 *rk, u8 *dst,
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 *                           const u8 *src, int nblocks)
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 */
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SYM_FUNC_START(sm4_aesni_avx_crypt4)
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	/* input:
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	 *	%rdi: round key array, CTX
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	 *	%rsi: dst (1..4 blocks)
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	 *	%rdx: src (1..4 blocks)
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	 *	%rcx: num blocks (1..4)
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	 */
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	FRAME_BEGIN
156

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	vmovdqu 0*16(%rdx), RA0;
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	vmovdqa RA0, RA1;
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	vmovdqa RA0, RA2;
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	vmovdqa RA0, RA3;
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	cmpq $2, %rcx;
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	jb .Lblk4_load_input_done;
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	vmovdqu 1*16(%rdx), RA1;
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	je .Lblk4_load_input_done;
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	vmovdqu 2*16(%rdx), RA2;
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	cmpq $3, %rcx;
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	je .Lblk4_load_input_done;
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	vmovdqu 3*16(%rdx), RA3;
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.Lblk4_load_input_done:
171

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	vmovdqa .Lbswap32_mask rRIP, RTMP2;
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	vpshufb RTMP2, RA0, RA0;
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	vpshufb RTMP2, RA1, RA1;
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	vpshufb RTMP2, RA2, RA2;
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	vpshufb RTMP2, RA3, RA3;
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	vbroadcastss .L0f0f0f0f rRIP, MASK_4BIT;
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	vmovdqa .Lpre_tf_lo_s rRIP, RTMP4;
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	vmovdqa .Lpre_tf_hi_s rRIP, RB0;
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	vmovdqa .Lpost_tf_lo_s rRIP, RB1;
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	vmovdqa .Lpost_tf_hi_s rRIP, RB2;
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	vmovdqa .Linv_shift_row rRIP, RB3;
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	vmovdqa .Linv_shift_row_rol_8 rRIP, RTMP2;
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	vmovdqa .Linv_shift_row_rol_16 rRIP, RTMP3;
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	transpose_4x4(RA0, RA1, RA2, RA3, RTMP0, RTMP1);
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#define ROUND(round, s0, s1, s2, s3)                                \
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	vbroadcastss (4*(round))(%rdi), RX0;                        \
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	vpxor s1, RX0, RX0;                                         \
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	vpxor s2, RX0, RX0;                                         \
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	vpxor s3, RX0, RX0; /* s1 ^ s2 ^ s3 ^ rk */                 \
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	                                                            \
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	/* sbox, non-linear part */                                 \
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	transform_pre(RX0, RTMP4, RB0, MASK_4BIT, RTMP0);           \
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	vaesenclast MASK_4BIT, RX0, RX0;                            \
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	transform_post(RX0, RB1, RB2, MASK_4BIT, RTMP0);            \
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	                                                            \
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	/* linear part */                                           \
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	vpshufb RB3, RX0, RTMP0;                                    \
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	vpxor RTMP0, s0, s0; /* s0 ^ x */                           \
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	vpshufb RTMP2, RX0, RTMP1;                                  \
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	vpxor RTMP1, RTMP0, RTMP0; /* x ^ rol(x,8) */               \
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	vpshufb RTMP3, RX0, RTMP1;                                  \
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	vpxor RTMP1, RTMP0, RTMP0; /* x ^ rol(x,8) ^ rol(x,16) */   \
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	vpshufb .Linv_shift_row_rol_24 rRIP, RX0, RTMP1;            \
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	vpxor RTMP1, s0, s0; /* s0 ^ x ^ rol(x,24) */               \
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	vpslld $2, RTMP0, RTMP1;                                    \
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	vpsrld $30, RTMP0, RTMP0;                                   \
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	vpxor RTMP0, s0, s0;                                        \
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	/* s0 ^ x ^ rol(x,2) ^ rol(x,10) ^ rol(x,18) ^ rol(x,24) */ \
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	vpxor RTMP1, s0, s0;
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	leaq (32*4)(%rdi), %rax;
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.align 16
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.Lroundloop_blk4:
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	ROUND(0, RA0, RA1, RA2, RA3);
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	ROUND(1, RA1, RA2, RA3, RA0);
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	ROUND(2, RA2, RA3, RA0, RA1);
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	ROUND(3, RA3, RA0, RA1, RA2);
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	leaq (4*4)(%rdi), %rdi;
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	cmpq %rax, %rdi;
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	jne .Lroundloop_blk4;
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#undef ROUND
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	vmovdqa .Lbswap128_mask rRIP, RTMP2;
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	transpose_4x4(RA0, RA1, RA2, RA3, RTMP0, RTMP1);
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	vpshufb RTMP2, RA0, RA0;
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	vpshufb RTMP2, RA1, RA1;
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	vpshufb RTMP2, RA2, RA2;
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	vpshufb RTMP2, RA3, RA3;
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	vmovdqu RA0, 0*16(%rsi);
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	cmpq $2, %rcx;
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	jb .Lblk4_store_output_done;
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	vmovdqu RA1, 1*16(%rsi);
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	je .Lblk4_store_output_done;
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	vmovdqu RA2, 2*16(%rsi);
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	cmpq $3, %rcx;
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	je .Lblk4_store_output_done;
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	vmovdqu RA3, 3*16(%rsi);
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.Lblk4_store_output_done:
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	vzeroall;
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	FRAME_END
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	RET;
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SYM_FUNC_END(sm4_aesni_avx_crypt4)
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SYM_FUNC_START_LOCAL(__sm4_crypt_blk8)
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	/* input:
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	 *	%rdi: round key array, CTX
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	 *	RA0, RA1, RA2, RA3, RB0, RB1, RB2, RB3: eight parallel
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	 *						plaintext blocks
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	 * output:
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	 *	RA0, RA1, RA2, RA3, RB0, RB1, RB2, RB3: eight parallel
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	 * 						ciphertext blocks
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	 */
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	FRAME_BEGIN
261

262
	vmovdqa .Lbswap32_mask rRIP, RTMP2;
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	vpshufb RTMP2, RA0, RA0;
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	vpshufb RTMP2, RA1, RA1;
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	vpshufb RTMP2, RA2, RA2;
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	vpshufb RTMP2, RA3, RA3;
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	vpshufb RTMP2, RB0, RB0;
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	vpshufb RTMP2, RB1, RB1;
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	vpshufb RTMP2, RB2, RB2;
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	vpshufb RTMP2, RB3, RB3;
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272
	vbroadcastss .L0f0f0f0f rRIP, MASK_4BIT;
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	transpose_4x4(RA0, RA1, RA2, RA3, RTMP0, RTMP1);
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	transpose_4x4(RB0, RB1, RB2, RB3, RTMP0, RTMP1);
275

276
#define ROUND(round, s0, s1, s2, s3, r0, r1, r2, r3)                \
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	vbroadcastss (4*(round))(%rdi), RX0;                        \
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	vmovdqa .Lpre_tf_lo_s rRIP, RTMP4;                          \
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	vmovdqa .Lpre_tf_hi_s rRIP, RTMP1;                          \
280
	vmovdqa RX0, RX1;                                           \
281
	vpxor s1, RX0, RX0;                                         \
282
	vpxor s2, RX0, RX0;                                         \
283
	vpxor s3, RX0, RX0; /* s1 ^ s2 ^ s3 ^ rk */                 \
284
	vmovdqa .Lpost_tf_lo_s rRIP, RTMP2;                         \
285
	vmovdqa .Lpost_tf_hi_s rRIP, RTMP3;                         \
286
	vpxor r1, RX1, RX1;                                         \
287
	vpxor r2, RX1, RX1;                                         \
288
	vpxor r3, RX1, RX1; /* r1 ^ r2 ^ r3 ^ rk */                 \
289
                                                                    \
290
	/* sbox, non-linear part */                                 \
291
	transform_pre(RX0, RTMP4, RTMP1, MASK_4BIT, RTMP0);         \
292
	transform_pre(RX1, RTMP4, RTMP1, MASK_4BIT, RTMP0);         \
293
	vmovdqa .Linv_shift_row rRIP, RTMP4;                        \
294
	vaesenclast MASK_4BIT, RX0, RX0;                            \
295
	vaesenclast MASK_4BIT, RX1, RX1;                            \
296
	transform_post(RX0, RTMP2, RTMP3, MASK_4BIT, RTMP0);        \
297
	transform_post(RX1, RTMP2, RTMP3, MASK_4BIT, RTMP0);        \
298
                                                                    \
299
	/* linear part */                                           \
300
	vpshufb RTMP4, RX0, RTMP0;                                  \
301
	vpxor RTMP0, s0, s0; /* s0 ^ x */                           \
302
	vpshufb RTMP4, RX1, RTMP2;                                  \
303
	vmovdqa .Linv_shift_row_rol_8 rRIP, RTMP4;                  \
304
	vpxor RTMP2, r0, r0; /* r0 ^ x */                           \
305
	vpshufb RTMP4, RX0, RTMP1;                                  \
306
	vpxor RTMP1, RTMP0, RTMP0; /* x ^ rol(x,8) */               \
307
	vpshufb RTMP4, RX1, RTMP3;                                  \
308
	vmovdqa .Linv_shift_row_rol_16 rRIP, RTMP4;                 \
309
	vpxor RTMP3, RTMP2, RTMP2; /* x ^ rol(x,8) */               \
310
	vpshufb RTMP4, RX0, RTMP1;                                  \
311
	vpxor RTMP1, RTMP0, RTMP0; /* x ^ rol(x,8) ^ rol(x,16) */   \
312
	vpshufb RTMP4, RX1, RTMP3;                                  \
313
	vmovdqa .Linv_shift_row_rol_24 rRIP, RTMP4;                 \
314
	vpxor RTMP3, RTMP2, RTMP2; /* x ^ rol(x,8) ^ rol(x,16) */   \
315
	vpshufb RTMP4, RX0, RTMP1;                                  \
316
	vpxor RTMP1, s0, s0; /* s0 ^ x ^ rol(x,24) */               \
317
	/* s0 ^ x ^ rol(x,2) ^ rol(x,10) ^ rol(x,18) ^ rol(x,24) */ \
318
	vpslld $2, RTMP0, RTMP1;                                    \
319
	vpsrld $30, RTMP0, RTMP0;                                   \
320
	vpxor RTMP0, s0, s0;                                        \
321
	vpxor RTMP1, s0, s0;                                        \
322
	vpshufb RTMP4, RX1, RTMP3;                                  \
323
	vpxor RTMP3, r0, r0; /* r0 ^ x ^ rol(x,24) */               \
324
	/* r0 ^ x ^ rol(x,2) ^ rol(x,10) ^ rol(x,18) ^ rol(x,24) */ \
325
	vpslld $2, RTMP2, RTMP3;                                    \
326
	vpsrld $30, RTMP2, RTMP2;                                   \
327
	vpxor RTMP2, r0, r0;                                        \
328
	vpxor RTMP3, r0, r0;
329

330
	leaq (32*4)(%rdi), %rax;
331
.align 16
332
.Lroundloop_blk8:
333
	ROUND(0, RA0, RA1, RA2, RA3, RB0, RB1, RB2, RB3);
334
	ROUND(1, RA1, RA2, RA3, RA0, RB1, RB2, RB3, RB0);
335
	ROUND(2, RA2, RA3, RA0, RA1, RB2, RB3, RB0, RB1);
336
	ROUND(3, RA3, RA0, RA1, RA2, RB3, RB0, RB1, RB2);
337
	leaq (4*4)(%rdi), %rdi;
338
	cmpq %rax, %rdi;
339
	jne .Lroundloop_blk8;
340

341
#undef ROUND
342

343
	vmovdqa .Lbswap128_mask rRIP, RTMP2;
344

345
	transpose_4x4(RA0, RA1, RA2, RA3, RTMP0, RTMP1);
346
	transpose_4x4(RB0, RB1, RB2, RB3, RTMP0, RTMP1);
347
	vpshufb RTMP2, RA0, RA0;
348
	vpshufb RTMP2, RA1, RA1;
349
	vpshufb RTMP2, RA2, RA2;
350
	vpshufb RTMP2, RA3, RA3;
351
	vpshufb RTMP2, RB0, RB0;
352
	vpshufb RTMP2, RB1, RB1;
353
	vpshufb RTMP2, RB2, RB2;
354
	vpshufb RTMP2, RB3, RB3;
355

356
	FRAME_END
357
	RET;
358
SYM_FUNC_END(__sm4_crypt_blk8)
359

360
/*
361
 * void sm4_aesni_avx_crypt8(const u32 *rk, u8 *dst,
362
 *                           const u8 *src, int nblocks)
363
 */
364
SYM_FUNC_START(sm4_aesni_avx_crypt8)
365
	/* input:
366
	 *	%rdi: round key array, CTX
367
	 *	%rsi: dst (1..8 blocks)
368
	 *	%rdx: src (1..8 blocks)
369
	 *	%rcx: num blocks (1..8)
370
	 */
371
	cmpq $5, %rcx;
372
	jb sm4_aesni_avx_crypt4;
373

374
	FRAME_BEGIN
375

376
	vmovdqu (0 * 16)(%rdx), RA0;
377
	vmovdqu (1 * 16)(%rdx), RA1;
378
	vmovdqu (2 * 16)(%rdx), RA2;
379
	vmovdqu (3 * 16)(%rdx), RA3;
380
	vmovdqu (4 * 16)(%rdx), RB0;
381
	vmovdqa RB0, RB1;
382
	vmovdqa RB0, RB2;
383
	vmovdqa RB0, RB3;
384
	je .Lblk8_load_input_done;
385
	vmovdqu (5 * 16)(%rdx), RB1;
386
	cmpq $7, %rcx;
387
	jb .Lblk8_load_input_done;
388
	vmovdqu (6 * 16)(%rdx), RB2;
389
	je .Lblk8_load_input_done;
390
	vmovdqu (7 * 16)(%rdx), RB3;
391

392
.Lblk8_load_input_done:
393
	call __sm4_crypt_blk8;
394

395
	cmpq $6, %rcx;
396
	vmovdqu RA0, (0 * 16)(%rsi);
397
	vmovdqu RA1, (1 * 16)(%rsi);
398
	vmovdqu RA2, (2 * 16)(%rsi);
399
	vmovdqu RA3, (3 * 16)(%rsi);
400
	vmovdqu RB0, (4 * 16)(%rsi);
401
	jb .Lblk8_store_output_done;
402
	vmovdqu RB1, (5 * 16)(%rsi);
403
	je .Lblk8_store_output_done;
404
	vmovdqu RB2, (6 * 16)(%rsi);
405
	cmpq $7, %rcx;
406
	je .Lblk8_store_output_done;
407
	vmovdqu RB3, (7 * 16)(%rsi);
408

409
.Lblk8_store_output_done:
410
	vzeroall;
411
	FRAME_END
412
	RET;
413
SYM_FUNC_END(sm4_aesni_avx_crypt8)
414

415
/*
416
 * void sm4_aesni_avx_ctr_enc_blk8(const u32 *rk, u8 *dst,
417
 *                                 const u8 *src, u8 *iv)
418
 */
419
SYM_TYPED_FUNC_START(sm4_aesni_avx_ctr_enc_blk8)
420
	/* input:
421
	 *	%rdi: round key array, CTX
422
	 *	%rsi: dst (8 blocks)
423
	 *	%rdx: src (8 blocks)
424
	 *	%rcx: iv (big endian, 128bit)
425
	 */
426
	FRAME_BEGIN
427

428
	/* load IV and byteswap */
429
	vmovdqu (%rcx), RA0;
430

431
	vmovdqa .Lbswap128_mask rRIP, RBSWAP;
432
	vpshufb RBSWAP, RA0, RTMP0; /* be => le */
433

434
	vpcmpeqd RNOT, RNOT, RNOT;
435
	vpsrldq $8, RNOT, RNOT; /* low: -1, high: 0 */
436

437
#define inc_le128(x, minus_one, tmp) \
438
	vpcmpeqq minus_one, x, tmp;  \
439
	vpsubq minus_one, x, x;      \
440
	vpslldq $8, tmp, tmp;        \
441
	vpsubq tmp, x, x;
442

443
	/* construct IVs */
444
	inc_le128(RTMP0, RNOT, RTMP2); /* +1 */
445
	vpshufb RBSWAP, RTMP0, RA1;
446
	inc_le128(RTMP0, RNOT, RTMP2); /* +2 */
447
	vpshufb RBSWAP, RTMP0, RA2;
448
	inc_le128(RTMP0, RNOT, RTMP2); /* +3 */
449
	vpshufb RBSWAP, RTMP0, RA3;
450
	inc_le128(RTMP0, RNOT, RTMP2); /* +4 */
451
	vpshufb RBSWAP, RTMP0, RB0;
452
	inc_le128(RTMP0, RNOT, RTMP2); /* +5 */
453
	vpshufb RBSWAP, RTMP0, RB1;
454
	inc_le128(RTMP0, RNOT, RTMP2); /* +6 */
455
	vpshufb RBSWAP, RTMP0, RB2;
456
	inc_le128(RTMP0, RNOT, RTMP2); /* +7 */
457
	vpshufb RBSWAP, RTMP0, RB3;
458
	inc_le128(RTMP0, RNOT, RTMP2); /* +8 */
459
	vpshufb RBSWAP, RTMP0, RTMP1;
460

461
	/* store new IV */
462
	vmovdqu RTMP1, (%rcx);
463

464
	call __sm4_crypt_blk8;
465

466
	vpxor (0 * 16)(%rdx), RA0, RA0;
467
	vpxor (1 * 16)(%rdx), RA1, RA1;
468
	vpxor (2 * 16)(%rdx), RA2, RA2;
469
	vpxor (3 * 16)(%rdx), RA3, RA3;
470
	vpxor (4 * 16)(%rdx), RB0, RB0;
471
	vpxor (5 * 16)(%rdx), RB1, RB1;
472
	vpxor (6 * 16)(%rdx), RB2, RB2;
473
	vpxor (7 * 16)(%rdx), RB3, RB3;
474

475
	vmovdqu RA0, (0 * 16)(%rsi);
476
	vmovdqu RA1, (1 * 16)(%rsi);
477
	vmovdqu RA2, (2 * 16)(%rsi);
478
	vmovdqu RA3, (3 * 16)(%rsi);
479
	vmovdqu RB0, (4 * 16)(%rsi);
480
	vmovdqu RB1, (5 * 16)(%rsi);
481
	vmovdqu RB2, (6 * 16)(%rsi);
482
	vmovdqu RB3, (7 * 16)(%rsi);
483

484
	vzeroall;
485
	FRAME_END
486
	RET;
487
SYM_FUNC_END(sm4_aesni_avx_ctr_enc_blk8)
488

489
/*
490
 * void sm4_aesni_avx_cbc_dec_blk8(const u32 *rk, u8 *dst,
491
 *                                 const u8 *src, u8 *iv)
492
 */
493
SYM_TYPED_FUNC_START(sm4_aesni_avx_cbc_dec_blk8)
494
	/* input:
495
	 *	%rdi: round key array, CTX
496
	 *	%rsi: dst (8 blocks)
497
	 *	%rdx: src (8 blocks)
498
	 *	%rcx: iv
499
	 */
500
	FRAME_BEGIN
501

502
	vmovdqu (0 * 16)(%rdx), RA0;
503
	vmovdqu (1 * 16)(%rdx), RA1;
504
	vmovdqu (2 * 16)(%rdx), RA2;
505
	vmovdqu (3 * 16)(%rdx), RA3;
506
	vmovdqu (4 * 16)(%rdx), RB0;
507
	vmovdqu (5 * 16)(%rdx), RB1;
508
	vmovdqu (6 * 16)(%rdx), RB2;
509
	vmovdqu (7 * 16)(%rdx), RB3;
510

511
	call __sm4_crypt_blk8;
512

513
	vmovdqu (7 * 16)(%rdx), RNOT;
514
	vpxor (%rcx), RA0, RA0;
515
	vpxor (0 * 16)(%rdx), RA1, RA1;
516
	vpxor (1 * 16)(%rdx), RA2, RA2;
517
	vpxor (2 * 16)(%rdx), RA3, RA3;
518
	vpxor (3 * 16)(%rdx), RB0, RB0;
519
	vpxor (4 * 16)(%rdx), RB1, RB1;
520
	vpxor (5 * 16)(%rdx), RB2, RB2;
521
	vpxor (6 * 16)(%rdx), RB3, RB3;
522
	vmovdqu RNOT, (%rcx); /* store new IV */
523

524
	vmovdqu RA0, (0 * 16)(%rsi);
525
	vmovdqu RA1, (1 * 16)(%rsi);
526
	vmovdqu RA2, (2 * 16)(%rsi);
527
	vmovdqu RA3, (3 * 16)(%rsi);
528
	vmovdqu RB0, (4 * 16)(%rsi);
529
	vmovdqu RB1, (5 * 16)(%rsi);
530
	vmovdqu RB2, (6 * 16)(%rsi);
531
	vmovdqu RB3, (7 * 16)(%rsi);
532

533
	vzeroall;
534
	FRAME_END
535
	RET;
536
SYM_FUNC_END(sm4_aesni_avx_cbc_dec_blk8)
537

538
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