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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/arch/x86/hyperv/hv_trampoline.S
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/* SPDX-License-Identifier: GPL-2.0-only */

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/*

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 * X86 specific Hyper-V kdump/crash related code.

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 *

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 * Copyright (C) 2025, Microsoft, Inc.

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 *

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 */

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#include <linux/linkage.h>

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#include <asm/alternative.h>

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#include <asm/msr.h>

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#include <asm/processor-flags.h>

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#include <asm/nospec-branch.h>

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/*

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 * void noreturn hv_crash_asm32(arg1)

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 *    arg1 == edi == 32bit PA of struct hv_crash_tramp_data

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 *

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 * The hypervisor jumps here upon devirtualization in protected mode. This

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 * code gets copied to a page in the low 4G ie, 32bit space so it can run

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 * in the protected mode. Hence we cannot use any compile/link time offsets or

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 * addresses. It restores long mode via temporary gdt and page tables and

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 * eventually jumps to kernel code entry at HV_CRASHDATA_OFFS_C_entry.

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 *

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 * PreCondition (ie, Hypervisor call back ABI):

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 *  o CR0 is set to 0x0021: PE(prot mode) and NE are set, paging is disabled

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 *  o CR4 is set to 0x0

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 *  o IA32_EFER is set to 0x901 (SCE and NXE are set)

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 *  o EDI is set to the Arg passed to HVCALL_DISABLE_HYP_EX.

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 *  o CS, DS, ES, FS, GS are all initialized with a base of 0 and limit 0xFFFF

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 *  o IDTR, TR and GDTR are initialized with a base of 0 and limit of 0xFFFF

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 *  o LDTR is initialized as invalid (limit of 0)

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 *  o MSR PAT is power on default.

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 *  o Other state/registers are cleared. All TLBs flushed.

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 */

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#define HV_CRASHDATA_OFFS_TRAMPCR3    0x0    /*  0 */

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#define HV_CRASHDATA_OFFS_KERNCR3     0x8    /*  8 */

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#define HV_CRASHDATA_OFFS_GDTRLIMIT  0x12    /* 18 */

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#define HV_CRASHDATA_OFFS_CS_JMPTGT  0x28    /* 40 */

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#define HV_CRASHDATA_OFFS_C_entry    0x30    /* 48 */

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	.text

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	.code32

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SYM_CODE_START(hv_crash_asm32)

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	UNWIND_HINT_UNDEFINED

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	ENDBR

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	movl	$X86_CR4_PAE, %ecx

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	movl	%ecx, %cr4

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	movl %edi, %ebx

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	add $HV_CRASHDATA_OFFS_TRAMPCR3, %ebx

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	movl %cs:(%ebx), %eax

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	movl %eax, %cr3

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	/* Setup EFER for long mode now */

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	movl	$MSR_EFER, %ecx

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	rdmsr

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	btsl	$_EFER_LME, %eax

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	wrmsr

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	/* Turn paging on using the temp 32bit trampoline page table */

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	movl %cr0, %eax

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	orl $(X86_CR0_PG), %eax

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	movl %eax, %cr0

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	/* since kernel cr3 could be above 4G, we need to be in the long mode

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	 * before we can load 64bits of the kernel cr3. We use a temp gdt for

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	 * that with CS.L=1 and CS.D=0 */

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	mov %edi, %eax

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	add $HV_CRASHDATA_OFFS_GDTRLIMIT, %eax

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	lgdtl %cs:(%eax)

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	/* not done yet, restore CS now to switch to CS.L=1 */

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	mov %edi, %eax

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	add $HV_CRASHDATA_OFFS_CS_JMPTGT, %eax

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	ljmp %cs:*(%eax)

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SYM_CODE_END(hv_crash_asm32)

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	/* we now run in full 64bit IA32-e long mode, CS.L=1 and CS.D=0 */

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	.code64

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	.balign 8

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SYM_CODE_START(hv_crash_asm64)

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	UNWIND_HINT_UNDEFINED

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	ENDBR

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	/* restore kernel page tables so we can jump to kernel code */

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	mov %edi, %eax

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	add $HV_CRASHDATA_OFFS_KERNCR3, %eax

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	movq %cs:(%eax), %rbx

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	movq %rbx, %cr3

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	mov %edi, %eax

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	add $HV_CRASHDATA_OFFS_C_entry, %eax

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	movq %cs:(%eax), %rbx

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	ANNOTATE_RETPOLINE_SAFE

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	jmp *%rbx

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	int $3

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SYM_INNER_LABEL(hv_crash_asm_end, SYM_L_GLOBAL)

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SYM_CODE_END(hv_crash_asm64)

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