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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/arch/x86/include/asm/barrier.h
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/* SPDX-License-Identifier: GPL-2.0 */

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#ifndef _ASM_X86_BARRIER_H

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#define _ASM_X86_BARRIER_H

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#include <asm/alternative.h>

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#include <asm/nops.h>

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/*

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 * Force strict CPU ordering.

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 * And yes, this might be required on UP too when we're talking

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 * to devices.

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 */

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#ifdef CONFIG_X86_32

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#define mb() asm volatile(ALTERNATIVE("lock addl $0,-4(%%esp)", "mfence", \

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				      X86_FEATURE_XMM2) ::: "memory", "cc")

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#define rmb() asm volatile(ALTERNATIVE("lock addl $0,-4(%%esp)", "lfence", \

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				       X86_FEATURE_XMM2) ::: "memory", "cc")

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#define wmb() asm volatile(ALTERNATIVE("lock addl $0,-4(%%esp)", "sfence", \

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				       X86_FEATURE_XMM2) ::: "memory", "cc")

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#else

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#define __mb()	asm volatile("mfence":::"memory")

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#define __rmb()	asm volatile("lfence":::"memory")

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#define __wmb()	asm volatile("sfence" ::: "memory")

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#endif

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/**

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 * array_index_mask_nospec() - generate a mask that is ~0UL when the

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 * 	bounds check succeeds and 0 otherwise

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 * @index: array element index

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 * @size: number of elements in array

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 *

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 * Returns:

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 *     0 - (index < size)

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 */

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#define array_index_mask_nospec(idx,sz) ({	\

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	typeof((idx)+(sz)) __idx = (idx);	\

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	typeof(__idx) __sz = (sz);		\

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	unsigned long __mask;			\

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	asm volatile ("cmp %1,%2; sbb %0,%0"	\

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			:"=r" (__mask)		\

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			:ASM_INPUT_G (__sz),	\

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			 "r" (__idx)		\

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			:"cc");			\

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	__mask; })

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/* Prevent speculative execution past this barrier. */

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#define barrier_nospec() alternative("", "lfence", X86_FEATURE_LFENCE_RDTSC)

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#define __dma_rmb()	barrier()

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#define __dma_wmb()	barrier()

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#define __smp_mb()	asm volatile("lock addl $0,-4(%%" _ASM_SP ")" ::: "memory", "cc")

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#define __smp_rmb()	dma_rmb()

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#define __smp_wmb()	barrier()

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#define __smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0)

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#define __smp_store_release(p, v)					\

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do {									\

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	compiletime_assert_atomic_type(*p);				\

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	barrier();							\

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	WRITE_ONCE(*p, v);						\

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} while (0)

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#define __smp_load_acquire(p)						\

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({									\

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	typeof(*p) ___p1 = READ_ONCE(*p);				\

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	compiletime_assert_atomic_type(*p);				\

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	barrier();							\

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	___p1;								\

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})

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/* Atomic operations are already serializing on x86 */

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#define __smp_mb__before_atomic()	do { } while (0)

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#define __smp_mb__after_atomic()	do { } while (0)

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/* Writing to CR3 provides a full memory barrier in switch_mm(). */

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#define smp_mb__after_switch_mm()	do { } while (0)

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#include <asm-generic/barrier.h>

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#endif /* _ASM_X86_BARRIER_H */

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