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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/arch/x86/kernel/cpu/cpu.h
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/* SPDX-License-Identifier: GPL-2.0 */

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#ifndef ARCH_X86_CPU_H

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#define ARCH_X86_CPU_H

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#include <asm/cpu.h>

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#include <asm/topology.h>

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#include "topology.h"

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/* attempt to consolidate cpu attributes */

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struct cpu_dev {

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	const char	*c_vendor;

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	/* some have two possibilities for cpuid string */

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	const char	*c_ident[2];

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	void            (*c_early_init)(struct cpuinfo_x86 *);

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	void		(*c_bsp_init)(struct cpuinfo_x86 *);

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	void		(*c_init)(struct cpuinfo_x86 *);

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	void		(*c_identify)(struct cpuinfo_x86 *);

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	void		(*c_detect_tlb)(struct cpuinfo_x86 *);

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	int		c_x86_vendor;

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#ifdef CONFIG_X86_32

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	/* Optional vendor specific routine to obtain the cache size. */

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	unsigned int	(*legacy_cache_size)(struct cpuinfo_x86 *,

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					     unsigned int);

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	/* Family/stepping-based lookup table for model names. */

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	struct legacy_cpu_model_info {

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		int		family;

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		const char	*model_names[16];

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	}		legacy_models[5];

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#endif

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};

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#define cpu_dev_register(cpu_devX) \

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	static const struct cpu_dev *const __cpu_dev_##cpu_devX __used \

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	__section(".x86_cpu_dev.init") = \

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	&cpu_devX;

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extern const struct cpu_dev *const __x86_cpu_dev_start[],

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			    *const __x86_cpu_dev_end[];

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#ifdef CONFIG_CPU_SUP_INTEL

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extern void __init tsx_init(void);

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void tsx_ap_init(void);

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void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c);

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#else

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static inline void tsx_init(void) { }

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static inline void tsx_ap_init(void) { }

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static inline void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c) { }

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#endif /* CONFIG_CPU_SUP_INTEL */

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extern void init_spectral_chicken(struct cpuinfo_x86 *c);

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extern void get_cpu_cap(struct cpuinfo_x86 *c);

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extern void get_cpu_address_sizes(struct cpuinfo_x86 *c);

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extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c);

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extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);

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extern void init_intel_cacheinfo(struct cpuinfo_x86 *c);

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extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);

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extern void init_hygon_cacheinfo(struct cpuinfo_x86 *c);

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extern void check_null_seg_clears_base(struct cpuinfo_x86 *c);

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void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u16 die_id);

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void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c);

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#if defined(CONFIG_AMD_NB) && defined(CONFIG_SYSFS)

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struct amd_northbridge *amd_init_l3_cache(int index);

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#else

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static inline struct amd_northbridge *amd_init_l3_cache(int index)

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{

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	return NULL;

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}

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#endif

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unsigned int aperfmperf_get_khz(int cpu);

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void cpu_select_mitigations(void);

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extern void x86_spec_ctrl_setup_ap(void);

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extern void update_srbds_msr(void);

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extern void update_gds_msr(void);

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extern enum spectre_v2_mitigation spectre_v2_enabled;

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static inline bool spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode)

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{

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	return mode == SPECTRE_V2_EIBRS ||

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	       mode == SPECTRE_V2_EIBRS_RETPOLINE ||

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	       mode == SPECTRE_V2_EIBRS_LFENCE;

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}

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#endif /* ARCH_X86_CPU_H */

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