/* SPDX-License-Identifier: GPL-2.0 */1/*---------------------------------------------------------------------------+2| control_w.h |3| |4| Copyright (C) 1992,1993 |5| W. Metzenthen, 22 Parker St, Ormond, Vic 3163, |6| Australia. E-mail [email protected] |7| |8+---------------------------------------------------------------------------*/910#ifndef _CONTROLW_H_11#define _CONTROLW_H_1213#ifdef __ASSEMBLER__14#define _Const_(x) $##x15#else16#define _Const_(x) x17#endif1819#define CW_RC _Const_(0x0C00) /* rounding control */20#define CW_PC _Const_(0x0300) /* precision control */2122#define CW_Precision Const_(0x0020) /* loss of precision mask */23#define CW_Underflow Const_(0x0010) /* underflow mask */24#define CW_Overflow Const_(0x0008) /* overflow mask */25#define CW_ZeroDiv Const_(0x0004) /* divide by zero mask */26#define CW_Denormal Const_(0x0002) /* denormalized operand mask */27#define CW_Invalid Const_(0x0001) /* invalid operation mask */2829#define CW_Exceptions _Const_(0x003f) /* all masks */3031#define RC_RND _Const_(0x0000)32#define RC_DOWN _Const_(0x0400)33#define RC_UP _Const_(0x0800)34#define RC_CHOP _Const_(0x0C00)3536/* p 15-5: Precision control bits affect only the following:37ADD, SUB(R), MUL, DIV(R), and SQRT */38#define PR_24_BITS _Const_(0x000)39#define PR_53_BITS _Const_(0x200)40#define PR_64_BITS _Const_(0x300)41#define PR_RESERVED_BITS _Const_(0x100)42/* FULL_PRECISION simulates all exceptions masked */43#define FULL_PRECISION (PR_64_BITS | RC_RND | 0x3f)4445#endif /* _CONTROLW_H_ */464748