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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/arch/xtensa/include/asm/cache.h
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/*

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 * include/asm-xtensa/cache.h

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 *

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 * This file is subject to the terms and conditions of the GNU General Public

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 * License.  See the file "COPYING" in the main directory of this archive

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 * for more details.

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 *

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 * (C) 2001 - 2005 Tensilica Inc.

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 */

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#ifndef _XTENSA_CACHE_H

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#define _XTENSA_CACHE_H

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#include <asm/core.h>

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#define L1_CACHE_SHIFT	XCHAL_DCACHE_LINEWIDTH

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#define L1_CACHE_BYTES	XCHAL_DCACHE_LINESIZE

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#define SMP_CACHE_BYTES	L1_CACHE_BYTES

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#define DCACHE_WAY_SIZE	(XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS)

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#define ICACHE_WAY_SIZE	(XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS)

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#define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)

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#define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH)

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/* Maximum cache size per way. */

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#if DCACHE_WAY_SIZE >= ICACHE_WAY_SIZE

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# define CACHE_WAY_SIZE DCACHE_WAY_SIZE

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#else

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# define CACHE_WAY_SIZE ICACHE_WAY_SIZE

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#endif

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#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES

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/*

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 * R/O after init is actually writable, it cannot go to .rodata

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 * according to vmlinux linker script.

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 */

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#define __ro_after_init __read_mostly

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#endif	/* _XTENSA_CACHE_H */

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