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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/arch/xtensa/include/asm/kmem_layout.h
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/*

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 * Kernel virtual memory layout definitions.

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 *

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 * This file is subject to the terms and conditions of the GNU General

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 * Public License.  See the file "COPYING" in the main directory of

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 * this archive for more details.

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 *

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 * Copyright (C) 2016 Cadence Design Systems Inc.

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 */

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#ifndef _XTENSA_KMEM_LAYOUT_H

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#define _XTENSA_KMEM_LAYOUT_H

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#include <asm/core.h>

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#include <asm/types.h>

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#ifdef CONFIG_MMU

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/*

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 * Fixed TLB translations in the processor.

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 */

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#define XCHAL_PAGE_TABLE_VADDR	__XTENSA_UL_CONST(0x80000000)

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#define XCHAL_PAGE_TABLE_SIZE	__XTENSA_UL_CONST(0x00400000)

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#if defined(CONFIG_XTENSA_KSEG_MMU_V2)

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#define XCHAL_KSEG_CACHED_VADDR	__XTENSA_UL_CONST(0xd0000000)

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#define XCHAL_KSEG_BYPASS_VADDR	__XTENSA_UL_CONST(0xd8000000)

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#define XCHAL_KSEG_SIZE		__XTENSA_UL_CONST(0x08000000)

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#define XCHAL_KSEG_ALIGNMENT	__XTENSA_UL_CONST(0x08000000)

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#define XCHAL_KSEG_TLB_WAY	5

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#define XCHAL_KIO_TLB_WAY	6

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#elif defined(CONFIG_XTENSA_KSEG_256M)

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#define XCHAL_KSEG_CACHED_VADDR	__XTENSA_UL_CONST(0xb0000000)

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#define XCHAL_KSEG_BYPASS_VADDR	__XTENSA_UL_CONST(0xc0000000)

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#define XCHAL_KSEG_SIZE		__XTENSA_UL_CONST(0x10000000)

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#define XCHAL_KSEG_ALIGNMENT	__XTENSA_UL_CONST(0x10000000)

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#define XCHAL_KSEG_TLB_WAY	6

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#define XCHAL_KIO_TLB_WAY	6

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#elif defined(CONFIG_XTENSA_KSEG_512M)

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#define XCHAL_KSEG_CACHED_VADDR	__XTENSA_UL_CONST(0xa0000000)

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#define XCHAL_KSEG_BYPASS_VADDR	__XTENSA_UL_CONST(0xc0000000)

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#define XCHAL_KSEG_SIZE		__XTENSA_UL_CONST(0x20000000)

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#define XCHAL_KSEG_ALIGNMENT	__XTENSA_UL_CONST(0x10000000)

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#define XCHAL_KSEG_TLB_WAY	6

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#define XCHAL_KIO_TLB_WAY	6

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#else

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#error Unsupported KSEG configuration

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#endif

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#ifdef CONFIG_KSEG_PADDR

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#define XCHAL_KSEG_PADDR        __XTENSA_UL_CONST(CONFIG_KSEG_PADDR)

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#else

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#define XCHAL_KSEG_PADDR	__XTENSA_UL_CONST(0x00000000)

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#endif

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#if XCHAL_KSEG_PADDR & (XCHAL_KSEG_ALIGNMENT - 1)

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#error XCHAL_KSEG_PADDR is not properly aligned to XCHAL_KSEG_ALIGNMENT

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#endif

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#endif

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/* KIO definition */

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#if XCHAL_HAVE_PTP_MMU

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#define XCHAL_KIO_CACHED_VADDR		0xe0000000

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#define XCHAL_KIO_BYPASS_VADDR		0xf0000000

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#define XCHAL_KIO_DEFAULT_PADDR		0xf0000000

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#else

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#define XCHAL_KIO_BYPASS_VADDR		XCHAL_KIO_PADDR

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#define XCHAL_KIO_DEFAULT_PADDR		0x90000000

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#endif

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#define XCHAL_KIO_SIZE			0x10000000

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#if (!XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY) && defined(CONFIG_USE_OF)

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#define XCHAL_KIO_PADDR			xtensa_get_kio_paddr()

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#ifndef __ASSEMBLER__

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extern unsigned long xtensa_kio_paddr;

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static inline unsigned long xtensa_get_kio_paddr(void)

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{

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	return xtensa_kio_paddr;

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}

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#endif

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#else

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#define XCHAL_KIO_PADDR			XCHAL_KIO_DEFAULT_PADDR

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#endif

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/* KERNEL_STACK definition */

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#ifndef CONFIG_KASAN

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#define KERNEL_STACK_SHIFT	13

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#else

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#define KERNEL_STACK_SHIFT	15

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#endif

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#define KERNEL_STACK_SIZE	(1 << KERNEL_STACK_SHIFT)

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#endif

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