CoCalc -- npu2

GitHub Repository: torvalds/linux
Path: blob/master/drivers/accel/amdxdna/npu2_regs.c
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// SPDX-License-Identifier: GPL-2.0
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/*
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 * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
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 */
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#include <drm/amdxdna_accel.h>
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#include <drm/drm_device.h>
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#include <drm/gpu_scheduler.h>
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#include <linux/sizes.h>
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#include "aie2_pci.h"
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#include "amdxdna_mailbox.h"
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#include "amdxdna_pci_drv.h"
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/* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */
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#define MPNPU_PUB_SEC_INTR             0x3010060
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#define MPNPU_PUB_PWRMGMT_INTR         0x3010064
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#define MPNPU_PUB_SCRATCH0             0x301006C
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#define MPNPU_PUB_SCRATCH1             0x3010070
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#define MPNPU_PUB_SCRATCH2             0x3010074
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#define MPNPU_PUB_SCRATCH3             0x3010078
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#define MPNPU_PUB_SCRATCH4             0x301007C
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#define MPNPU_PUB_SCRATCH5             0x3010080
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#define MPNPU_PUB_SCRATCH6             0x3010084
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#define MPNPU_PUB_SCRATCH7             0x3010088
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#define MPNPU_PUB_SCRATCH8             0x301008C
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#define MPNPU_PUB_SCRATCH9             0x3010090
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#define MPNPU_PUB_SCRATCH10            0x3010094
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#define MPNPU_PUB_SCRATCH11            0x3010098
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#define MPNPU_PUB_SCRATCH12            0x301009C
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#define MPNPU_PUB_SCRATCH13            0x30100A0
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#define MPNPU_PUB_SCRATCH14            0x30100A4
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#define MPNPU_PUB_SCRATCH15            0x30100A8
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#define MP0_C2PMSG_73                  0x3810A24
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#define MP0_C2PMSG_123                 0x3810AEC
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#define MP1_C2PMSG_0                   0x3B10900
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#define MP1_C2PMSG_60                  0x3B109F0
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#define MP1_C2PMSG_61                  0x3B109F4
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#define MPNPU_SRAM_X2I_MAILBOX_0       0x3600000
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#define MPNPU_SRAM_X2I_MAILBOX_15      0x361E000
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#define MPNPU_SRAM_X2I_MAILBOX_31      0x363E000
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#define MPNPU_SRAM_I2X_MAILBOX_31      0x363F000
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#define MMNPU_APERTURE0_BASE           0x3000000
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#define MMNPU_APERTURE1_BASE           0x3600000
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#define MMNPU_APERTURE3_BASE           0x3810000
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#define MMNPU_APERTURE4_BASE           0x3B10000
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/* PCIe BAR Index for NPU2 */
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#define NPU2_REG_BAR_INDEX	0
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#define NPU2_MBOX_BAR_INDEX	0
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#define NPU2_PSP_BAR_INDEX	4
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#define NPU2_SMU_BAR_INDEX	5
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#define NPU2_SRAM_BAR_INDEX	2
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/* Associated BARs and Apertures */
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#define NPU2_REG_BAR_BASE	MMNPU_APERTURE0_BASE
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#define NPU2_MBOX_BAR_BASE	MMNPU_APERTURE0_BASE
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#define NPU2_PSP_BAR_BASE	MMNPU_APERTURE3_BASE
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#define NPU2_SMU_BAR_BASE	MMNPU_APERTURE4_BASE
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#define NPU2_SRAM_BAR_BASE	MMNPU_APERTURE1_BASE
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static const struct amdxdna_dev_priv npu2_dev_priv = {
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	.fw_path        = "amdnpu/17f0_00/npu.sbin",
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	.protocol_major = 0x6,
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	.protocol_minor = 0x6,
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	.rt_config	= npu4_default_rt_cfg,
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	.dpm_clk_tbl	= npu4_dpm_clk_table,
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	.col_align	= COL_ALIGN_NATURE,
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	.mbox_dev_addr  = NPU2_MBOX_BAR_BASE,
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	.mbox_size      = 0, /* Use BAR size */
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	.sram_dev_addr  = NPU2_SRAM_BAR_BASE,
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	.sram_offs      = {
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		DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU2_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
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		DEFINE_BAR_OFFSET(FW_ALIVE_OFF,   NPU2_SRAM, MPNPU_SRAM_X2I_MAILBOX_15),
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	},
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	.psp_regs_off   = {
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		DEFINE_BAR_OFFSET(PSP_CMD_REG,    NPU2_PSP, MP0_C2PMSG_123),
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		DEFINE_BAR_OFFSET(PSP_ARG0_REG,   NPU2_REG, MPNPU_PUB_SCRATCH3),
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		DEFINE_BAR_OFFSET(PSP_ARG1_REG,   NPU2_REG, MPNPU_PUB_SCRATCH4),
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		DEFINE_BAR_OFFSET(PSP_ARG2_REG,   NPU2_REG, MPNPU_PUB_SCRATCH9),
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		DEFINE_BAR_OFFSET(PSP_INTR_REG,   NPU2_PSP, MP0_C2PMSG_73),
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		DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU2_PSP, MP0_C2PMSG_123),
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		DEFINE_BAR_OFFSET(PSP_RESP_REG,   NPU2_REG, MPNPU_PUB_SCRATCH3),
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	},
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	.smu_regs_off   = {
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		DEFINE_BAR_OFFSET(SMU_CMD_REG,  NPU2_SMU, MP1_C2PMSG_0),
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		DEFINE_BAR_OFFSET(SMU_ARG_REG,  NPU2_SMU, MP1_C2PMSG_60),
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		DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU2_SMU, MMNPU_APERTURE4_BASE),
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		DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU2_SMU, MP1_C2PMSG_61),
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		DEFINE_BAR_OFFSET(SMU_OUT_REG,  NPU2_SMU, MP1_C2PMSG_60),
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	},
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	.hw_ops	=	 {
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		.set_dpm = npu4_set_dpm,
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	},
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};
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const struct amdxdna_dev_info dev_npu2_info = {
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	.reg_bar           = NPU2_REG_BAR_INDEX,
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	.mbox_bar          = NPU2_MBOX_BAR_INDEX,
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	.sram_bar          = NPU2_SRAM_BAR_INDEX,
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	.psp_bar           = NPU2_PSP_BAR_INDEX,
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	.smu_bar           = NPU2_SMU_BAR_INDEX,
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	.first_col         = 0,
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	.dev_mem_buf_shift = 15, /* 32 KiB aligned */
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	.dev_mem_base      = AIE2_DEVM_BASE,
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	.dev_mem_size      = AIE2_DEVM_SIZE,
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	.vbnv              = "RyzenAI-npu2",
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	.device_type       = AMDXDNA_DEV_TYPE_KMQ,
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	.dev_priv          = &npu2_dev_priv,
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	.ops               = &aie2_ops, /* NPU2 can share NPU1's callback */
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};
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