Path: blob/master/drivers/accel/habanalabs/gaudi2/gaudi2_security.c
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// SPDX-License-Identifier: GPL-2.012/*3* Copyright 2020-2022 HabanaLabs, Ltd.4* All Rights Reserved.5*/67#include "gaudi2P.h"8#include "../include/gaudi2/asic_reg/gaudi2_regs.h"910#define UNSET_GLBL_SEC_BIT(array, b) ((array)[((b) / 32)] |= (1 << ((b) % 32)))1112#define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_MASK13#define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_MASK14#define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_MASK15#define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_MASK16#define SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_MASK17#define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD \18PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_MASK19#define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR \20PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_MASK21#define SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR \22PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_MASK2324/* LBW RR */25#define SFT_NUM_OF_LBW_RTR 126#define SFT_LBW_RTR_OFFSET 027#define RR_LBW_LONG_MASK 0x7FFFFFFull28#define RR_LBW_SHORT_MASK 0x7FFF000ull2930/* HBW RR */31#define SFT_NUM_OF_HBW_RTR 232#define RR_HBW_SHORT_LO_MASK 0xFFFFFFFF000ull33#define RR_HBW_SHORT_HI_MASK 0xF00000000000ull34#define RR_HBW_LONG_LO_MASK 0xFFFFFFFF000ull35#define RR_HBW_LONG_HI_MASK 0xFFFFF00000000000ull3637struct rr_config {38u64 min;39u64 max;40u32 index;41u8 type;42};4344struct gaudi2_atypical_bp_blocks {45u32 mm_block_base_addr;46u32 block_size;47u32 glbl_sec_offset;48u32 glbl_sec_length;49};5051static const struct gaudi2_atypical_bp_blocks gaudi2_pb_dcr0_sm_objs = {52mmDCORE0_SYNC_MNGR_OBJS_BASE,53128 * 1024,54SM_OBJS_PROT_BITS_OFFS,5564056};5758static const u32 gaudi2_pb_sft0[] = {59mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE,60mmSFT0_HBW_RTR_IF0_RTR_H3_BASE,61mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE,62mmSFT0_HBW_RTR_IF0_ADDR_DEC_HBW_BASE,63mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE,64mmSFT0_HBW_RTR_IF1_RTR_H3_BASE,65mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE,66mmSFT0_HBW_RTR_IF1_ADDR_DEC_HBW_BASE,67mmSFT0_LBW_RTR_IF_RTR_CTRL_BASE,68mmSFT0_LBW_RTR_IF_RTR_H3_BASE,69mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE,70mmSFT0_LBW_RTR_IF_ADDR_DEC_HBW_BASE,71mmSFT0_BASE,72};7374static const u32 gaudi2_pb_dcr0_hif[] = {75mmDCORE0_HIF0_BASE,76};7778static const u32 gaudi2_pb_dcr0_rtr0[] = {79mmDCORE0_RTR0_CTRL_BASE,80mmDCORE0_RTR0_H3_BASE,81mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE,82mmDCORE0_RTR0_ADD_DEC_HBW_BASE,83mmDCORE0_RTR0_BASE,84mmDCORE0_RTR0_DBG_ADDR_BASE,85};8687static const u32 gaudi2_pb_dcr0_hmmu0[] = {88mmDCORE0_HMMU0_MMU_BASE,89mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE,90mmDCORE0_HMMU0_SCRAMB_OUT_BASE,91mmDCORE0_HMMU0_STLB_BASE,92};9394static const u32 gaudi2_pb_cpu_if[] = {95mmCPU_IF_BASE,96};9798static const u32 gaudi2_pb_cpu[] = {99mmCPU_CA53_CFG_BASE,100mmCPU_MSTR_IF_RR_SHRD_HBW_BASE,101};102103static const u32 gaudi2_pb_kdma[] = {104mmARC_FARM_KDMA_BASE,105mmARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_BASE,106};107108static const u32 gaudi2_pb_pdma0[] = {109mmPDMA0_CORE_BASE,110mmPDMA0_MSTR_IF_RR_SHRD_HBW_BASE,111mmPDMA0_QM_BASE,112};113114static const u32 gaudi2_pb_pdma0_arc[] = {115mmPDMA0_QM_ARC_AUX_BASE,116};117118static const struct range gaudi2_pb_pdma0_arc_unsecured_regs[] = {119{mmPDMA0_QM_ARC_AUX_RUN_HALT_REQ, mmPDMA0_QM_ARC_AUX_RUN_HALT_ACK},120{mmPDMA0_QM_ARC_AUX_CLUSTER_NUM, mmPDMA0_QM_ARC_AUX_WAKE_UP_EVENT},121{mmPDMA0_QM_ARC_AUX_ARC_RST_REQ, mmPDMA0_QM_ARC_AUX_CID_OFFSET_7},122{mmPDMA0_QM_ARC_AUX_SCRATCHPAD_0, mmPDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},123{mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},124{mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},125{mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},126{mmPDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, mmPDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},127{mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmPDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},128};129130static const u32 gaudi2_pb_pdma0_unsecured_regs[] = {131mmPDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION,132mmPDMA0_CORE_CTX_WR_COMP_ADDR_HI,133mmPDMA0_CORE_CTX_WR_COMP_ADDR_LO,134mmPDMA0_CORE_CTX_WR_COMP_WDATA,135mmPDMA0_CORE_CTX_SRC_BASE_LO,136mmPDMA0_CORE_CTX_SRC_BASE_HI,137mmPDMA0_CORE_CTX_DST_BASE_LO,138mmPDMA0_CORE_CTX_DST_BASE_HI,139mmPDMA0_CORE_CTX_SRC_TSIZE_0,140mmPDMA0_CORE_CTX_SRC_TSIZE_1,141mmPDMA0_CORE_CTX_SRC_TSIZE_2,142mmPDMA0_CORE_CTX_SRC_TSIZE_3,143mmPDMA0_CORE_CTX_SRC_TSIZE_4,144mmPDMA0_CORE_CTX_SRC_STRIDE_1,145mmPDMA0_CORE_CTX_SRC_STRIDE_2,146mmPDMA0_CORE_CTX_SRC_STRIDE_3,147mmPDMA0_CORE_CTX_SRC_STRIDE_4,148mmPDMA0_CORE_CTX_SRC_OFFSET_LO,149mmPDMA0_CORE_CTX_SRC_OFFSET_HI,150mmPDMA0_CORE_CTX_DST_TSIZE_0,151mmPDMA0_CORE_CTX_DST_TSIZE_1,152mmPDMA0_CORE_CTX_DST_TSIZE_2,153mmPDMA0_CORE_CTX_DST_TSIZE_3,154mmPDMA0_CORE_CTX_DST_TSIZE_4,155mmPDMA0_CORE_CTX_DST_STRIDE_1,156mmPDMA0_CORE_CTX_DST_STRIDE_2,157mmPDMA0_CORE_CTX_DST_STRIDE_3,158mmPDMA0_CORE_CTX_DST_STRIDE_4,159mmPDMA0_CORE_CTX_DST_OFFSET_LO,160mmPDMA0_CORE_CTX_DST_OFFSET_HI,161mmPDMA0_CORE_CTX_COMMIT,162mmPDMA0_CORE_CTX_CTRL,163mmPDMA0_CORE_CTX_TE_NUMROWS,164mmPDMA0_CORE_CTX_IDX,165mmPDMA0_CORE_CTX_IDX_INC,166mmPDMA0_QM_CQ_CFG0_0,167mmPDMA0_QM_CQ_CFG0_1,168mmPDMA0_QM_CQ_CFG0_2,169mmPDMA0_QM_CQ_CFG0_3,170mmPDMA0_QM_CQ_CFG0_4,171mmPDMA0_QM_CP_FENCE0_RDATA_0,172mmPDMA0_QM_CP_FENCE0_RDATA_1,173mmPDMA0_QM_CP_FENCE0_RDATA_2,174mmPDMA0_QM_CP_FENCE0_RDATA_3,175mmPDMA0_QM_CP_FENCE0_RDATA_4,176mmPDMA0_QM_CP_FENCE1_RDATA_0,177mmPDMA0_QM_CP_FENCE1_RDATA_1,178mmPDMA0_QM_CP_FENCE1_RDATA_2,179mmPDMA0_QM_CP_FENCE1_RDATA_3,180mmPDMA0_QM_CP_FENCE1_RDATA_4,181mmPDMA0_QM_CP_FENCE2_RDATA_0,182mmPDMA0_QM_CP_FENCE2_RDATA_1,183mmPDMA0_QM_CP_FENCE2_RDATA_2,184mmPDMA0_QM_CP_FENCE2_RDATA_3,185mmPDMA0_QM_CP_FENCE2_RDATA_4,186mmPDMA0_QM_CP_FENCE3_RDATA_0,187mmPDMA0_QM_CP_FENCE3_RDATA_1,188mmPDMA0_QM_CP_FENCE3_RDATA_2,189mmPDMA0_QM_CP_FENCE3_RDATA_3,190mmPDMA0_QM_CP_FENCE3_RDATA_4,191mmPDMA0_QM_CP_FENCE0_CNT_0,192mmPDMA0_QM_CP_FENCE0_CNT_1,193mmPDMA0_QM_CP_FENCE0_CNT_2,194mmPDMA0_QM_CP_FENCE0_CNT_3,195mmPDMA0_QM_CP_FENCE0_CNT_4,196mmPDMA0_QM_CP_FENCE1_CNT_0,197mmPDMA0_QM_CP_FENCE1_CNT_1,198mmPDMA0_QM_CP_FENCE1_CNT_2,199mmPDMA0_QM_CP_FENCE1_CNT_3,200mmPDMA0_QM_CP_FENCE1_CNT_4,201mmPDMA0_QM_CP_FENCE2_CNT_0,202mmPDMA0_QM_CP_FENCE2_CNT_1,203mmPDMA0_QM_CP_FENCE2_CNT_2,204mmPDMA0_QM_CP_FENCE2_CNT_3,205mmPDMA0_QM_CP_FENCE2_CNT_4,206mmPDMA0_QM_CP_FENCE3_CNT_0,207mmPDMA0_QM_CP_FENCE3_CNT_1,208mmPDMA0_QM_CP_FENCE3_CNT_2,209mmPDMA0_QM_CP_FENCE3_CNT_3,210mmPDMA0_QM_CP_FENCE3_CNT_4,211mmPDMA0_QM_CQ_PTR_LO_0,212mmPDMA0_QM_CQ_PTR_HI_0,213mmPDMA0_QM_CQ_TSIZE_0,214mmPDMA0_QM_CQ_CTL_0,215mmPDMA0_QM_CQ_PTR_LO_1,216mmPDMA0_QM_CQ_PTR_HI_1,217mmPDMA0_QM_CQ_TSIZE_1,218mmPDMA0_QM_CQ_CTL_1,219mmPDMA0_QM_CQ_PTR_LO_2,220mmPDMA0_QM_CQ_PTR_HI_2,221mmPDMA0_QM_CQ_TSIZE_2,222mmPDMA0_QM_CQ_CTL_2,223mmPDMA0_QM_CQ_PTR_LO_3,224mmPDMA0_QM_CQ_PTR_HI_3,225mmPDMA0_QM_CQ_TSIZE_3,226mmPDMA0_QM_CQ_CTL_3,227mmPDMA0_QM_CQ_PTR_LO_4,228mmPDMA0_QM_CQ_PTR_HI_4,229mmPDMA0_QM_CQ_TSIZE_4,230mmPDMA0_QM_CQ_CTL_4,231mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE,232mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,233mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE,234mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,235mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE,236mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,237mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE,238mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,239mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE,240mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,241mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE,242mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,243mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE,244mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,245mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE,246mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,247mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE,248mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,249mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE,250mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,251mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE,252mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,253mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE,254mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,255mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE,256mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,257mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE,258mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,259mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE,260mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,261mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE,262mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,263mmPDMA0_QM_ARC_CQ_PTR_LO,264mmPDMA0_QM_ARC_CQ_PTR_LO_STS,265mmPDMA0_QM_ARC_CQ_PTR_HI,266mmPDMA0_QM_ARC_CQ_PTR_HI_STS,267mmPDMA0_QM_ARB_CFG_0,268mmPDMA0_QM_ARB_MST_QUIET_PER,269mmPDMA0_QM_ARB_CHOICE_Q_PUSH,270mmPDMA0_QM_ARB_WRR_WEIGHT_0,271mmPDMA0_QM_ARB_WRR_WEIGHT_1,272mmPDMA0_QM_ARB_WRR_WEIGHT_2,273mmPDMA0_QM_ARB_WRR_WEIGHT_3,274mmPDMA0_QM_ARB_BASE_LO,275mmPDMA0_QM_ARB_BASE_HI,276mmPDMA0_QM_ARB_MST_SLAVE_EN,277mmPDMA0_QM_ARB_MST_SLAVE_EN_1,278mmPDMA0_QM_ARB_MST_CRED_INC,279mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0,280mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1,281mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2,282mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3,283mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4,284mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5,285mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6,286mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7,287mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8,288mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9,289mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10,290mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11,291mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12,292mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13,293mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14,294mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15,295mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16,296mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17,297mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18,298mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19,299mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20,300mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21,301mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22,302mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23,303mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24,304mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25,305mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26,306mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27,307mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28,308mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29,309mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30,310mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31,311mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32,312mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33,313mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34,314mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35,315mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36,316mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37,317mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38,318mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39,319mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40,320mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41,321mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42,322mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43,323mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44,324mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45,325mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46,326mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47,327mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48,328mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49,329mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50,330mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51,331mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52,332mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53,333mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54,334mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55,335mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56,336mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57,337mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58,338mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59,339mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60,340mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61,341mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62,342mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63,343mmPDMA0_QM_ARB_SLV_ID,344mmPDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST,345mmPDMA0_QM_ARC_CQ_CFG0,346mmPDMA0_QM_CQ_IFIFO_CI_0,347mmPDMA0_QM_CQ_IFIFO_CI_1,348mmPDMA0_QM_CQ_IFIFO_CI_2,349mmPDMA0_QM_CQ_IFIFO_CI_3,350mmPDMA0_QM_CQ_IFIFO_CI_4,351mmPDMA0_QM_ARC_CQ_IFIFO_CI,352mmPDMA0_QM_CQ_CTL_CI_0,353mmPDMA0_QM_CQ_CTL_CI_1,354mmPDMA0_QM_CQ_CTL_CI_2,355mmPDMA0_QM_CQ_CTL_CI_3,356mmPDMA0_QM_CQ_CTL_CI_4,357mmPDMA0_QM_ARC_CQ_CTL_CI,358mmPDMA0_QM_ARC_CQ_TSIZE,359mmPDMA0_QM_ARC_CQ_CTL,360mmPDMA0_QM_CP_SWITCH_WD_SET,361mmPDMA0_QM_CP_EXT_SWITCH,362mmPDMA0_QM_CP_PRED_0,363mmPDMA0_QM_CP_PRED_1,364mmPDMA0_QM_CP_PRED_2,365mmPDMA0_QM_CP_PRED_3,366mmPDMA0_QM_CP_PRED_4,367mmPDMA0_QM_CP_PRED_UPEN_0,368mmPDMA0_QM_CP_PRED_UPEN_1,369mmPDMA0_QM_CP_PRED_UPEN_2,370mmPDMA0_QM_CP_PRED_UPEN_3,371mmPDMA0_QM_CP_PRED_UPEN_4,372mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_0,373mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_1,374mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_2,375mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_3,376mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_4,377mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_0,378mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_1,379mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_2,380mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_3,381mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_4,382mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_0,383mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_1,384mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_2,385mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_3,386mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_4,387mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_0,388mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_1,389mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_2,390mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_3,391mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_4,392mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_0,393mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_1,394mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_2,395mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_3,396mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_4,397mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_0,398mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_1,399mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_2,400mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_3,401mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_4,402mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_0,403mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_1,404mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_2,405mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_3,406mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_4,407mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_0,408mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_1,409mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_2,410mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_3,411mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_4,412mmPDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,413mmPDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO,414mmPDMA0_QM_CQ_IFIFO_MSG_BASE_LO,415mmPDMA0_QM_CQ_CTL_MSG_BASE_LO416};417418static const u32 gaudi2_pb_dcr0_edma0[] = {419mmDCORE0_EDMA0_CORE_BASE,420mmDCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE,421mmDCORE0_EDMA0_QM_BASE,422};423424static const u32 gaudi2_pb_dcr0_edma0_arc[] = {425mmDCORE0_EDMA0_QM_ARC_AUX_BASE,426};427428static const struct range gaudi2_pb_dcr0_edma0_arc_unsecured_regs[] = {429{mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_ACK},430{mmDCORE0_EDMA0_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_EDMA0_QM_ARC_AUX_WAKE_UP_EVENT},431{mmDCORE0_EDMA0_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_7},432{mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_EDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},433{mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN,434mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},435{mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN,436mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},437{mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,438mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},439{mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,440mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},441{mmDCORE0_EDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,442mmDCORE0_EDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},443};444445static const u32 gaudi2_pb_dcr0_edma0_unsecured_regs[] = {446mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION,447mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_HI,448mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_LO,449mmDCORE0_EDMA0_CORE_CTX_WR_COMP_WDATA,450mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_LO,451mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_HI,452mmDCORE0_EDMA0_CORE_CTX_DST_BASE_LO,453mmDCORE0_EDMA0_CORE_CTX_DST_BASE_HI,454mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_0,455mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_1,456mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_2,457mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_3,458mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_4,459mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_1,460mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_2,461mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_3,462mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_4,463mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_LO,464mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_HI,465mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_0,466mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_1,467mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_2,468mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_3,469mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_4,470mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_1,471mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_2,472mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_3,473mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_4,474mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_LO,475mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_HI,476mmDCORE0_EDMA0_CORE_CTX_COMMIT,477mmDCORE0_EDMA0_CORE_CTX_CTRL,478mmDCORE0_EDMA0_CORE_CTX_TE_NUMROWS,479mmDCORE0_EDMA0_CORE_CTX_IDX,480mmDCORE0_EDMA0_CORE_CTX_IDX_INC,481mmDCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND,482mmDCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG,483mmDCORE0_EDMA0_QM_CQ_CFG0_0,484mmDCORE0_EDMA0_QM_CQ_CFG0_1,485mmDCORE0_EDMA0_QM_CQ_CFG0_2,486mmDCORE0_EDMA0_QM_CQ_CFG0_3,487mmDCORE0_EDMA0_QM_CQ_CFG0_4,488mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_0,489mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_1,490mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_2,491mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_3,492mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_4,493mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_0,494mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_1,495mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_2,496mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_3,497mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_4,498mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_0,499mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_1,500mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_2,501mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_3,502mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_4,503mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_0,504mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_1,505mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_2,506mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_3,507mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_4,508mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_0,509mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_1,510mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_2,511mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_3,512mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_4,513mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_0,514mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_1,515mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_2,516mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_3,517mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_4,518mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_0,519mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_1,520mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_2,521mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_3,522mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_4,523mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_0,524mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_1,525mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_2,526mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_3,527mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_4,528mmDCORE0_EDMA0_QM_CQ_PTR_LO_0,529mmDCORE0_EDMA0_QM_CQ_PTR_HI_0,530mmDCORE0_EDMA0_QM_CQ_TSIZE_0,531mmDCORE0_EDMA0_QM_CQ_CTL_0,532mmDCORE0_EDMA0_QM_CQ_PTR_LO_1,533mmDCORE0_EDMA0_QM_CQ_PTR_HI_1,534mmDCORE0_EDMA0_QM_CQ_TSIZE_1,535mmDCORE0_EDMA0_QM_CQ_CTL_1,536mmDCORE0_EDMA0_QM_CQ_PTR_LO_2,537mmDCORE0_EDMA0_QM_CQ_PTR_HI_2,538mmDCORE0_EDMA0_QM_CQ_TSIZE_2,539mmDCORE0_EDMA0_QM_CQ_CTL_2,540mmDCORE0_EDMA0_QM_CQ_PTR_LO_3,541mmDCORE0_EDMA0_QM_CQ_PTR_HI_3,542mmDCORE0_EDMA0_QM_CQ_TSIZE_3,543mmDCORE0_EDMA0_QM_CQ_CTL_3,544mmDCORE0_EDMA0_QM_CQ_PTR_LO_4,545mmDCORE0_EDMA0_QM_CQ_PTR_HI_4,546mmDCORE0_EDMA0_QM_CQ_TSIZE_4,547mmDCORE0_EDMA0_QM_CQ_CTL_4,548mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE,549mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,550mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE,551mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,552mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE,553mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,554mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE,555mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,556mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE,557mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,558mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE,559mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,560mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE,561mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,562mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE,563mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,564mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE,565mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,566mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE,567mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,568mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE,569mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,570mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE,571mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,572mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE,573mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,574mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE,575mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,576mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE,577mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,578mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE,579mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,580mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO,581mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS,582mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI,583mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS,584mmDCORE0_EDMA0_QM_ARB_CFG_0,585mmDCORE0_EDMA0_QM_ARB_MST_QUIET_PER,586mmDCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH,587mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_0,588mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_1,589mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_2,590mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_3,591mmDCORE0_EDMA0_QM_ARB_BASE_LO,592mmDCORE0_EDMA0_QM_ARB_BASE_HI,593mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN,594mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1,595mmDCORE0_EDMA0_QM_ARB_MST_CRED_INC,596mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0,597mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1,598mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2,599mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3,600mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4,601mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5,602mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6,603mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7,604mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8,605mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9,606mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10,607mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11,608mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12,609mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13,610mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14,611mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15,612mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16,613mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17,614mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18,615mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19,616mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20,617mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21,618mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22,619mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23,620mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24,621mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25,622mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26,623mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27,624mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28,625mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29,626mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30,627mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31,628mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32,629mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33,630mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34,631mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35,632mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36,633mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37,634mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38,635mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39,636mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40,637mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41,638mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42,639mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43,640mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44,641mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45,642mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46,643mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47,644mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48,645mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49,646mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50,647mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51,648mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52,649mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53,650mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54,651mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55,652mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56,653mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57,654mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58,655mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59,656mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60,657mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61,658mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62,659mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63,660mmDCORE0_EDMA0_QM_ARB_SLV_ID,661mmDCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST,662mmDCORE0_EDMA0_QM_ARC_CQ_CFG0,663mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_0,664mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_1,665mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_2,666mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_3,667mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_4,668mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI,669mmDCORE0_EDMA0_QM_CQ_CTL_CI_0,670mmDCORE0_EDMA0_QM_CQ_CTL_CI_1,671mmDCORE0_EDMA0_QM_CQ_CTL_CI_2,672mmDCORE0_EDMA0_QM_CQ_CTL_CI_3,673mmDCORE0_EDMA0_QM_CQ_CTL_CI_4,674mmDCORE0_EDMA0_QM_ARC_CQ_CTL_CI,675mmDCORE0_EDMA0_QM_ARC_CQ_TSIZE,676mmDCORE0_EDMA0_QM_ARC_CQ_CTL,677mmDCORE0_EDMA0_QM_CP_SWITCH_WD_SET,678mmDCORE0_EDMA0_QM_CP_EXT_SWITCH,679mmDCORE0_EDMA0_QM_CP_PRED_0,680mmDCORE0_EDMA0_QM_CP_PRED_1,681mmDCORE0_EDMA0_QM_CP_PRED_2,682mmDCORE0_EDMA0_QM_CP_PRED_3,683mmDCORE0_EDMA0_QM_CP_PRED_4,684mmDCORE0_EDMA0_QM_CP_PRED_UPEN_0,685mmDCORE0_EDMA0_QM_CP_PRED_UPEN_1,686mmDCORE0_EDMA0_QM_CP_PRED_UPEN_2,687mmDCORE0_EDMA0_QM_CP_PRED_UPEN_3,688mmDCORE0_EDMA0_QM_CP_PRED_UPEN_4,689mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_0,690mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_1,691mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_2,692mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_3,693mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_4,694mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_0,695mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_1,696mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_2,697mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_3,698mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_4,699mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_0,700mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_1,701mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_2,702mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_3,703mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_4,704mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_0,705mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_1,706mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_2,707mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_3,708mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_4,709mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_0,710mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_1,711mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_2,712mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_3,713mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_4,714mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_0,715mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_1,716mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_2,717mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_3,718mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_4,719mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_0,720mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_1,721mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_2,722mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_3,723mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_4,724mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_0,725mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_1,726mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_2,727mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_3,728mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_4,729mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,730mmDCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO,731mmDCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO,732mmDCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO733};734735static const u32 gaudi2_pb_dcr0_mme_sbte[] = {736mmDCORE0_MME_SBTE0_BASE,737mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE,738};739740static const u32 gaudi2_pb_dcr0_mme_qm[] = {741mmDCORE0_MME_QM_BASE,742};743744static const u32 gaudi2_pb_dcr0_mme_eng[] = {745mmDCORE0_MME_ACC_BASE,746mmDCORE0_MME_CTRL_HI_BASE,747mmDCORE0_MME_CTRL_LO_BASE,748mmDCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE,749mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE,750mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE,751};752753static const u32 gaudi2_pb_dcr0_mme_arc[] = {754mmDCORE0_MME_QM_ARC_AUX_BASE,755mmDCORE0_MME_QM_ARC_DUP_ENG_BASE,756};757758static const struct range gaudi2_pb_dcr0_mme_arc_unsecured_regs[] = {759{mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_ACK},760{mmDCORE0_MME_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_MME_QM_ARC_AUX_WAKE_UP_EVENT},761{mmDCORE0_MME_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_7},762{mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},763{mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN},764{mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN},765{mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,766mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},767{mmDCORE0_MME_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,768mmDCORE0_MME_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},769{mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,770mmDCORE0_MME_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},771{mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_0,772mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_63},773{mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_STRONG_ORDER,774mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_LB_OVRD},775};776777static const u32 gaudi2_pb_dcr0_mme_qm_unsecured_regs[] = {778mmDCORE0_MME_QM_CQ_CFG0_0,779mmDCORE0_MME_QM_CQ_CFG0_1,780mmDCORE0_MME_QM_CQ_CFG0_2,781mmDCORE0_MME_QM_CQ_CFG0_3,782mmDCORE0_MME_QM_CQ_CFG0_4,783mmDCORE0_MME_QM_CP_FENCE0_RDATA_0,784mmDCORE0_MME_QM_CP_FENCE0_RDATA_1,785mmDCORE0_MME_QM_CP_FENCE0_RDATA_2,786mmDCORE0_MME_QM_CP_FENCE0_RDATA_3,787mmDCORE0_MME_QM_CP_FENCE0_RDATA_4,788mmDCORE0_MME_QM_CP_FENCE1_RDATA_0,789mmDCORE0_MME_QM_CP_FENCE1_RDATA_1,790mmDCORE0_MME_QM_CP_FENCE1_RDATA_2,791mmDCORE0_MME_QM_CP_FENCE1_RDATA_3,792mmDCORE0_MME_QM_CP_FENCE1_RDATA_4,793mmDCORE0_MME_QM_CP_FENCE2_RDATA_0,794mmDCORE0_MME_QM_CP_FENCE2_RDATA_1,795mmDCORE0_MME_QM_CP_FENCE2_RDATA_2,796mmDCORE0_MME_QM_CP_FENCE2_RDATA_3,797mmDCORE0_MME_QM_CP_FENCE2_RDATA_4,798mmDCORE0_MME_QM_CP_FENCE3_RDATA_0,799mmDCORE0_MME_QM_CP_FENCE3_RDATA_1,800mmDCORE0_MME_QM_CP_FENCE3_RDATA_2,801mmDCORE0_MME_QM_CP_FENCE3_RDATA_3,802mmDCORE0_MME_QM_CP_FENCE3_RDATA_4,803mmDCORE0_MME_QM_CP_FENCE0_CNT_0,804mmDCORE0_MME_QM_CP_FENCE0_CNT_1,805mmDCORE0_MME_QM_CP_FENCE0_CNT_2,806mmDCORE0_MME_QM_CP_FENCE0_CNT_3,807mmDCORE0_MME_QM_CP_FENCE0_CNT_4,808mmDCORE0_MME_QM_CP_FENCE1_CNT_0,809mmDCORE0_MME_QM_CP_FENCE1_CNT_1,810mmDCORE0_MME_QM_CP_FENCE1_CNT_2,811mmDCORE0_MME_QM_CP_FENCE1_CNT_3,812mmDCORE0_MME_QM_CP_FENCE1_CNT_4,813mmDCORE0_MME_QM_CP_FENCE2_CNT_0,814mmDCORE0_MME_QM_CP_FENCE2_CNT_1,815mmDCORE0_MME_QM_CP_FENCE2_CNT_2,816mmDCORE0_MME_QM_CP_FENCE2_CNT_3,817mmDCORE0_MME_QM_CP_FENCE2_CNT_4,818mmDCORE0_MME_QM_CP_FENCE3_CNT_0,819mmDCORE0_MME_QM_CP_FENCE3_CNT_1,820mmDCORE0_MME_QM_CP_FENCE3_CNT_2,821mmDCORE0_MME_QM_CP_FENCE3_CNT_3,822mmDCORE0_MME_QM_CP_FENCE3_CNT_4,823mmDCORE0_MME_QM_CQ_PTR_LO_0,824mmDCORE0_MME_QM_CQ_PTR_HI_0,825mmDCORE0_MME_QM_CQ_TSIZE_0,826mmDCORE0_MME_QM_CQ_CTL_0,827mmDCORE0_MME_QM_CQ_PTR_LO_1,828mmDCORE0_MME_QM_CQ_PTR_HI_1,829mmDCORE0_MME_QM_CQ_TSIZE_1,830mmDCORE0_MME_QM_CQ_CTL_1,831mmDCORE0_MME_QM_CQ_PTR_LO_2,832mmDCORE0_MME_QM_CQ_PTR_HI_2,833mmDCORE0_MME_QM_CQ_TSIZE_2,834mmDCORE0_MME_QM_CQ_CTL_2,835mmDCORE0_MME_QM_CQ_PTR_LO_3,836mmDCORE0_MME_QM_CQ_PTR_HI_3,837mmDCORE0_MME_QM_CQ_TSIZE_3,838mmDCORE0_MME_QM_CQ_CTL_3,839mmDCORE0_MME_QM_CQ_PTR_LO_4,840mmDCORE0_MME_QM_CQ_PTR_HI_4,841mmDCORE0_MME_QM_CQ_TSIZE_4,842mmDCORE0_MME_QM_CQ_CTL_4,843mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE,844mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,845mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE,846mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,847mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE,848mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,849mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE,850mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,851mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE,852mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,853mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE,854mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,855mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE,856mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,857mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE,858mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,859mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE,860mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,861mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE,862mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,863mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE,864mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,865mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE,866mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,867mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE,868mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,869mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE,870mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,871mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE,872mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,873mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE,874mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,875mmDCORE0_MME_QM_ARC_CQ_PTR_LO,876mmDCORE0_MME_QM_ARC_CQ_PTR_LO_STS,877mmDCORE0_MME_QM_ARC_CQ_PTR_HI,878mmDCORE0_MME_QM_ARC_CQ_PTR_HI_STS,879mmDCORE0_MME_QM_ARB_CFG_0,880mmDCORE0_MME_QM_ARB_MST_QUIET_PER,881mmDCORE0_MME_QM_ARB_CHOICE_Q_PUSH,882mmDCORE0_MME_QM_ARB_WRR_WEIGHT_0,883mmDCORE0_MME_QM_ARB_WRR_WEIGHT_1,884mmDCORE0_MME_QM_ARB_WRR_WEIGHT_2,885mmDCORE0_MME_QM_ARB_WRR_WEIGHT_3,886mmDCORE0_MME_QM_ARB_BASE_LO,887mmDCORE0_MME_QM_ARB_BASE_HI,888mmDCORE0_MME_QM_ARB_MST_SLAVE_EN,889mmDCORE0_MME_QM_ARB_MST_SLAVE_EN_1,890mmDCORE0_MME_QM_ARB_MST_CRED_INC,891mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_0,892mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_1,893mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_2,894mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_3,895mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_4,896mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_5,897mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_6,898mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_7,899mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_8,900mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_9,901mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_10,902mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_11,903mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_12,904mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_13,905mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_14,906mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_15,907mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_16,908mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_17,909mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_18,910mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_19,911mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_20,912mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_21,913mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_22,914mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_23,915mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_24,916mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_25,917mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_26,918mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_27,919mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_28,920mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_29,921mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_30,922mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_31,923mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_32,924mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_33,925mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_34,926mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_35,927mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_36,928mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_37,929mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_38,930mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_39,931mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_40,932mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_41,933mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_42,934mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_43,935mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_44,936mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_45,937mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_46,938mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_47,939mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_48,940mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_49,941mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_50,942mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_51,943mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_52,944mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_53,945mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_54,946mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_55,947mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_56,948mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_57,949mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_58,950mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_59,951mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_60,952mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_61,953mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_62,954mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_63,955mmDCORE0_MME_QM_ARB_SLV_ID,956mmDCORE0_MME_QM_ARB_SLV_MASTER_INC_CRED_OFST,957mmDCORE0_MME_QM_ARC_CQ_CFG0,958mmDCORE0_MME_QM_CQ_IFIFO_CI_0,959mmDCORE0_MME_QM_CQ_IFIFO_CI_1,960mmDCORE0_MME_QM_CQ_IFIFO_CI_2,961mmDCORE0_MME_QM_CQ_IFIFO_CI_3,962mmDCORE0_MME_QM_CQ_IFIFO_CI_4,963mmDCORE0_MME_QM_ARC_CQ_IFIFO_CI,964mmDCORE0_MME_QM_CQ_CTL_CI_0,965mmDCORE0_MME_QM_CQ_CTL_CI_1,966mmDCORE0_MME_QM_CQ_CTL_CI_2,967mmDCORE0_MME_QM_CQ_CTL_CI_3,968mmDCORE0_MME_QM_CQ_CTL_CI_4,969mmDCORE0_MME_QM_ARC_CQ_CTL_CI,970mmDCORE0_MME_QM_ARC_CQ_TSIZE,971mmDCORE0_MME_QM_ARC_CQ_CTL,972mmDCORE0_MME_QM_CP_SWITCH_WD_SET,973mmDCORE0_MME_QM_CP_EXT_SWITCH,974mmDCORE0_MME_QM_CP_PRED_0,975mmDCORE0_MME_QM_CP_PRED_1,976mmDCORE0_MME_QM_CP_PRED_2,977mmDCORE0_MME_QM_CP_PRED_3,978mmDCORE0_MME_QM_CP_PRED_4,979mmDCORE0_MME_QM_CP_PRED_UPEN_0,980mmDCORE0_MME_QM_CP_PRED_UPEN_1,981mmDCORE0_MME_QM_CP_PRED_UPEN_2,982mmDCORE0_MME_QM_CP_PRED_UPEN_3,983mmDCORE0_MME_QM_CP_PRED_UPEN_4,984mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_0,985mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_1,986mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_2,987mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_3,988mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_4,989mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_0,990mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_1,991mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_2,992mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_3,993mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_4,994mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_0,995mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_1,996mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_2,997mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_3,998mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_4,999mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_0,1000mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_1,1001mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_2,1002mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_3,1003mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_4,1004mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_0,1005mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_1,1006mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_2,1007mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_3,1008mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_4,1009mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_0,1010mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_1,1011mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_2,1012mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_3,1013mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_4,1014mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_0,1015mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_1,1016mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_2,1017mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_3,1018mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_4,1019mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_0,1020mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_1,1021mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_2,1022mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_3,1023mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_4,1024mmDCORE0_MME_QM_ARC_CQ_IFIFO_MSG_BASE_LO,1025mmDCORE0_MME_QM_ARC_CQ_CTL_MSG_BASE_LO,1026mmDCORE0_MME_QM_CQ_IFIFO_MSG_BASE_LO,1027mmDCORE0_MME_QM_CQ_CTL_MSG_BASE_LO1028};10291030static const u32 gaudi2_pb_dcr0_mme_eng_unsecured_regs[] = {1031mmDCORE0_MME_CTRL_LO_CMD,1032mmDCORE0_MME_CTRL_LO_AGU,1033mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_0,1034mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_1,1035mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_2,1036mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_3,1037mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_4,1038mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_0,1039mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_1,1040mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_2,1041mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_3,1042mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_4,1043mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_LOW,1044mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_HIGH,1045mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_LOW,1046mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_HIGH,1047mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_MASTER,1048mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_SLAVE,1049mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_KERNEL_SIZE_MINUS_1,1050mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_LOW,1051mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_HIGH,1052mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_OUTER_LOOP,1053mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_NUM_ITERATIONS_MINUS_1,1054mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SB_REPEAT,1055mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_FP8_BIAS,1056mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_RATE_LIMITER,1057mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_USER_DATA,1058mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_IN,1059mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_OUT,1060mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PCU,1061mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ0_ADDR,1062mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ1_ADDR,1063mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_POWER_LOOP,1064mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_MASTER,1065mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_MASTER,1066mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_MASTER,1067mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_MASTER,1068mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_SLAVE,1069mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_SLAVE,1070mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_SLAVE,1071mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_SLAVE,1072mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_WKL_ID,1073mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_0,1074mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_1,1075mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_2,1076mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_3,1077mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_4,1078mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_0,1079mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_1,1080mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_2,1081mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_3,1082mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_4,1083mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_0,1084mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_1,1085mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_2,1086mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_3,1087mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_4,1088mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_0,1089mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_1,1090mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_2,1091mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_3,1092mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_4,1093mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_0,1094mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_1,1095mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_2,1096mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_3,1097mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_4,1098mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_0,1099mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_1,1100mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_2,1101mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_3,1102mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_4,1103mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_0,1104mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_1,1105mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_2,1106mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_3,1107mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_4,1108mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_0,1109mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_1,1110mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_2,1111mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_3,1112mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_4,1113mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_0,1114mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_1,1115mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_2,1116mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_3,1117mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_0,1118mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_1,1119mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_2,1120mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_3,1121mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_0,1122mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_1,1123mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_2,1124mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_3,1125mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_0,1126mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_1,1127mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_2,1128mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_3,1129mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_4,1130mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_LOW,1131mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_HIGH,1132mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_LOW,1133mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_HIGH,1134mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_LOW,1135mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_HIGH,1136mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_LOW,1137mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_HIGH,1138mmDCORE0_MME_CTRL_LO_ARCH_STATUS,1139mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0,1140mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0,1141mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0,1142mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1,1143mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1,1144mmDCORE0_MME_CTRL_LO_ARCH_A_SS,1145mmDCORE0_MME_CTRL_LO_ARCH_B_SS,1146mmDCORE0_MME_CTRL_LO_ARCH_COUT_SS,1147mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_0,1148mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_1,1149mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_2,1150mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_3,1151mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_4,1152mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_0,1153mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_1,1154mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_2,1155mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_3,1156mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_4,1157mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_0,1158mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_1,1159mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_2,1160mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_3,1161mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_4,1162mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_0,1163mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_1,1164mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_2,1165mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_3,1166mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_4,1167mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_0,1168mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_1,1169mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_2,1170mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_3,1171mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_0,1172mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_1,1173mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_2,1174mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_3,1175mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_0,1176mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_1,1177mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_2,1178mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_3,1179mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_BASE,1180mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE,1181mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_BASE,1182mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_BASE,1183mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE,1184mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE,1185mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE,1186mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE,1187mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE,1188mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE,1189mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE,1190mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE,1191mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE,1192mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE,1193mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE,1194mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE,1195mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE,1196mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE,1197mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE,1198mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE,1199mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_0,1200mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_1,1201mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_2,1202mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_3,1203mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_4,1204mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_0,1205mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_1,1206mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_2,1207mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_3,1208mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_4,1209mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_0,1210mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_1,1211mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_2,1212mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_3,1213mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_4,1214mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_0,1215mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_1,1216mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_2,1217mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_3,1218mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_4,1219mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_0,1220mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_1,1221mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_2,1222mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_3,1223mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_0,1224mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_1,1225mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_2,1226mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_3,1227mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_0,1228mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_1,1229mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_2,1230mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_3,1231mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_0,1232mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_1,1233mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_2,1234mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_3,1235mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_4,1236mmDCORE0_MME_ACC_AP_LFSR_POLY,1237mmDCORE0_MME_ACC_AP_LFSR_SEED_WDATA,1238mmDCORE0_MME_ACC_AP_LFSR_SEED_SEL,1239mmDCORE0_MME_ACC_AP_LFSR_SEED_RDATA,1240mmDCORE0_MME_ACC_AP_LFSR_CLOSE_CGATE_DLY,1241mmDCORE0_MME_ACC_WBC_SRC_BP,1242};12431244static const u32 gaudi2_pb_dcr0_tpc0[] = {1245mmDCORE0_TPC0_QM_BASE,1246mmDCORE0_TPC0_CFG_BASE,1247mmDCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_BASE,1248};12491250static const u32 gaudi2_pb_dcr0_tpc0_arc[] = {1251mmDCORE0_TPC0_QM_ARC_AUX_BASE,1252};12531254static const struct range gaudi2_pb_dcr0_tpc0_arc_unsecured_regs[] = {1255{mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_ACK},1256{mmDCORE0_TPC0_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_TPC0_QM_ARC_AUX_WAKE_UP_EVENT},1257{mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_7},1258{mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},1259{mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},1260{mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},1261{mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,1262mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},1263{mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,1264mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},1265{mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,1266mmDCORE0_TPC0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},1267};12681269static const u32 gaudi2_pb_dcr0_tpc0_unsecured_regs[] = {1270mmDCORE0_TPC0_QM_CQ_CFG0_0,1271mmDCORE0_TPC0_QM_CQ_CFG0_1,1272mmDCORE0_TPC0_QM_CQ_CFG0_2,1273mmDCORE0_TPC0_QM_CQ_CFG0_3,1274mmDCORE0_TPC0_QM_CQ_CFG0_4,1275mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_0,1276mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_1,1277mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_2,1278mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_3,1279mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_4,1280mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_0,1281mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_1,1282mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_2,1283mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_3,1284mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_4,1285mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_0,1286mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_1,1287mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_2,1288mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_3,1289mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_4,1290mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_0,1291mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_1,1292mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_2,1293mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_3,1294mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_4,1295mmDCORE0_TPC0_QM_CP_FENCE0_CNT_0,1296mmDCORE0_TPC0_QM_CP_FENCE0_CNT_1,1297mmDCORE0_TPC0_QM_CP_FENCE0_CNT_2,1298mmDCORE0_TPC0_QM_CP_FENCE0_CNT_3,1299mmDCORE0_TPC0_QM_CP_FENCE0_CNT_4,1300mmDCORE0_TPC0_QM_CP_FENCE1_CNT_0,1301mmDCORE0_TPC0_QM_CP_FENCE1_CNT_1,1302mmDCORE0_TPC0_QM_CP_FENCE1_CNT_2,1303mmDCORE0_TPC0_QM_CP_FENCE1_CNT_3,1304mmDCORE0_TPC0_QM_CP_FENCE1_CNT_4,1305mmDCORE0_TPC0_QM_CP_FENCE2_CNT_0,1306mmDCORE0_TPC0_QM_CP_FENCE2_CNT_1,1307mmDCORE0_TPC0_QM_CP_FENCE2_CNT_2,1308mmDCORE0_TPC0_QM_CP_FENCE2_CNT_3,1309mmDCORE0_TPC0_QM_CP_FENCE2_CNT_4,1310mmDCORE0_TPC0_QM_CP_FENCE3_CNT_0,1311mmDCORE0_TPC0_QM_CP_FENCE3_CNT_1,1312mmDCORE0_TPC0_QM_CP_FENCE3_CNT_2,1313mmDCORE0_TPC0_QM_CP_FENCE3_CNT_3,1314mmDCORE0_TPC0_QM_CP_FENCE3_CNT_4,1315mmDCORE0_TPC0_QM_CQ_PTR_LO_0,1316mmDCORE0_TPC0_QM_CQ_PTR_HI_0,1317mmDCORE0_TPC0_QM_CQ_TSIZE_0,1318mmDCORE0_TPC0_QM_CQ_CTL_0,1319mmDCORE0_TPC0_QM_CQ_PTR_LO_1,1320mmDCORE0_TPC0_QM_CQ_PTR_HI_1,1321mmDCORE0_TPC0_QM_CQ_TSIZE_1,1322mmDCORE0_TPC0_QM_CQ_CTL_1,1323mmDCORE0_TPC0_QM_CQ_PTR_LO_2,1324mmDCORE0_TPC0_QM_CQ_PTR_HI_2,1325mmDCORE0_TPC0_QM_CQ_TSIZE_2,1326mmDCORE0_TPC0_QM_CQ_CTL_2,1327mmDCORE0_TPC0_QM_CQ_PTR_LO_3,1328mmDCORE0_TPC0_QM_CQ_PTR_HI_3,1329mmDCORE0_TPC0_QM_CQ_TSIZE_3,1330mmDCORE0_TPC0_QM_CQ_CTL_3,1331mmDCORE0_TPC0_QM_CQ_PTR_LO_4,1332mmDCORE0_TPC0_QM_CQ_PTR_HI_4,1333mmDCORE0_TPC0_QM_CQ_TSIZE_4,1334mmDCORE0_TPC0_QM_CQ_CTL_4,1335mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE,1336mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,1337mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE,1338mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,1339mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE,1340mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,1341mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE,1342mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,1343mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE,1344mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,1345mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE,1346mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,1347mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE,1348mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,1349mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE,1350mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,1351mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE,1352mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,1353mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE,1354mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,1355mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE,1356mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,1357mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE,1358mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,1359mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE,1360mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,1361mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE,1362mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,1363mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE,1364mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,1365mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE,1366mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,1367mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO,1368mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO_STS,1369mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI,1370mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI_STS,1371mmDCORE0_TPC0_QM_ARB_CFG_0,1372mmDCORE0_TPC0_QM_ARB_MST_QUIET_PER,1373mmDCORE0_TPC0_QM_ARB_CHOICE_Q_PUSH,1374mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_0,1375mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_1,1376mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_2,1377mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_3,1378mmDCORE0_TPC0_QM_ARB_BASE_LO,1379mmDCORE0_TPC0_QM_ARB_BASE_HI,1380mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN,1381mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN_1,1382mmDCORE0_TPC0_QM_ARB_MST_CRED_INC,1383mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_0,1384mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_1,1385mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_2,1386mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_3,1387mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_4,1388mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_5,1389mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_6,1390mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_7,1391mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_8,1392mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_9,1393mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_10,1394mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_11,1395mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_12,1396mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_13,1397mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_14,1398mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_15,1399mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_16,1400mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_17,1401mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_18,1402mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_19,1403mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_20,1404mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_21,1405mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_22,1406mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_23,1407mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_24,1408mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_25,1409mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_26,1410mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_27,1411mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_28,1412mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_29,1413mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_30,1414mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_31,1415mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_32,1416mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_33,1417mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_34,1418mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_35,1419mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_36,1420mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_37,1421mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_38,1422mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_39,1423mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_40,1424mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_41,1425mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_42,1426mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_43,1427mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_44,1428mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_45,1429mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_46,1430mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_47,1431mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_48,1432mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_49,1433mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_50,1434mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_51,1435mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_52,1436mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_53,1437mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_54,1438mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_55,1439mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_56,1440mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_57,1441mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_58,1442mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_59,1443mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_60,1444mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_61,1445mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_62,1446mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_63,1447mmDCORE0_TPC0_QM_ARB_SLV_ID,1448mmDCORE0_TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST,1449mmDCORE0_TPC0_QM_ARC_CQ_CFG0,1450mmDCORE0_TPC0_QM_CQ_IFIFO_CI_0,1451mmDCORE0_TPC0_QM_CQ_IFIFO_CI_1,1452mmDCORE0_TPC0_QM_CQ_IFIFO_CI_2,1453mmDCORE0_TPC0_QM_CQ_IFIFO_CI_3,1454mmDCORE0_TPC0_QM_CQ_IFIFO_CI_4,1455mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_CI,1456mmDCORE0_TPC0_QM_CQ_CTL_CI_0,1457mmDCORE0_TPC0_QM_CQ_CTL_CI_1,1458mmDCORE0_TPC0_QM_CQ_CTL_CI_2,1459mmDCORE0_TPC0_QM_CQ_CTL_CI_3,1460mmDCORE0_TPC0_QM_CQ_CTL_CI_4,1461mmDCORE0_TPC0_QM_ARC_CQ_CTL_CI,1462mmDCORE0_TPC0_QM_ARC_CQ_TSIZE,1463mmDCORE0_TPC0_QM_ARC_CQ_CTL,1464mmDCORE0_TPC0_QM_CP_SWITCH_WD_SET,1465mmDCORE0_TPC0_QM_CP_EXT_SWITCH,1466mmDCORE0_TPC0_QM_CP_PRED_0,1467mmDCORE0_TPC0_QM_CP_PRED_1,1468mmDCORE0_TPC0_QM_CP_PRED_2,1469mmDCORE0_TPC0_QM_CP_PRED_3,1470mmDCORE0_TPC0_QM_CP_PRED_4,1471mmDCORE0_TPC0_QM_CP_PRED_UPEN_0,1472mmDCORE0_TPC0_QM_CP_PRED_UPEN_1,1473mmDCORE0_TPC0_QM_CP_PRED_UPEN_2,1474mmDCORE0_TPC0_QM_CP_PRED_UPEN_3,1475mmDCORE0_TPC0_QM_CP_PRED_UPEN_4,1476mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_0,1477mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_1,1478mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_2,1479mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_3,1480mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_4,1481mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_0,1482mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_1,1483mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_2,1484mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_3,1485mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_4,1486mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_0,1487mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_1,1488mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_2,1489mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_3,1490mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_4,1491mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_0,1492mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_1,1493mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_2,1494mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_3,1495mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_4,1496mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_0,1497mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_1,1498mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_2,1499mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_3,1500mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_4,1501mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_0,1502mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_1,1503mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_2,1504mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_3,1505mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_4,1506mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_0,1507mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_1,1508mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_2,1509mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_3,1510mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_4,1511mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_0,1512mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_1,1513mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_2,1514mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_3,1515mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_4,1516mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,1517mmDCORE0_TPC0_QM_ARC_CQ_CTL_MSG_BASE_LO,1518mmDCORE0_TPC0_QM_CQ_IFIFO_MSG_BASE_LO,1519mmDCORE0_TPC0_QM_CQ_CTL_MSG_BASE_LO,1520mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_MESSAGE,1521mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_ADDR,1522mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW,1523mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH,1524mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_0,1525mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_0,1526mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_1,1527mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_1,1528mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_2,1529mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_2,1530mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_3,1531mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_3,1532mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_4,1533mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_4,1534mmDCORE0_TPC0_CFG_QM_KERNEL_CONFIG,1535mmDCORE0_TPC0_CFG_QM_KERNEL_ID,1536mmDCORE0_TPC0_CFG_QM_POWER_LOOP,1537mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_0,1538mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_1,1539mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_2,1540mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_3,1541mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO,1542mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI,1543mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO,1544mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI,1545mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO,1546mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI,1547mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO,1548mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI,1549mmDCORE0_TPC0_CFG_FP8_143_BIAS,1550mmDCORE0_TPC0_CFG_ROUND_CSR,1551mmDCORE0_TPC0_CFG_CONV_ROUND_CSR,1552mmDCORE0_TPC0_CFG_SEMAPHORE,1553mmDCORE0_TPC0_CFG_LFSR_POLYNOM,1554mmDCORE0_TPC0_CFG_STATUS,1555mmDCORE0_TPC0_CFG_TPC_CMD,1556mmDCORE0_TPC0_CFG_TPC_EXECUTE,1557mmDCORE0_TPC0_CFG_TPC_DCACHE_L0CD,1558mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW,1559mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH,1560mmDCORE0_TPC0_CFG_RD_RATE_LIMIT,1561mmDCORE0_TPC0_CFG_WR_RATE_LIMIT,1562mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO,1563mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI,1564mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO,1565mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI,1566mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO,1567mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI,1568mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO,1569mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI,1570mmDCORE0_TPC0_CFG_KERNEL_KERNEL_CONFIG,1571mmDCORE0_TPC0_CFG_KERNEL_SRF_0,1572mmDCORE0_TPC0_CFG_KERNEL_SRF_1,1573mmDCORE0_TPC0_CFG_KERNEL_SRF_2,1574mmDCORE0_TPC0_CFG_KERNEL_SRF_3,1575mmDCORE0_TPC0_CFG_KERNEL_SRF_4,1576mmDCORE0_TPC0_CFG_KERNEL_SRF_5,1577mmDCORE0_TPC0_CFG_KERNEL_SRF_6,1578mmDCORE0_TPC0_CFG_KERNEL_SRF_7,1579mmDCORE0_TPC0_CFG_KERNEL_SRF_8,1580mmDCORE0_TPC0_CFG_KERNEL_SRF_9,1581mmDCORE0_TPC0_CFG_KERNEL_SRF_10,1582mmDCORE0_TPC0_CFG_KERNEL_SRF_11,1583mmDCORE0_TPC0_CFG_KERNEL_SRF_12,1584mmDCORE0_TPC0_CFG_KERNEL_SRF_13,1585mmDCORE0_TPC0_CFG_KERNEL_SRF_14,1586mmDCORE0_TPC0_CFG_KERNEL_SRF_15,1587mmDCORE0_TPC0_CFG_KERNEL_SRF_16,1588mmDCORE0_TPC0_CFG_KERNEL_SRF_17,1589mmDCORE0_TPC0_CFG_KERNEL_SRF_18,1590mmDCORE0_TPC0_CFG_KERNEL_SRF_19,1591mmDCORE0_TPC0_CFG_KERNEL_SRF_20,1592mmDCORE0_TPC0_CFG_KERNEL_SRF_21,1593mmDCORE0_TPC0_CFG_KERNEL_SRF_22,1594mmDCORE0_TPC0_CFG_KERNEL_SRF_23,1595mmDCORE0_TPC0_CFG_KERNEL_SRF_24,1596mmDCORE0_TPC0_CFG_KERNEL_SRF_25,1597mmDCORE0_TPC0_CFG_KERNEL_SRF_26,1598mmDCORE0_TPC0_CFG_KERNEL_SRF_27,1599mmDCORE0_TPC0_CFG_KERNEL_SRF_28,1600mmDCORE0_TPC0_CFG_KERNEL_SRF_29,1601mmDCORE0_TPC0_CFG_KERNEL_SRF_30,1602mmDCORE0_TPC0_CFG_KERNEL_SRF_31,1603mmDCORE0_TPC0_CFG_TPC_SB_L0CD,1604mmDCORE0_TPC0_CFG_TPC_COUNT,1605mmDCORE0_TPC0_CFG_TPC_ID,1606mmDCORE0_TPC0_CFG_QM_KERNEL_ID_INC,1607mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_0,1608mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_1,1609mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_2,1610mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_3,1611mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_4,1612mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_0,1613mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_1,1614mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_2,1615mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_31616};16171618static const u32 gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs[] = {1619mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW,1620mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH,1621mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE,1622mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG,1623mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE,1624mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE,1625mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE,1626mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE,1627mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE,1628mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE,1629mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE,1630mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE,1631mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE,1632mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE,1633mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PREF_STRIDE,1634mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH,1635mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH,1636mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH,1637mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH,1638mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH,1639};16401641static const u32 gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs[] = {1642mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW,1643mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH,1644mmDCORE0_TPC0_CFG_QM_TENSOR_0_PADDING_VALUE,1645mmDCORE0_TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG,1646mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE,1647mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE,1648mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE,1649mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE,1650mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE,1651mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE,1652mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE,1653mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE,1654mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE,1655mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE,1656mmDCORE0_TPC0_CFG_QM_TENSOR_0_PREF_STRIDE,1657mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH,1658mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH,1659mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH,1660mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH,1661mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH,1662};16631664static const u32 gaudi2_pb_dcr0_sram0[] = {1665mmDCORE0_SRAM0_BANK_BASE,1666mmDCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE,1667mmDCORE0_SRAM0_RTR_BASE,1668};16691670static const u32 gaudi2_pb_dcr0_sm_mstr_if[] = {1671mmDCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE,1672};16731674static const u32 gaudi2_pb_dcr0_sm_glbl[] = {1675mmDCORE0_SYNC_MNGR_GLBL_BASE,1676};16771678static const u32 gaudi2_pb_dcr1_sm_glbl[] = {1679mmDCORE1_SYNC_MNGR_GLBL_BASE,1680};16811682static const struct range gaudi2_pb_dcr0_sm_glbl_unsecured_regs[] = {1683{mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63},1684{mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63},1685{mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63},1686{mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_63},1687{mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_63},1688{mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_63},1689{mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_63},1690{mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_63},1691};16921693static const struct range gaudi2_pb_dcr_x_sm_glbl_unsecured_regs[] = {1694{mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63},1695{mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63},1696{mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63},1697{mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_63},1698{mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_0, mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_63},1699{mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_0, mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_63},1700{mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_0, mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_63},1701{mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_63},1702};17031704static const u32 gaudi2_pb_arc_sched[] = {1705mmARC_FARM_ARC0_AUX_BASE,1706mmARC_FARM_ARC0_DUP_ENG_BASE,1707mmARC_FARM_ARC0_ACP_ENG_BASE,1708};17091710static const struct range gaudi2_pb_arc_sched_unsecured_regs[] = {1711{mmARC_FARM_ARC0_AUX_RUN_HALT_REQ, mmARC_FARM_ARC0_AUX_RUN_HALT_ACK},1712{mmARC_FARM_ARC0_AUX_CLUSTER_NUM, mmARC_FARM_ARC0_AUX_WAKE_UP_EVENT},1713{mmARC_FARM_ARC0_AUX_ARC_RST_REQ, mmARC_FARM_ARC0_AUX_CID_OFFSET_7},1714{mmARC_FARM_ARC0_AUX_SCRATCHPAD_0, mmARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT},1715{mmARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN, mmARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN},1716{mmARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN, mmARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN},1717{mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_0, mmARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG},1718{mmARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT, mmARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI},1719{mmARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN},1720{mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_0, mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_63},1721{mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_STRONG_ORDER, mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_OVRD},1722{mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_0, mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_REG},1723};17241725static const u32 gaudi2_pb_xbar_mid[] = {1726mmXBAR_MID_0_BASE,1727};17281729static const u32 gaudi2_pb_xbar_mid_unsecured_regs[] = {1730mmXBAR_MID_0_UPSCALE,1731mmXBAR_MID_0_DOWN_CONV,1732mmXBAR_MID_0_DOWN_CONV_LFSR_EN,1733mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VLD,1734mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VALUE,1735mmXBAR_MID_0_DOWN_CONV_LFSR_CFG_POLY,1736};17371738static const u32 gaudi2_pb_xbar_edge[] = {1739mmXBAR_EDGE_0_BASE,1740};17411742static const u32 gaudi2_pb_xbar_edge_unsecured_regs[] = {1743mmXBAR_EDGE_0_UPSCALE,1744mmXBAR_EDGE_0_DOWN_CONV,1745mmXBAR_EDGE_0_DOWN_CONV_LFSR_EN,1746mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VLD,1747mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VALUE,1748mmXBAR_EDGE_0_DOWN_CONV_LFSR_CFG_POLY,1749};17501751static const u32 gaudi2_pb_nic0[] = {1752mmNIC0_TMR_BASE,1753mmNIC0_RXB_CORE_BASE,1754mmNIC0_RXE0_BASE,1755mmNIC0_RXE1_BASE,1756mmNIC0_RXE0_AXUSER_AXUSER_CQ0_BASE,1757mmNIC0_RXE1_AXUSER_AXUSER_CQ0_BASE,1758mmNIC0_TXS0_BASE,1759mmNIC0_TXS1_BASE,1760mmNIC0_TXE0_BASE,1761mmNIC0_TXE1_BASE,1762mmNIC0_TXB_BASE,1763mmNIC0_MSTR_IF_RR_SHRD_HBW_BASE,1764};17651766static const u32 gaudi2_pb_nic0_qm_qpc[] = {1767mmNIC0_QM0_BASE,1768mmNIC0_QPC0_BASE,1769};17701771static const u32 gaudi2_pb_nic0_qm_arc_aux0[] = {1772mmNIC0_QM_ARC_AUX0_BASE,1773};17741775static const struct range gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs[] = {1776{mmNIC0_QM_ARC_AUX0_RUN_HALT_REQ, mmNIC0_QM_ARC_AUX0_RUN_HALT_ACK},1777{mmNIC0_QM_ARC_AUX0_CLUSTER_NUM, mmNIC0_QM_ARC_AUX0_WAKE_UP_EVENT},1778{mmNIC0_QM_ARC_AUX0_ARC_RST_REQ, mmNIC0_QM_ARC_AUX0_CID_OFFSET_7},1779{mmNIC0_QM_ARC_AUX0_SCRATCHPAD_0, mmNIC0_QM_ARC_AUX0_INFLIGHT_LBU_RD_CNT},1780{mmNIC0_QM_ARC_AUX0_CBU_EARLY_BRESP_EN, mmNIC0_QM_ARC_AUX0_CBU_EARLY_BRESP_EN},1781{mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN, mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN},1782{mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_0, mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_ALERT_MSG},1783{mmNIC0_QM_ARC_AUX0_DCCM_Q_PUSH_FIFO_CNT, mmNIC0_QM_ARC_AUX0_QMAN_ARC_CQ_SHADOW_CI},1784{mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_WR_IF_CNT, mmNIC0_QM_ARC_AUX0_MME_ARC_UPPER_DCCM_EN},1785};17861787static const u32 gaudi2_pb_nic0_umr[] = {1788mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE,1789mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 1, /* UMR0_1 */1790mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 2, /* UMR0_2 */1791mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 3, /* UMR0_3 */1792mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 4, /* UMR0_4 */1793mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 5, /* UMR0_5 */1794mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 6, /* UMR0_6 */1795mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 7, /* UMR0_7 */1796mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 8, /* UMR0_8 */1797mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 9, /* UMR0_9 */1798mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 10, /* UMR0_10 */1799mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 11, /* UMR0_11 */1800mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 12, /* UMR0_12 */1801mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 13, /* UMR0_13 */1802mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 14, /* UMR0_14 */1803};18041805static const struct range gaudi2_pb_nic0_umr_unsecured_regs[] = {1806{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32,1807mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX},1808{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 1, /* UMR0_1 */1809mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 1},1810{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 2, /* UMR0_2 */1811mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 2},1812{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 3, /* UMR0_3 */1813mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 3},1814{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 4, /* UMR0_4 */1815mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 4},1816{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 5, /* UMR0_5 */1817mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 5},1818{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 6, /* UMR0_6 */1819mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 6},1820{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 7, /* UMR0_7 */1821mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 7},1822{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 8, /* UMR0_8 */1823mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 8},1824{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 9, /* UMR0_9 */1825mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 9},1826{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 10, /* UMR0_10 */1827mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 10},1828{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 11, /* UMR0_11 */1829mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 11},1830{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 12, /* UMR0_12 */1831mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 12},1832{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 13, /* UMR0_13 */1833mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 13},1834{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 14, /* UMR0_14 */1835mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 14},1836};18371838/*1839* mmNIC0_QPC0_LINEAR_WQE_QPN and mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN are 32-bit1840* registers and since the user writes in bulks of 64 bits we need to un-secure1841* also the following 32 bits (that's why we added also the next 4 bytes to the1842* table). In the RTL, as part of ECO (2874), writing to the next 4 bytes1843* triggers a write to the SPECIAL_GLBL_SPARE register, hence it's must be1844* unsecured as well.1845*/1846#define mmNIC0_QPC0_LINEAR_WQE_RSV (mmNIC0_QPC0_LINEAR_WQE_QPN + 4)1847#define mmNIC0_QPC0_MULTI_STRIDE_WQE_RSV (mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN + 4)1848#define mmNIC0_QPC0_SPECIAL_GLBL_SPARE 0x541FF6018491850static const u32 gaudi2_pb_nic0_qm_qpc_unsecured_regs[] = {1851mmNIC0_QPC0_LINEAR_WQE_STATIC_0,1852mmNIC0_QPC0_LINEAR_WQE_STATIC_1,1853mmNIC0_QPC0_LINEAR_WQE_STATIC_2,1854mmNIC0_QPC0_LINEAR_WQE_STATIC_3,1855mmNIC0_QPC0_LINEAR_WQE_STATIC_4,1856mmNIC0_QPC0_LINEAR_WQE_STATIC_5,1857mmNIC0_QPC0_LINEAR_WQE_STATIC_6,1858mmNIC0_QPC0_LINEAR_WQE_STATIC_7,1859mmNIC0_QPC0_LINEAR_WQE_STATIC_8,1860mmNIC0_QPC0_LINEAR_WQE_STATIC_9,1861mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_0,1862mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_1,1863mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_2,1864mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_3,1865mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_4,1866mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_5,1867mmNIC0_QPC0_LINEAR_WQE_QPN,1868mmNIC0_QPC0_LINEAR_WQE_RSV,1869mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_0,1870mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_1,1871mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_2,1872mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_3,1873mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_4,1874mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_5,1875mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_6,1876mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_7,1877mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_8,1878mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_9,1879mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_10,1880mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_11,1881mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_12,1882mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_13,1883mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_14,1884mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_15,1885mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_16,1886mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_17,1887mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_0,1888mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_1,1889mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_2,1890mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_3,1891mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_4,1892mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_5,1893mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN,1894mmNIC0_QPC0_MULTI_STRIDE_WQE_RSV,1895mmNIC0_QPC0_QMAN_DOORBELL,1896mmNIC0_QPC0_QMAN_DOORBELL_QPN,1897mmNIC0_QPC0_SPECIAL_GLBL_SPARE,1898mmNIC0_QM0_CQ_CFG0_0,1899mmNIC0_QM0_CQ_CFG0_1,1900mmNIC0_QM0_CQ_CFG0_2,1901mmNIC0_QM0_CQ_CFG0_3,1902mmNIC0_QM0_CQ_CFG0_4,1903mmNIC0_QM0_CP_FENCE0_RDATA_0,1904mmNIC0_QM0_CP_FENCE0_RDATA_1,1905mmNIC0_QM0_CP_FENCE0_RDATA_2,1906mmNIC0_QM0_CP_FENCE0_RDATA_3,1907mmNIC0_QM0_CP_FENCE0_RDATA_4,1908mmNIC0_QM0_CP_FENCE1_RDATA_0,1909mmNIC0_QM0_CP_FENCE1_RDATA_1,1910mmNIC0_QM0_CP_FENCE1_RDATA_2,1911mmNIC0_QM0_CP_FENCE1_RDATA_3,1912mmNIC0_QM0_CP_FENCE1_RDATA_4,1913mmNIC0_QM0_CP_FENCE2_RDATA_0,1914mmNIC0_QM0_CP_FENCE2_RDATA_1,1915mmNIC0_QM0_CP_FENCE2_RDATA_2,1916mmNIC0_QM0_CP_FENCE2_RDATA_3,1917mmNIC0_QM0_CP_FENCE2_RDATA_4,1918mmNIC0_QM0_CP_FENCE3_RDATA_0,1919mmNIC0_QM0_CP_FENCE3_RDATA_1,1920mmNIC0_QM0_CP_FENCE3_RDATA_2,1921mmNIC0_QM0_CP_FENCE3_RDATA_3,1922mmNIC0_QM0_CP_FENCE3_RDATA_4,1923mmNIC0_QM0_CP_FENCE0_CNT_0,1924mmNIC0_QM0_CP_FENCE0_CNT_1,1925mmNIC0_QM0_CP_FENCE0_CNT_2,1926mmNIC0_QM0_CP_FENCE0_CNT_3,1927mmNIC0_QM0_CP_FENCE0_CNT_4,1928mmNIC0_QM0_CP_FENCE1_CNT_0,1929mmNIC0_QM0_CP_FENCE1_CNT_1,1930mmNIC0_QM0_CP_FENCE1_CNT_2,1931mmNIC0_QM0_CP_FENCE1_CNT_3,1932mmNIC0_QM0_CP_FENCE1_CNT_4,1933mmNIC0_QM0_CP_FENCE2_CNT_0,1934mmNIC0_QM0_CP_FENCE2_CNT_1,1935mmNIC0_QM0_CP_FENCE2_CNT_2,1936mmNIC0_QM0_CP_FENCE2_CNT_3,1937mmNIC0_QM0_CP_FENCE2_CNT_4,1938mmNIC0_QM0_CP_FENCE3_CNT_0,1939mmNIC0_QM0_CP_FENCE3_CNT_1,1940mmNIC0_QM0_CP_FENCE3_CNT_2,1941mmNIC0_QM0_CP_FENCE3_CNT_3,1942mmNIC0_QM0_CP_FENCE3_CNT_4,1943mmNIC0_QM0_CQ_PTR_LO_0,1944mmNIC0_QM0_CQ_PTR_HI_0,1945mmNIC0_QM0_CQ_TSIZE_0,1946mmNIC0_QM0_CQ_CTL_0,1947mmNIC0_QM0_CQ_PTR_LO_1,1948mmNIC0_QM0_CQ_PTR_HI_1,1949mmNIC0_QM0_CQ_TSIZE_1,1950mmNIC0_QM0_CQ_CTL_1,1951mmNIC0_QM0_CQ_PTR_LO_2,1952mmNIC0_QM0_CQ_PTR_HI_2,1953mmNIC0_QM0_CQ_TSIZE_2,1954mmNIC0_QM0_CQ_CTL_2,1955mmNIC0_QM0_CQ_PTR_LO_3,1956mmNIC0_QM0_CQ_PTR_HI_3,1957mmNIC0_QM0_CQ_TSIZE_3,1958mmNIC0_QM0_CQ_CTL_3,1959mmNIC0_QM0_CQ_PTR_LO_4,1960mmNIC0_QM0_CQ_PTR_HI_4,1961mmNIC0_QM0_CQ_TSIZE_4,1962mmNIC0_QM0_CQ_CTL_4,1963mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE,1964mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE + 4,1965mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE,1966mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE + 4,1967mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE,1968mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE + 4,1969mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE,1970mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE + 4,1971mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE,1972mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE + 4,1973mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE,1974mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE + 4,1975mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE,1976mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE + 4,1977mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE,1978mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE + 4,1979mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE,1980mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE + 4,1981mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE,1982mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE + 4,1983mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE,1984mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE + 4,1985mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE,1986mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE + 4,1987mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE,1988mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE + 4,1989mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE,1990mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE + 4,1991mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE,1992mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE + 4,1993mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE,1994mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE + 4,1995mmNIC0_QM0_ARC_CQ_PTR_LO,1996mmNIC0_QM0_ARC_CQ_PTR_LO_STS,1997mmNIC0_QM0_ARC_CQ_PTR_HI,1998mmNIC0_QM0_ARC_CQ_PTR_HI_STS,1999mmNIC0_QM0_ARB_CFG_0,2000mmNIC0_QM0_ARB_MST_QUIET_PER,2001mmNIC0_QM0_ARB_CHOICE_Q_PUSH,2002mmNIC0_QM0_ARB_WRR_WEIGHT_0,2003mmNIC0_QM0_ARB_WRR_WEIGHT_1,2004mmNIC0_QM0_ARB_WRR_WEIGHT_2,2005mmNIC0_QM0_ARB_WRR_WEIGHT_3,2006mmNIC0_QM0_ARB_BASE_LO,2007mmNIC0_QM0_ARB_BASE_HI,2008mmNIC0_QM0_ARB_MST_SLAVE_EN,2009mmNIC0_QM0_ARB_MST_SLAVE_EN_1,2010mmNIC0_QM0_ARB_MST_CRED_INC,2011mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_0,2012mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_1,2013mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_2,2014mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_3,2015mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_4,2016mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_5,2017mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_6,2018mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_7,2019mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_8,2020mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_9,2021mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_10,2022mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_11,2023mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_12,2024mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_13,2025mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_14,2026mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_15,2027mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_16,2028mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_17,2029mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_18,2030mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_19,2031mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_20,2032mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_21,2033mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_22,2034mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_23,2035mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_24,2036mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_25,2037mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_26,2038mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_27,2039mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_28,2040mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_29,2041mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_30,2042mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_31,2043mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_32,2044mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_33,2045mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_34,2046mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_35,2047mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_36,2048mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_37,2049mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_38,2050mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_39,2051mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_40,2052mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_41,2053mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_42,2054mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_43,2055mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_44,2056mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_45,2057mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_46,2058mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_47,2059mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_48,2060mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_49,2061mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_50,2062mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_51,2063mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_52,2064mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_53,2065mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_54,2066mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_55,2067mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_56,2068mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_57,2069mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_58,2070mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_59,2071mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_60,2072mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_61,2073mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_62,2074mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_63,2075mmNIC0_QM0_ARB_SLV_ID,2076mmNIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST,2077mmNIC0_QM0_ARC_CQ_CFG0,2078mmNIC0_QM0_CQ_IFIFO_CI_0,2079mmNIC0_QM0_CQ_IFIFO_CI_1,2080mmNIC0_QM0_CQ_IFIFO_CI_2,2081mmNIC0_QM0_CQ_IFIFO_CI_3,2082mmNIC0_QM0_CQ_IFIFO_CI_4,2083mmNIC0_QM0_ARC_CQ_IFIFO_CI,2084mmNIC0_QM0_CQ_CTL_CI_0,2085mmNIC0_QM0_CQ_CTL_CI_1,2086mmNIC0_QM0_CQ_CTL_CI_2,2087mmNIC0_QM0_CQ_CTL_CI_3,2088mmNIC0_QM0_CQ_CTL_CI_4,2089mmNIC0_QM0_ARC_CQ_CTL_CI,2090mmNIC0_QM0_ARC_CQ_TSIZE,2091mmNIC0_QM0_ARC_CQ_CTL,2092mmNIC0_QM0_CP_SWITCH_WD_SET,2093mmNIC0_QM0_CP_EXT_SWITCH,2094mmNIC0_QM0_CP_PRED_0,2095mmNIC0_QM0_CP_PRED_1,2096mmNIC0_QM0_CP_PRED_2,2097mmNIC0_QM0_CP_PRED_3,2098mmNIC0_QM0_CP_PRED_4,2099mmNIC0_QM0_CP_PRED_UPEN_0,2100mmNIC0_QM0_CP_PRED_UPEN_1,2101mmNIC0_QM0_CP_PRED_UPEN_2,2102mmNIC0_QM0_CP_PRED_UPEN_3,2103mmNIC0_QM0_CP_PRED_UPEN_4,2104mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0,2105mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_1,2106mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_2,2107mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_3,2108mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_4,2109mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0,2110mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_1,2111mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_2,2112mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_3,2113mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_4,2114mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0,2115mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_1,2116mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_2,2117mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_3,2118mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_4,2119mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0,2120mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_1,2121mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_2,2122mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_3,2123mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_4,2124mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0,2125mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_1,2126mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2,2127mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_3,2128mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_4,2129mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0,2130mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_1,2131mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_2,2132mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_3,2133mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_4,2134mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0,2135mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_1,2136mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_2,2137mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_3,2138mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_4,2139mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0,2140mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_1,2141mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_2,2142mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_3,2143mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_4,2144mmNIC0_QM0_ARC_CQ_IFIFO_MSG_BASE_LO,2145mmNIC0_QM0_ARC_CQ_CTL_MSG_BASE_LO,2146mmNIC0_QM0_CQ_IFIFO_MSG_BASE_LO,2147mmNIC0_QM0_CQ_CTL_MSG_BASE_LO2148};21492150static const u32 gaudi2_pb_rot0[] = {2151mmROT0_BASE,2152mmROT0_MSTR_IF_RR_SHRD_HBW_BASE,2153mmROT0_QM_BASE,2154};21552156static const u32 gaudi2_pb_rot0_arc[] = {2157mmROT0_QM_ARC_AUX_BASE2158};21592160static const struct range gaudi2_pb_rot0_arc_unsecured_regs[] = {2161{mmROT0_QM_ARC_AUX_RUN_HALT_REQ, mmROT0_QM_ARC_AUX_RUN_HALT_ACK},2162{mmROT0_QM_ARC_AUX_CLUSTER_NUM, mmROT0_QM_ARC_AUX_WAKE_UP_EVENT},2163{mmROT0_QM_ARC_AUX_ARC_RST_REQ, mmROT0_QM_ARC_AUX_CID_OFFSET_7},2164{mmROT0_QM_ARC_AUX_SCRATCHPAD_0, mmROT0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},2165{mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},2166{mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},2167{mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, mmROT0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},2168{mmROT0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, mmROT0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},2169{mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmROT0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},2170};21712172static const u32 gaudi2_pb_rot0_unsecured_regs[] = {2173mmROT0_QM_CQ_CFG0_0,2174mmROT0_QM_CQ_CFG0_1,2175mmROT0_QM_CQ_CFG0_2,2176mmROT0_QM_CQ_CFG0_3,2177mmROT0_QM_CQ_CFG0_4,2178mmROT0_QM_CP_FENCE0_RDATA_0,2179mmROT0_QM_CP_FENCE0_RDATA_1,2180mmROT0_QM_CP_FENCE0_RDATA_2,2181mmROT0_QM_CP_FENCE0_RDATA_3,2182mmROT0_QM_CP_FENCE0_RDATA_4,2183mmROT0_QM_CP_FENCE1_RDATA_0,2184mmROT0_QM_CP_FENCE1_RDATA_1,2185mmROT0_QM_CP_FENCE1_RDATA_2,2186mmROT0_QM_CP_FENCE1_RDATA_3,2187mmROT0_QM_CP_FENCE1_RDATA_4,2188mmROT0_QM_CP_FENCE2_RDATA_0,2189mmROT0_QM_CP_FENCE2_RDATA_1,2190mmROT0_QM_CP_FENCE2_RDATA_2,2191mmROT0_QM_CP_FENCE2_RDATA_3,2192mmROT0_QM_CP_FENCE2_RDATA_4,2193mmROT0_QM_CP_FENCE3_RDATA_0,2194mmROT0_QM_CP_FENCE3_RDATA_1,2195mmROT0_QM_CP_FENCE3_RDATA_2,2196mmROT0_QM_CP_FENCE3_RDATA_3,2197mmROT0_QM_CP_FENCE3_RDATA_4,2198mmROT0_QM_CP_FENCE0_CNT_0,2199mmROT0_QM_CP_FENCE0_CNT_1,2200mmROT0_QM_CP_FENCE0_CNT_2,2201mmROT0_QM_CP_FENCE0_CNT_3,2202mmROT0_QM_CP_FENCE0_CNT_4,2203mmROT0_QM_CP_FENCE1_CNT_0,2204mmROT0_QM_CP_FENCE1_CNT_1,2205mmROT0_QM_CP_FENCE1_CNT_2,2206mmROT0_QM_CP_FENCE1_CNT_3,2207mmROT0_QM_CP_FENCE1_CNT_4,2208mmROT0_QM_CP_FENCE2_CNT_0,2209mmROT0_QM_CP_FENCE2_CNT_1,2210mmROT0_QM_CP_FENCE2_CNT_2,2211mmROT0_QM_CP_FENCE2_CNT_3,2212mmROT0_QM_CP_FENCE2_CNT_4,2213mmROT0_QM_CP_FENCE3_CNT_0,2214mmROT0_QM_CP_FENCE3_CNT_1,2215mmROT0_QM_CP_FENCE3_CNT_2,2216mmROT0_QM_CP_FENCE3_CNT_3,2217mmROT0_QM_CP_FENCE3_CNT_4,2218mmROT0_QM_CQ_PTR_LO_0,2219mmROT0_QM_CQ_PTR_HI_0,2220mmROT0_QM_CQ_TSIZE_0,2221mmROT0_QM_CQ_CTL_0,2222mmROT0_QM_CQ_PTR_LO_1,2223mmROT0_QM_CQ_PTR_HI_1,2224mmROT0_QM_CQ_TSIZE_1,2225mmROT0_QM_CQ_CTL_1,2226mmROT0_QM_CQ_PTR_LO_2,2227mmROT0_QM_CQ_PTR_HI_2,2228mmROT0_QM_CQ_TSIZE_2,2229mmROT0_QM_CQ_CTL_2,2230mmROT0_QM_CQ_PTR_LO_3,2231mmROT0_QM_CQ_PTR_HI_3,2232mmROT0_QM_CQ_TSIZE_3,2233mmROT0_QM_CQ_CTL_3,2234mmROT0_QM_CQ_PTR_LO_4,2235mmROT0_QM_CQ_PTR_HI_4,2236mmROT0_QM_CQ_TSIZE_4,2237mmROT0_QM_CQ_CTL_4,2238mmROT0_QM_QMAN_WR64_BASE_ADDR0_BASE,2239mmROT0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,2240mmROT0_QM_QMAN_WR64_BASE_ADDR1_BASE,2241mmROT0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,2242mmROT0_QM_QMAN_WR64_BASE_ADDR2_BASE,2243mmROT0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,2244mmROT0_QM_QMAN_WR64_BASE_ADDR3_BASE,2245mmROT0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,2246mmROT0_QM_QMAN_WR64_BASE_ADDR4_BASE,2247mmROT0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,2248mmROT0_QM_QMAN_WR64_BASE_ADDR5_BASE,2249mmROT0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,2250mmROT0_QM_QMAN_WR64_BASE_ADDR6_BASE,2251mmROT0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,2252mmROT0_QM_QMAN_WR64_BASE_ADDR7_BASE,2253mmROT0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,2254mmROT0_QM_QMAN_WR64_BASE_ADDR8_BASE,2255mmROT0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,2256mmROT0_QM_QMAN_WR64_BASE_ADDR9_BASE,2257mmROT0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,2258mmROT0_QM_QMAN_WR64_BASE_ADDR10_BASE,2259mmROT0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,2260mmROT0_QM_QMAN_WR64_BASE_ADDR11_BASE,2261mmROT0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,2262mmROT0_QM_QMAN_WR64_BASE_ADDR12_BASE,2263mmROT0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,2264mmROT0_QM_QMAN_WR64_BASE_ADDR13_BASE,2265mmROT0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,2266mmROT0_QM_QMAN_WR64_BASE_ADDR14_BASE,2267mmROT0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,2268mmROT0_QM_QMAN_WR64_BASE_ADDR15_BASE,2269mmROT0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,2270mmROT0_QM_ARC_CQ_PTR_LO,2271mmROT0_QM_ARC_CQ_PTR_LO_STS,2272mmROT0_QM_ARC_CQ_PTR_HI,2273mmROT0_QM_ARC_CQ_PTR_HI_STS,2274mmROT0_QM_ARB_CFG_0,2275mmROT0_QM_ARB_MST_QUIET_PER,2276mmROT0_QM_ARB_CHOICE_Q_PUSH,2277mmROT0_QM_ARB_WRR_WEIGHT_0,2278mmROT0_QM_ARB_WRR_WEIGHT_1,2279mmROT0_QM_ARB_WRR_WEIGHT_2,2280mmROT0_QM_ARB_WRR_WEIGHT_3,2281mmROT0_QM_ARB_BASE_LO,2282mmROT0_QM_ARB_BASE_HI,2283mmROT0_QM_ARB_MST_SLAVE_EN,2284mmROT0_QM_ARB_MST_SLAVE_EN_1,2285mmROT0_QM_ARB_MST_CRED_INC,2286mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_0,2287mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_1,2288mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_2,2289mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_3,2290mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_4,2291mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_5,2292mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_6,2293mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_7,2294mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_8,2295mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_9,2296mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_10,2297mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_11,2298mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_12,2299mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_13,2300mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_14,2301mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_15,2302mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_16,2303mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_17,2304mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_18,2305mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_19,2306mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_20,2307mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_21,2308mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_22,2309mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_23,2310mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_24,2311mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_25,2312mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_26,2313mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_27,2314mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_28,2315mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_29,2316mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_30,2317mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_31,2318mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_32,2319mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_33,2320mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_34,2321mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_35,2322mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_36,2323mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_37,2324mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_38,2325mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_39,2326mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_40,2327mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_41,2328mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_42,2329mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_43,2330mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_44,2331mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_45,2332mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_46,2333mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_47,2334mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_48,2335mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_49,2336mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_50,2337mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_51,2338mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_52,2339mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_53,2340mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_54,2341mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_55,2342mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_56,2343mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_57,2344mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_58,2345mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_59,2346mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_60,2347mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_61,2348mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_62,2349mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_63,2350mmROT0_QM_ARB_SLV_ID,2351mmROT0_QM_ARB_SLV_MASTER_INC_CRED_OFST,2352mmROT0_QM_ARC_CQ_CFG0,2353mmROT0_QM_CQ_IFIFO_CI_0,2354mmROT0_QM_CQ_IFIFO_CI_1,2355mmROT0_QM_CQ_IFIFO_CI_2,2356mmROT0_QM_CQ_IFIFO_CI_3,2357mmROT0_QM_CQ_IFIFO_CI_4,2358mmROT0_QM_ARC_CQ_IFIFO_CI,2359mmROT0_QM_CQ_CTL_CI_0,2360mmROT0_QM_CQ_CTL_CI_1,2361mmROT0_QM_CQ_CTL_CI_2,2362mmROT0_QM_CQ_CTL_CI_3,2363mmROT0_QM_CQ_CTL_CI_4,2364mmROT0_QM_ARC_CQ_CTL_CI,2365mmROT0_QM_ARC_CQ_TSIZE,2366mmROT0_QM_ARC_CQ_CTL,2367mmROT0_QM_CP_SWITCH_WD_SET,2368mmROT0_QM_CP_EXT_SWITCH,2369mmROT0_QM_CP_PRED_0,2370mmROT0_QM_CP_PRED_1,2371mmROT0_QM_CP_PRED_2,2372mmROT0_QM_CP_PRED_3,2373mmROT0_QM_CP_PRED_4,2374mmROT0_QM_CP_PRED_UPEN_0,2375mmROT0_QM_CP_PRED_UPEN_1,2376mmROT0_QM_CP_PRED_UPEN_2,2377mmROT0_QM_CP_PRED_UPEN_3,2378mmROT0_QM_CP_PRED_UPEN_4,2379mmROT0_QM_CP_MSG_BASE0_ADDR_LO_0,2380mmROT0_QM_CP_MSG_BASE0_ADDR_LO_1,2381mmROT0_QM_CP_MSG_BASE0_ADDR_LO_2,2382mmROT0_QM_CP_MSG_BASE0_ADDR_LO_3,2383mmROT0_QM_CP_MSG_BASE0_ADDR_LO_4,2384mmROT0_QM_CP_MSG_BASE0_ADDR_HI_0,2385mmROT0_QM_CP_MSG_BASE0_ADDR_HI_1,2386mmROT0_QM_CP_MSG_BASE0_ADDR_HI_2,2387mmROT0_QM_CP_MSG_BASE0_ADDR_HI_3,2388mmROT0_QM_CP_MSG_BASE0_ADDR_HI_4,2389mmROT0_QM_CP_MSG_BASE1_ADDR_LO_0,2390mmROT0_QM_CP_MSG_BASE1_ADDR_LO_1,2391mmROT0_QM_CP_MSG_BASE1_ADDR_LO_2,2392mmROT0_QM_CP_MSG_BASE1_ADDR_LO_3,2393mmROT0_QM_CP_MSG_BASE1_ADDR_LO_4,2394mmROT0_QM_CP_MSG_BASE1_ADDR_HI_0,2395mmROT0_QM_CP_MSG_BASE1_ADDR_HI_1,2396mmROT0_QM_CP_MSG_BASE1_ADDR_HI_2,2397mmROT0_QM_CP_MSG_BASE1_ADDR_HI_3,2398mmROT0_QM_CP_MSG_BASE1_ADDR_HI_4,2399mmROT0_QM_CP_MSG_BASE2_ADDR_LO_0,2400mmROT0_QM_CP_MSG_BASE2_ADDR_LO_1,2401mmROT0_QM_CP_MSG_BASE2_ADDR_LO_2,2402mmROT0_QM_CP_MSG_BASE2_ADDR_LO_3,2403mmROT0_QM_CP_MSG_BASE2_ADDR_LO_4,2404mmROT0_QM_CP_MSG_BASE2_ADDR_HI_0,2405mmROT0_QM_CP_MSG_BASE2_ADDR_HI_1,2406mmROT0_QM_CP_MSG_BASE2_ADDR_HI_2,2407mmROT0_QM_CP_MSG_BASE2_ADDR_HI_3,2408mmROT0_QM_CP_MSG_BASE2_ADDR_HI_4,2409mmROT0_QM_CP_MSG_BASE3_ADDR_LO_0,2410mmROT0_QM_CP_MSG_BASE3_ADDR_LO_1,2411mmROT0_QM_CP_MSG_BASE3_ADDR_LO_2,2412mmROT0_QM_CP_MSG_BASE3_ADDR_LO_3,2413mmROT0_QM_CP_MSG_BASE3_ADDR_LO_4,2414mmROT0_QM_CP_MSG_BASE3_ADDR_HI_0,2415mmROT0_QM_CP_MSG_BASE3_ADDR_HI_1,2416mmROT0_QM_CP_MSG_BASE3_ADDR_HI_2,2417mmROT0_QM_CP_MSG_BASE3_ADDR_HI_3,2418mmROT0_QM_CP_MSG_BASE3_ADDR_HI_4,2419mmROT0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,2420mmROT0_QM_ARC_CQ_CTL_MSG_BASE_LO,2421mmROT0_QM_CQ_IFIFO_MSG_BASE_LO,2422mmROT0_QM_CQ_CTL_MSG_BASE_LO,2423mmROT0_DESC_CONTEXT_ID,2424mmROT0_DESC_IN_IMG_START_ADDR_L,2425mmROT0_DESC_IN_IMG_START_ADDR_H,2426mmROT0_DESC_OUT_IMG_START_ADDR_L,2427mmROT0_DESC_OUT_IMG_START_ADDR_H,2428mmROT0_DESC_CFG,2429mmROT0_DESC_IM_READ_SLOPE,2430mmROT0_DESC_SIN_D,2431mmROT0_DESC_COS_D,2432mmROT0_DESC_IN_IMG,2433mmROT0_DESC_IN_STRIDE,2434mmROT0_DESC_IN_STRIPE,2435mmROT0_DESC_IN_CENTER,2436mmROT0_DESC_OUT_IMG,2437mmROT0_DESC_OUT_STRIDE,2438mmROT0_DESC_OUT_STRIPE,2439mmROT0_DESC_OUT_CENTER,2440mmROT0_DESC_BACKGROUND,2441mmROT0_DESC_CPL_MSG_EN,2442mmROT0_DESC_IDLE_STATE,2443mmROT0_DESC_CPL_MSG_ADDR,2444mmROT0_DESC_CPL_MSG_DATA,2445mmROT0_DESC_X_I_START_OFFSET,2446mmROT0_DESC_X_I_START_OFFSET_FLIP,2447mmROT0_DESC_X_I_FIRST,2448mmROT0_DESC_Y_I_FIRST,2449mmROT0_DESC_Y_I,2450mmROT0_DESC_OUT_STRIPE_SIZE,2451mmROT0_DESC_RSB_CFG_0,2452mmROT0_DESC_RSB_PAD_VAL,2453mmROT0_DESC_OWM_CFG,2454mmROT0_DESC_CTRL_CFG,2455mmROT0_DESC_PIXEL_PAD,2456mmROT0_DESC_PREC_SHIFT,2457mmROT0_DESC_MAX_VAL,2458mmROT0_DESC_A0_M11,2459mmROT0_DESC_A1_M12,2460mmROT0_DESC_A2,2461mmROT0_DESC_B0_M21,2462mmROT0_DESC_B1_M22,2463mmROT0_DESC_B2,2464mmROT0_DESC_C0,2465mmROT0_DESC_C1,2466mmROT0_DESC_C2,2467mmROT0_DESC_D0,2468mmROT0_DESC_D1,2469mmROT0_DESC_D2,2470mmROT0_DESC_INV_PROC_SIZE_M_1,2471mmROT0_DESC_MESH_IMG_START_ADDR_L,2472mmROT0_DESC_MESH_IMG_START_ADDR_H,2473mmROT0_DESC_MESH_IMG,2474mmROT0_DESC_MESH_STRIDE,2475mmROT0_DESC_MESH_STRIPE,2476mmROT0_DESC_MESH_CTRL,2477mmROT0_DESC_MESH_GH,2478mmROT0_DESC_MESH_GV,2479mmROT0_DESC_MRSB_CFG_0,2480mmROT0_DESC_MRSB_PAD_VAL,2481mmROT0_DESC_BUF_CFG,2482mmROT0_DESC_CID_OFFSET,2483mmROT0_DESC_PUSH_DESC2484};24852486static const u32 gaudi2_pb_psoc_global_conf[] = {2487mmPSOC_GLOBAL_CONF_BASE2488};24892490static const u32 gaudi2_pb_psoc[] = {2491mmPSOC_EFUSE_BASE,2492mmPSOC_BTL_BASE,2493mmPSOC_CS_TRACE_BASE,2494mmPSOC_DFT_EFUSE_BASE,2495mmPSOC_PID_BASE,2496mmPSOC_ARC0_CFG_BASE,2497mmPSOC_ARC0_MSTR_IF_RR_SHRD_HBW_BASE,2498mmPSOC_ARC0_AUX_BASE,2499mmPSOC_ARC1_CFG_BASE,2500mmPSOC_ARC1_MSTR_IF_RR_SHRD_HBW_BASE,2501mmPSOC_ARC1_AUX_BASE,2502mmJT_MSTR_IF_RR_SHRD_HBW_BASE,2503mmSMI_MSTR_IF_RR_SHRD_HBW_BASE,2504mmI2C_S_MSTR_IF_RR_SHRD_HBW_BASE,2505mmPSOC_SVID0_BASE,2506mmPSOC_SVID1_BASE,2507mmPSOC_SVID2_BASE,2508mmPSOC_AVS0_BASE,2509mmPSOC_AVS1_BASE,2510mmPSOC_AVS2_BASE,2511mmPSOC_PWM0_BASE,2512mmPSOC_PWM1_BASE,2513mmPSOC_MSTR_IF_RR_SHRD_HBW_BASE,2514};25152516static const u32 gaudi2_pb_pmmu[] = {2517mmPMMU_HBW_MMU_BASE,2518mmPMMU_HBW_STLB_BASE,2519mmPMMU_HBW_MSTR_IF_RR_SHRD_HBW_BASE,2520mmPMMU_PIF_BASE,2521};25222523static const u32 gaudi2_pb_psoc_pll[] = {2524mmPSOC_MME_PLL_CTRL_BASE,2525mmPSOC_CPU_PLL_CTRL_BASE,2526mmPSOC_VID_PLL_CTRL_BASE2527};25282529static const u32 gaudi2_pb_pmmu_pll[] = {2530mmPMMU_MME_PLL_CTRL_BASE,2531mmPMMU_VID_PLL_CTRL_BASE2532};25332534static const u32 gaudi2_pb_xbar_pll[] = {2535mmDCORE0_XBAR_DMA_PLL_CTRL_BASE,2536mmDCORE0_XBAR_MMU_PLL_CTRL_BASE,2537mmDCORE0_XBAR_IF_PLL_CTRL_BASE,2538mmDCORE0_XBAR_MESH_PLL_CTRL_BASE,2539mmDCORE1_XBAR_DMA_PLL_CTRL_BASE,2540mmDCORE1_XBAR_MMU_PLL_CTRL_BASE,2541mmDCORE1_XBAR_IF_PLL_CTRL_BASE,2542mmDCORE1_XBAR_MESH_PLL_CTRL_BASE,2543mmDCORE1_XBAR_HBM_PLL_CTRL_BASE,2544mmDCORE2_XBAR_DMA_PLL_CTRL_BASE,2545mmDCORE2_XBAR_MMU_PLL_CTRL_BASE,2546mmDCORE2_XBAR_IF_PLL_CTRL_BASE,2547mmDCORE2_XBAR_BANK_PLL_CTRL_BASE,2548mmDCORE2_XBAR_HBM_PLL_CTRL_BASE,2549mmDCORE3_XBAR_DMA_PLL_CTRL_BASE,2550mmDCORE3_XBAR_MMU_PLL_CTRL_BASE,2551mmDCORE3_XBAR_IF_PLL_CTRL_BASE,2552mmDCORE3_XBAR_BANK_PLL_CTRL_BASE2553};25542555static const u32 gaudi2_pb_xft_pll[] = {2556mmDCORE0_HBM_PLL_CTRL_BASE,2557mmDCORE0_TPC_PLL_CTRL_BASE,2558mmDCORE0_PCI_PLL_CTRL_BASE,2559mmDCORE1_HBM_PLL_CTRL_BASE,2560mmDCORE1_TPC_PLL_CTRL_BASE,2561mmDCORE1_NIC_PLL_CTRL_BASE,2562mmDCORE2_HBM_PLL_CTRL_BASE,2563mmDCORE2_TPC_PLL_CTRL_BASE,2564mmDCORE3_HBM_PLL_CTRL_BASE,2565mmDCORE3_TPC_PLL_CTRL_BASE,2566mmDCORE3_NIC_PLL_CTRL_BASE,2567};25682569static const u32 gaudi2_pb_pcie[] = {2570mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_BASE,2571mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_BASE,2572mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE,2573mmPCIE_WRAP_BASE,2574};25752576static const u32 gaudi2_pb_pcie_unsecured_regs[] = {2577mmPCIE_WRAP_SPECIAL_GLBL_SPARE_0,2578};25792580static const u32 gaudi2_pb_thermal_sensor0[] = {2581mmDCORE0_XFT_BASE,2582mmDCORE0_TSTDVS_BASE,2583};25842585static const u32 gaudi2_pb_hbm[] = {2586mmHBM0_MC0_BASE,2587mmHBM0_MC1_BASE,2588};25892590static const u32 gaudi2_pb_mme_qm_arc_acp_eng[] = {2591mmDCORE0_MME_QM_ARC_ACP_ENG_BASE,2592};25932594static const struct range gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs[] = {2595{mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_0, mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_REG},2596};25972598struct gaudi2_tpc_pb_data {2599struct hl_block_glbl_sec *glbl_sec;2600u32 block_array_size;2601};26022603static void gaudi2_config_tpcs_glbl_sec(struct hl_device *hdev, int dcore, int inst, u32 offset,2604struct iterate_module_ctx *ctx)2605{2606struct gaudi2_tpc_pb_data *pb_data = ctx->data;26072608hl_config_glbl_sec(hdev, gaudi2_pb_dcr0_tpc0, pb_data->glbl_sec,2609offset, pb_data->block_array_size);2610}26112612static int gaudi2_init_pb_tpc(struct hl_device *hdev)2613{2614u32 stride, kernel_tensor_stride, qm_tensor_stride, block_array_size;2615struct gaudi2_tpc_pb_data tpc_pb_data;2616struct hl_block_glbl_sec *glbl_sec;2617struct iterate_module_ctx tpc_iter;2618int i;26192620block_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0);26212622glbl_sec = kcalloc(block_array_size, sizeof(struct hl_block_glbl_sec), GFP_KERNEL);2623if (!glbl_sec)2624return -ENOMEM;26252626kernel_tensor_stride = mmDCORE0_TPC0_CFG_KERNEL_TENSOR_1_BASE -2627mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE;2628qm_tensor_stride = mmDCORE0_TPC0_CFG_QM_TENSOR_1_BASE - mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE;26292630hl_secure_block(hdev, glbl_sec, block_array_size);2631hl_unsecure_registers(hdev, gaudi2_pb_dcr0_tpc0_unsecured_regs,2632ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_unsecured_regs),26330, gaudi2_pb_dcr0_tpc0, glbl_sec,2634block_array_size);26352636/* Unsecure all TPC kernel tensors */2637for (i = 0 ; i < TPC_NUM_OF_KERNEL_TENSORS ; i++)2638hl_unsecure_registers(hdev,2639gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs,2640ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs),2641i * kernel_tensor_stride, gaudi2_pb_dcr0_tpc0,2642glbl_sec, block_array_size);26432644/* Unsecure all TPC QM tensors */2645for (i = 0 ; i < TPC_NUM_OF_QM_TENSORS ; i++)2646hl_unsecure_registers(hdev,2647gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs,2648ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs),2649i * qm_tensor_stride,2650gaudi2_pb_dcr0_tpc0, glbl_sec, block_array_size);26512652/* unsecure all 32 TPC QM SRF regs */2653stride = mmDCORE0_TPC0_CFG_QM_SRF_1 - mmDCORE0_TPC0_CFG_QM_SRF_0;2654for (i = 0 ; i < 32 ; i++)2655hl_unsecure_register(hdev, mmDCORE0_TPC0_CFG_QM_SRF_0,2656i * stride, gaudi2_pb_dcr0_tpc0, glbl_sec,2657block_array_size);26582659/* unsecure the 4 TPC LOCK VALUE regs */2660stride = mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_1 - mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0;2661for (i = 0 ; i < 4 ; i++)2662hl_unsecure_register(hdev, mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0,2663i * stride, gaudi2_pb_dcr0_tpc0, glbl_sec,2664block_array_size);26652666/* prepare data for TPC iterator */2667tpc_pb_data.glbl_sec = glbl_sec;2668tpc_pb_data.block_array_size = block_array_size;2669tpc_iter.fn = &gaudi2_config_tpcs_glbl_sec;2670tpc_iter.data = &tpc_pb_data;2671gaudi2_iterate_tpcs(hdev, &tpc_iter);26722673kfree(glbl_sec);26742675return 0;2676}26772678struct gaudi2_tpc_arc_pb_data {2679u32 unsecured_regs_arr_size;2680u32 arc_regs_arr_size;2681};26822683static void gaudi2_config_tpcs_pb_ranges(struct hl_device *hdev, int dcore, int inst, u32 offset,2684struct iterate_module_ctx *ctx)2685{2686struct gaudi2_tpc_arc_pb_data *pb_data = ctx->data;26872688ctx->rc = hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 1,2689offset, gaudi2_pb_dcr0_tpc0_arc,2690pb_data->arc_regs_arr_size,2691gaudi2_pb_dcr0_tpc0_arc_unsecured_regs,2692pb_data->unsecured_regs_arr_size);2693}26942695static int gaudi2_init_pb_tpc_arc(struct hl_device *hdev)2696{2697struct gaudi2_tpc_arc_pb_data tpc_arc_pb_data;2698struct iterate_module_ctx tpc_iter;26992700tpc_arc_pb_data.arc_regs_arr_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc);2701tpc_arc_pb_data.unsecured_regs_arr_size =2702ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc_unsecured_regs);27032704tpc_iter.fn = &gaudi2_config_tpcs_pb_ranges;2705tpc_iter.data = &tpc_arc_pb_data;2706gaudi2_iterate_tpcs(hdev, &tpc_iter);27072708return tpc_iter.rc;2709}27102711static int gaudi2_init_pb_sm_objs(struct hl_device *hdev)2712{2713int i, j, glbl_sec_array_len = gaudi2_pb_dcr0_sm_objs.glbl_sec_length;2714u32 sec_entry, *sec_array, array_base, first_sob, first_mon;27152716array_base = gaudi2_pb_dcr0_sm_objs.mm_block_base_addr +2717gaudi2_pb_dcr0_sm_objs.glbl_sec_offset;27182719sec_array = kcalloc(glbl_sec_array_len, sizeof(u32), GFP_KERNEL);2720if (!sec_array)2721return -ENOMEM;27222723first_sob = GAUDI2_RESERVED_SOB_NUMBER;2724first_mon = GAUDI2_RESERVED_MON_NUMBER;27252726/* 8192 SOB_OBJs skipping first GAUDI2_MAX_PENDING_CS of them */2727for (j = i = first_sob ; i < DCORE_NUM_OF_SOB ; i++, j++)2728UNSET_GLBL_SEC_BIT(sec_array, j);27292730/* 2048 MON_PAY ADDR_L skipping first GAUDI2_MAX_PENDING_CS of them */2731for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)2732UNSET_GLBL_SEC_BIT(sec_array, j);27332734/* 2048 MON_PAY ADDR_H skipping first GAUDI2_MAX_PENDING_CS of them */2735for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)2736UNSET_GLBL_SEC_BIT(sec_array, j);27372738/* 2048 MON_PAY DATA skipping first GAUDI2_MAX_PENDING_CS of them */2739for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)2740UNSET_GLBL_SEC_BIT(sec_array, j);27412742/* 2048 MON_ARM skipping first GAUDI2_MAX_PENDING_CS of them */2743for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)2744UNSET_GLBL_SEC_BIT(sec_array, j);27452746/* 2048 MON_CONFIG skipping first GAUDI2_MAX_PENDING_CS of them */2747for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)2748UNSET_GLBL_SEC_BIT(sec_array, j);27492750/* 2048 MON_STATUS skipping first GAUDI2_MAX_PENDING_CS of them */2751for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)2752UNSET_GLBL_SEC_BIT(sec_array, j);27532754/* Unsecure selected Dcore0 registers */2755for (i = 0 ; i < glbl_sec_array_len ; i++) {2756sec_entry = array_base + i * sizeof(u32);2757WREG32(sec_entry, sec_array[i]);2758}27592760/* Unsecure Dcore1 - Dcore3 registers */2761memset(sec_array, -1, glbl_sec_array_len * sizeof(u32));27622763for (i = 1 ; i < NUM_OF_DCORES ; i++) {2764for (j = 0 ; j < glbl_sec_array_len ; j++) {2765sec_entry = DCORE_OFFSET * i + array_base + j * sizeof(u32);2766WREG32(sec_entry, sec_array[j]);2767}2768}27692770kfree(sec_array);27712772return 0;2773}27742775static void gaudi2_write_lbw_range_register(struct hl_device *hdev, u64 base, void *data)2776{2777u32 reg_min_offset, reg_max_offset, write_min, write_max;2778struct rr_config *rr_cfg = (struct rr_config *) data;27792780switch (rr_cfg->type) {2781case RR_TYPE_SHORT:2782reg_min_offset = RR_LBW_SEC_RANGE_MIN_SHORT_0_OFFSET;2783reg_max_offset = RR_LBW_SEC_RANGE_MAX_SHORT_0_OFFSET;2784break;27852786case RR_TYPE_LONG:2787reg_min_offset = RR_LBW_SEC_RANGE_MIN_0_OFFSET;2788reg_max_offset = RR_LBW_SEC_RANGE_MAX_0_OFFSET;2789break;27902791case RR_TYPE_SHORT_PRIV:2792reg_min_offset = RR_LBW_PRIV_RANGE_MIN_SHORT_0_OFFSET;2793reg_max_offset = RR_LBW_PRIV_RANGE_MAX_SHORT_0_OFFSET;2794break;27952796case RR_TYPE_LONG_PRIV:2797reg_min_offset = RR_LBW_PRIV_RANGE_MIN_0_OFFSET;2798reg_max_offset = RR_LBW_PRIV_RANGE_MAX_0_OFFSET;2799break;28002801default:2802dev_err(hdev->dev, "Invalid LBW RR type %u\n", rr_cfg->type);2803return;2804}28052806reg_min_offset += rr_cfg->index * sizeof(u32);2807reg_max_offset += rr_cfg->index * sizeof(u32);28082809if (rr_cfg->type == RR_TYPE_SHORT || rr_cfg->type == RR_TYPE_SHORT_PRIV) {2810write_min = FIELD_GET(RR_LBW_SHORT_MASK, lower_32_bits(rr_cfg->min));2811write_max = FIELD_GET(RR_LBW_SHORT_MASK, lower_32_bits(rr_cfg->max));28122813} else {2814write_min = FIELD_GET(RR_LBW_LONG_MASK, lower_32_bits(rr_cfg->min));2815write_max = FIELD_GET(RR_LBW_LONG_MASK, lower_32_bits(rr_cfg->max));2816}28172818/* Configure LBW RR:2819* Both RR types start blocking from base address 0x1000007FF80000002820* SHORT RRs address bits [26:12]2821* LONG RRs address bits [26:0]2822*/2823WREG32(base + reg_min_offset, write_min);2824WREG32(base + reg_max_offset, write_max);2825}28262827void gaudi2_write_rr_to_all_lbw_rtrs(struct hl_device *hdev, u8 rr_type, u32 rr_index, u64 min_val,2828u64 max_val)2829{2830struct dup_block_ctx block_ctx;2831struct rr_config rr_cfg;28322833if ((rr_type == RR_TYPE_SHORT || rr_type == RR_TYPE_SHORT_PRIV) &&2834rr_index >= NUM_SHORT_LBW_RR) {28352836dev_err(hdev->dev, "invalid short LBW %s range register index: %u",2837rr_type == RR_TYPE_SHORT ? "secure" : "privileged", rr_index);2838return;2839}28402841if ((rr_type == RR_TYPE_LONG || rr_type == RR_TYPE_LONG_PRIV) &&2842rr_index >= NUM_LONG_LBW_RR) {28432844dev_err(hdev->dev, "invalid long LBW %s range register index: %u",2845rr_type == RR_TYPE_LONG ? "secure" : "privileged", rr_index);2846return;2847}28482849rr_cfg.type = rr_type;2850rr_cfg.index = rr_index;2851rr_cfg.min = min_val;2852rr_cfg.max = max_val;28532854block_ctx.instance_cfg_fn = &gaudi2_write_lbw_range_register;2855block_ctx.data = &rr_cfg;28562857/* SFT */2858block_ctx.base = mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE;2859block_ctx.blocks = NUM_OF_SFT;2860block_ctx.block_off = SFT_OFFSET;2861block_ctx.instances = SFT_NUM_OF_LBW_RTR;2862block_ctx.instance_off = SFT_LBW_RTR_OFFSET;2863gaudi2_init_blocks(hdev, &block_ctx);28642865/* SIF */2866block_ctx.base = mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE;2867block_ctx.blocks = NUM_OF_DCORES;2868block_ctx.block_off = DCORE_OFFSET;2869block_ctx.instances = NUM_OF_RTR_PER_DCORE;2870block_ctx.instance_off = DCORE_RTR_OFFSET;2871gaudi2_init_blocks(hdev, &block_ctx);28722873block_ctx.blocks = 1;2874block_ctx.block_off = 0;2875block_ctx.instances = 1;2876block_ctx.instance_off = 0;28772878/* PCIE ELBI */2879block_ctx.base = mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_BASE;2880gaudi2_init_blocks(hdev, &block_ctx);28812882/* PCIE MSTR */2883block_ctx.base = mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_BASE;2884gaudi2_init_blocks(hdev, &block_ctx);28852886/* PCIE LBW */2887block_ctx.base = mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_BASE;2888gaudi2_init_blocks(hdev, &block_ctx);2889}28902891static void gaudi2_init_lbw_range_registers_secure(struct hl_device *hdev)2892{2893int i;28942895/* Up to 14 14bit-address regs.2896*2897* - range 0: NIC0_CFG2898* - range 1: NIC1_CFG2899* - range 2: NIC2_CFG2900* - range 3: NIC3_CFG2901* - range 4: NIC4_CFG2902* - range 5: NIC5_CFG2903* - range 6: NIC6_CFG2904* - range 7: NIC7_CFG2905* - range 8: NIC8_CFG2906* - range 9: NIC9_CFG2907* - range 10: NIC10_CFG2908* - range 11: NIC11_CFG + *_DBG (not including TPC_DBG)2909*2910* If F/W security is not enabled:2911* - ranges 12,13: PSOC_CFG (excluding PSOC_TIMESTAMP, PSOC_EFUSE and PSOC_GLOBAL_CONF)2912*/2913u64 lbw_range_min_short[] = {2914mmNIC0_TX_AXUSER_BASE,2915mmNIC1_TX_AXUSER_BASE,2916mmNIC2_TX_AXUSER_BASE,2917mmNIC3_TX_AXUSER_BASE,2918mmNIC4_TX_AXUSER_BASE,2919mmNIC5_TX_AXUSER_BASE,2920mmNIC6_TX_AXUSER_BASE,2921mmNIC7_TX_AXUSER_BASE,2922mmNIC8_TX_AXUSER_BASE,2923mmNIC9_TX_AXUSER_BASE,2924mmNIC10_TX_AXUSER_BASE,2925mmNIC11_TX_AXUSER_BASE,2926mmPSOC_I2C_M0_BASE,2927mmPSOC_GPIO0_BASE2928};2929u64 lbw_range_max_short[] = {2930mmNIC0_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,2931mmNIC1_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,2932mmNIC2_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,2933mmNIC3_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,2934mmNIC4_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,2935mmNIC5_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,2936mmNIC6_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,2937mmNIC7_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,2938mmNIC8_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,2939mmNIC9_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,2940mmNIC10_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,2941mmNIC11_DBG_FUNNEL_NCH_BASE + HL_BLOCK_SIZE,2942mmPSOC_WDOG_BASE + HL_BLOCK_SIZE,2943mmSVID2_AC_BASE + HL_BLOCK_SIZE2944};29452946/* Up to 4 26bit-address regs.2947*2948* - range 0: TPC_DBG2949* - range 1: PCIE_DBI.MSIX_DOORBELL_OFF2950* - range 2/3: used in soft reset to block access to several blocks and are cleared here2951*/2952u64 lbw_range_min_long[] = {2953mmDCORE0_TPC0_ROM_TABLE_BASE,2954mmPCIE_DBI_MSIX_DOORBELL_OFF,29550x0,29560x02957};2958u64 lbw_range_max_long[] = {2959mmDCORE3_TPC5_EML_CS_BASE + HL_BLOCK_SIZE,2960mmPCIE_DBI_MSIX_DOORBELL_OFF + 0x4,29610x0,29620x02963};29642965/* write short range registers to all lbw rtrs */2966for (i = 0 ; i < ARRAY_SIZE(lbw_range_min_short) ; i++) {2967if ((lbw_range_min_short[i] == mmPSOC_I2C_M0_BASE ||2968lbw_range_min_short[i] == mmPSOC_EFUSE_BASE) &&2969hdev->asic_prop.fw_security_enabled)2970continue;29712972gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_SHORT, i,2973lbw_range_min_short[i], lbw_range_max_short[i]);2974}29752976/* write long range registers to all lbw rtrs */2977for (i = 0 ; i < ARRAY_SIZE(lbw_range_min_long) ; i++) {2978gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_LONG, i,2979lbw_range_min_long[i], lbw_range_max_long[i]);2980}2981}29822983static void gaudi2_init_lbw_range_registers(struct hl_device *hdev)2984{2985gaudi2_init_lbw_range_registers_secure(hdev);2986}29872988static void gaudi2_write_hbw_range_register(struct hl_device *hdev, u64 base, void *data)2989{2990u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset;2991struct rr_config *rr_cfg = (struct rr_config *) data;2992u64 val_min, val_max;29932994switch (rr_cfg->type) {2995case RR_TYPE_SHORT:2996min_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0_OFFSET;2997min_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0_OFFSET;2998max_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0_OFFSET;2999max_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0_OFFSET;3000break;30013002case RR_TYPE_LONG:3003min_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_LO_0_OFFSET;3004min_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_HI_0_OFFSET;3005max_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_LO_0_OFFSET;3006max_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_HI_0_OFFSET;3007break;30083009case RR_TYPE_SHORT_PRIV:3010min_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0_OFFSET;3011min_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0_OFFSET;3012max_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0_OFFSET;3013max_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0_OFFSET;3014break;30153016case RR_TYPE_LONG_PRIV:3017min_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0_OFFSET;3018min_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0_OFFSET;3019max_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0_OFFSET;3020max_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0_OFFSET;3021break;30223023default:3024dev_err(hdev->dev, "Invalid HBW RR type %u\n", rr_cfg->type);3025return;3026}30273028min_lo_reg_offset += rr_cfg->index * sizeof(u32);3029min_hi_reg_offset += rr_cfg->index * sizeof(u32);3030max_lo_reg_offset += rr_cfg->index * sizeof(u32);3031max_hi_reg_offset += rr_cfg->index * sizeof(u32);30323033if (rr_cfg->type == RR_TYPE_SHORT || rr_cfg->type == RR_TYPE_SHORT_PRIV) {3034val_min = FIELD_GET(RR_HBW_SHORT_HI_MASK, rr_cfg->min) |3035FIELD_GET(RR_HBW_SHORT_LO_MASK, rr_cfg->min);3036val_max = FIELD_GET(RR_HBW_SHORT_HI_MASK, rr_cfg->max) |3037FIELD_GET(RR_HBW_SHORT_LO_MASK, rr_cfg->max);3038} else {3039val_min = FIELD_GET(RR_HBW_LONG_HI_MASK, rr_cfg->min) |3040FIELD_GET(RR_HBW_LONG_LO_MASK, rr_cfg->min);3041val_max = FIELD_GET(RR_HBW_LONG_HI_MASK, rr_cfg->max) |3042FIELD_GET(RR_HBW_LONG_LO_MASK, rr_cfg->max);3043}30443045/* Configure HBW RR:3046* SHORT RRs (0x1000_<36bits>000) - HI: address bits [47:44], LO: address bits [43:12]3047* LONG RRs (0x<52bits>000) - HI: address bits [63:44], LO: address bits [43:12]3048*/3049WREG32(base + min_lo_reg_offset, lower_32_bits(val_min));3050WREG32(base + min_hi_reg_offset, upper_32_bits(val_min));3051WREG32(base + max_lo_reg_offset, lower_32_bits(val_max));3052WREG32(base + max_hi_reg_offset, upper_32_bits(val_max));3053}30543055static void gaudi2_write_hbw_rr_to_all_mstr_if(struct hl_device *hdev, u8 rr_type, u32 rr_index,3056u64 min_val, u64 max_val)3057{3058struct dup_block_ctx block_ctx;3059struct rr_config rr_cfg;30603061if ((rr_type == RR_TYPE_SHORT || rr_type == RR_TYPE_SHORT_PRIV) &&3062rr_index >= NUM_SHORT_HBW_RR) {30633064dev_err(hdev->dev, "invalid short HBW %s range register index: %u",3065rr_type == RR_TYPE_SHORT ? "secure" : "privileged", rr_index);3066return;3067}30683069if ((rr_type == RR_TYPE_LONG || rr_type == RR_TYPE_LONG_PRIV) &&3070rr_index >= NUM_LONG_HBW_RR) {30713072dev_err(hdev->dev, "invalid long HBW %s range register index: %u",3073rr_type == RR_TYPE_LONG ? "secure" : "privileged", rr_index);3074return;3075}30763077rr_cfg.type = rr_type;3078rr_cfg.index = rr_index;3079rr_cfg.min = min_val;3080rr_cfg.max = max_val;30813082block_ctx.instance_cfg_fn = &gaudi2_write_hbw_range_register;3083block_ctx.data = &rr_cfg;30843085/* SFT */3086block_ctx.base = mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE;3087block_ctx.blocks = NUM_OF_SFT;3088block_ctx.block_off = SFT_OFFSET;3089block_ctx.instances = SFT_NUM_OF_HBW_RTR;3090block_ctx.instance_off = SFT_IF_RTR_OFFSET;3091gaudi2_init_blocks(hdev, &block_ctx);30923093/* SIF */3094block_ctx.base = mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE;3095block_ctx.blocks = NUM_OF_DCORES;3096block_ctx.block_off = DCORE_OFFSET;3097block_ctx.instances = NUM_OF_RTR_PER_DCORE;3098block_ctx.instance_off = DCORE_RTR_OFFSET;3099gaudi2_init_blocks(hdev, &block_ctx);31003101/* PCIE MSTR */3102block_ctx.base = mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE;3103block_ctx.blocks = 1;3104block_ctx.block_off = 0;3105block_ctx.instances = 1;3106block_ctx.instance_off = 0;3107gaudi2_init_blocks(hdev, &block_ctx);3108}31093110static void gaudi2_init_hbw_range_registers(struct hl_device *hdev)3111{3112int i;31133114/* Up to 6 short RR (0x1000_<36bits>000) and 4 long RR (0x<52bits>000).3115*3116* - short range 0:3117* SPI Flash, ARC0/1 ICCM/DCCM, Secure Boot ROM, PSOC_FW/Scratchpad/PCIE_FW SRAM3118*/3119u64 hbw_range_min_short[] = {3120SPI_FLASH_BASE_ADDR3121};3122u64 hbw_range_max_short[] = {3123PCIE_FW_SRAM_ADDR + PCIE_FW_SRAM_SIZE3124};31253126for (i = 0 ; i < ARRAY_SIZE(hbw_range_min_short) ; i++) {3127gaudi2_write_hbw_rr_to_all_mstr_if(hdev, RR_TYPE_SHORT, i, hbw_range_min_short[i],3128hbw_range_max_short[i]);3129}3130}31313132static void gaudi2_write_mmu_range_register(struct hl_device *hdev, u64 base,3133struct rr_config *rr_cfg)3134{3135u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset;31363137switch (rr_cfg->type) {3138case RR_TYPE_LONG:3139min_lo_reg_offset = MMU_RR_SEC_MIN_31_0_0_OFFSET;3140min_hi_reg_offset = MMU_RR_SEC_MIN_63_32_0_OFFSET;3141max_lo_reg_offset = MMU_RR_SEC_MAX_31_0_0_OFFSET;3142max_hi_reg_offset = MMU_RR_SEC_MAX_63_32_0_OFFSET;3143break;31443145case RR_TYPE_LONG_PRIV:3146min_lo_reg_offset = MMU_RR_PRIV_MIN_31_0_0_OFFSET;3147min_hi_reg_offset = MMU_RR_PRIV_MIN_63_32_0_OFFSET;3148max_lo_reg_offset = MMU_RR_PRIV_MAX_31_0_0_OFFSET;3149max_hi_reg_offset = MMU_RR_PRIV_MAX_63_32_0_OFFSET;3150break;31513152default:3153dev_err(hdev->dev, "Invalid MMU RR type %u\n", rr_cfg->type);3154return;3155}31563157min_lo_reg_offset += rr_cfg->index * sizeof(u32);3158min_hi_reg_offset += rr_cfg->index * sizeof(u32);3159max_lo_reg_offset += rr_cfg->index * sizeof(u32);3160max_hi_reg_offset += rr_cfg->index * sizeof(u32);31613162/* Configure MMU RR (address bits [63:0]) */3163WREG32(base + min_lo_reg_offset, lower_32_bits(rr_cfg->min));3164WREG32(base + min_hi_reg_offset, upper_32_bits(rr_cfg->min));3165WREG32(base + max_lo_reg_offset, lower_32_bits(rr_cfg->max));3166WREG32(base + max_hi_reg_offset, upper_32_bits(rr_cfg->max));3167}31683169static void gaudi2_init_mmu_range_registers(struct hl_device *hdev)3170{3171u32 dcore_id, hmmu_id, hmmu_base;3172struct rr_config rr_cfg;31733174/* Up to 8 ranges [63:0].3175*3176* - range 0: Reserved HBM area for F/W and driver3177*/31783179/* The RRs are located after the HMMU so need to use the scrambled addresses */3180rr_cfg.min = hdev->asic_funcs->scramble_addr(hdev, DRAM_PHYS_BASE);3181rr_cfg.max = hdev->asic_funcs->scramble_addr(hdev, hdev->asic_prop.dram_user_base_address);3182rr_cfg.index = 0;3183rr_cfg.type = RR_TYPE_LONG;31843185for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {3186for (hmmu_id = 0 ; hmmu_id < NUM_OF_HMMU_PER_DCORE; hmmu_id++) {3187if (!gaudi2_is_hmmu_enabled(hdev, dcore_id, hmmu_id))3188continue;31893190hmmu_base = mmDCORE0_HMMU0_MMU_BASE + dcore_id * DCORE_OFFSET +3191hmmu_id * DCORE_HMMU_OFFSET;31923193gaudi2_write_mmu_range_register(hdev, hmmu_base, &rr_cfg);3194}3195}3196}31973198/**3199* gaudi2_init_range_registers -3200* Initialize range registers of all initiators3201*3202* @hdev: pointer to hl_device structure3203*/3204static void gaudi2_init_range_registers(struct hl_device *hdev)3205{3206gaudi2_init_lbw_range_registers(hdev);3207gaudi2_init_hbw_range_registers(hdev);3208gaudi2_init_mmu_range_registers(hdev);3209}32103211/**3212* gaudi2_init_protection_bits -3213* Initialize protection bits of specific registers3214*3215* @hdev: pointer to hl_device structure3216*3217* All protection bits are 1 by default, means not protected. Need to set to 03218* each bit that belongs to a protected register.3219*3220*/3221static int gaudi2_init_protection_bits(struct hl_device *hdev)3222{3223u32 *user_regs_array = NULL, user_regs_array_size = 0, engine_core_intr_reg;3224struct asic_fixed_properties *prop = &hdev->asic_prop;3225u32 instance_offset;3226int rc = 0;3227u8 i;32283229/* SFT */3230instance_offset = mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE;3231rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,3232gaudi2_pb_sft0, ARRAY_SIZE(gaudi2_pb_sft0),3233NULL, HL_PB_NA);32343235/* HIF */3236instance_offset = mmDCORE0_HIF1_BASE - mmDCORE0_HIF0_BASE;3237rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,3238NUM_OF_HIF_PER_DCORE, instance_offset,3239gaudi2_pb_dcr0_hif, ARRAY_SIZE(gaudi2_pb_dcr0_hif),3240NULL, HL_PB_NA, prop->hmmu_hif_enabled_mask);32413242/* RTR */3243instance_offset = mmDCORE0_RTR1_CTRL_BASE - mmDCORE0_RTR0_CTRL_BASE;3244rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,3245gaudi2_pb_dcr0_rtr0, ARRAY_SIZE(gaudi2_pb_dcr0_rtr0),3246NULL, HL_PB_NA);32473248/* HMMU */3249rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,3250NUM_OF_HMMU_PER_DCORE, DCORE_HMMU_OFFSET,3251gaudi2_pb_dcr0_hmmu0, ARRAY_SIZE(gaudi2_pb_dcr0_hmmu0),3252NULL, HL_PB_NA, prop->hmmu_hif_enabled_mask);32533254/* CPU.3255* Except for CPU_IF, skip when security is enabled in F/W, because the blocks are protected3256* by privileged RR.3257*/3258rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,3259HL_PB_SINGLE_INSTANCE, HL_PB_NA,3260gaudi2_pb_cpu_if, ARRAY_SIZE(gaudi2_pb_cpu_if),3261NULL, HL_PB_NA);32623263if (!hdev->asic_prop.fw_security_enabled)3264rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,3265HL_PB_SINGLE_INSTANCE, HL_PB_NA,3266gaudi2_pb_cpu, ARRAY_SIZE(gaudi2_pb_cpu),3267NULL, HL_PB_NA);32683269/* KDMA */3270rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,3271HL_PB_SINGLE_INSTANCE, HL_PB_NA,3272gaudi2_pb_kdma, ARRAY_SIZE(gaudi2_pb_kdma),3273NULL, HL_PB_NA);32743275/* PDMA */3276instance_offset = mmPDMA1_CORE_BASE - mmPDMA0_CORE_BASE;3277rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,3278gaudi2_pb_pdma0, ARRAY_SIZE(gaudi2_pb_pdma0),3279gaudi2_pb_pdma0_unsecured_regs,3280ARRAY_SIZE(gaudi2_pb_pdma0_unsecured_regs));32813282/* ARC PDMA */3283rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 2,3284instance_offset, gaudi2_pb_pdma0_arc,3285ARRAY_SIZE(gaudi2_pb_pdma0_arc),3286gaudi2_pb_pdma0_arc_unsecured_regs,3287ARRAY_SIZE(gaudi2_pb_pdma0_arc_unsecured_regs));32883289/* EDMA */3290instance_offset = mmDCORE0_EDMA1_CORE_BASE - mmDCORE0_EDMA0_CORE_BASE;3291rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,3292instance_offset, gaudi2_pb_dcr0_edma0,3293ARRAY_SIZE(gaudi2_pb_dcr0_edma0),3294gaudi2_pb_dcr0_edma0_unsecured_regs,3295ARRAY_SIZE(gaudi2_pb_dcr0_edma0_unsecured_regs),3296prop->edma_enabled_mask);32973298/* ARC EDMA */3299rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,3300instance_offset, gaudi2_pb_dcr0_edma0_arc,3301ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc),3302gaudi2_pb_dcr0_edma0_arc_unsecured_regs,3303ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc_unsecured_regs),3304prop->edma_enabled_mask);33053306/* MME */3307instance_offset = mmDCORE0_MME_SBTE1_BASE - mmDCORE0_MME_SBTE0_BASE;33083309for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {3310/* MME SBTE */3311rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5,3312instance_offset, gaudi2_pb_dcr0_mme_sbte,3313ARRAY_SIZE(gaudi2_pb_dcr0_mme_sbte), NULL,3314HL_PB_NA);33153316/* MME */3317rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i),3318HL_PB_SINGLE_INSTANCE, HL_PB_NA,3319gaudi2_pb_dcr0_mme_eng,3320ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng),3321gaudi2_pb_dcr0_mme_eng_unsecured_regs,3322ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng_unsecured_regs));3323}33243325/*3326* we have special iteration for case in which we would like to3327* configure stubbed MME's ARC/QMAN3328*/3329for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {3330/* MME QM */3331rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i),3332HL_PB_SINGLE_INSTANCE, HL_PB_NA,3333gaudi2_pb_dcr0_mme_qm,3334ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm),3335gaudi2_pb_dcr0_mme_qm_unsecured_regs,3336ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm_unsecured_regs));33373338/* ARC MME */3339rc |= hl_init_pb_ranges_single_dcore(hdev, (DCORE_OFFSET * i),3340HL_PB_SINGLE_INSTANCE, HL_PB_NA,3341gaudi2_pb_dcr0_mme_arc,3342ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc),3343gaudi2_pb_dcr0_mme_arc_unsecured_regs,3344ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc_unsecured_regs));3345}33463347/* MME QM ARC ACP ENG */3348rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,3349HL_PB_SINGLE_INSTANCE, HL_PB_NA,3350gaudi2_pb_mme_qm_arc_acp_eng,3351ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng),3352gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs,3353ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs),3354(BIT(NUM_OF_DCORES * NUM_OF_MME_PER_DCORE) - 1));33553356/* TPC */3357rc |= gaudi2_init_pb_tpc(hdev);3358rc |= gaudi2_init_pb_tpc_arc(hdev);33593360/* SRAM */3361instance_offset = mmDCORE0_SRAM1_BANK_BASE - mmDCORE0_SRAM0_BANK_BASE;3362rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,3363gaudi2_pb_dcr0_sram0, ARRAY_SIZE(gaudi2_pb_dcr0_sram0),3364NULL, HL_PB_NA);33653366/* Sync Manager MSTR IF */3367rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET,3368HL_PB_SINGLE_INSTANCE, HL_PB_NA,3369gaudi2_pb_dcr0_sm_mstr_if,3370ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if),3371NULL, HL_PB_NA);33723373/* Sync Manager GLBL */33743375/* Secure Dcore0 CQ0 registers */3376rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA,3377HL_PB_SINGLE_INSTANCE, HL_PB_NA,3378gaudi2_pb_dcr0_sm_glbl,3379ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl),3380gaudi2_pb_dcr0_sm_glbl_unsecured_regs,3381ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl_unsecured_regs));33823383/* Unsecure all other CQ registers */3384rc |= hl_init_pb_ranges(hdev, NUM_OF_DCORES - 1, DCORE_OFFSET,3385HL_PB_SINGLE_INSTANCE, HL_PB_NA,3386gaudi2_pb_dcr1_sm_glbl,3387ARRAY_SIZE(gaudi2_pb_dcr1_sm_glbl),3388gaudi2_pb_dcr_x_sm_glbl_unsecured_regs,3389ARRAY_SIZE(gaudi2_pb_dcr_x_sm_glbl_unsecured_regs));33903391/* PSOC.3392* Except for PSOC_GLOBAL_CONF, skip when security is enabled in F/W, because the blocks are3393* protected by privileged RR.3394* For PSOC_GLOBAL_CONF, need to un-secure the scratchpad register which is used for engine3395* cores to raise events towards F/W.3396*/3397engine_core_intr_reg = (u32) (hdev->asic_prop.engine_core_interrupt_reg_addr - CFG_BASE);3398if (engine_core_intr_reg >= mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 &&3399engine_core_intr_reg <= mmPSOC_GLOBAL_CONF_SCRATCHPAD_31) {3400user_regs_array = &engine_core_intr_reg;3401user_regs_array_size = 1;3402} else {3403dev_err(hdev->dev,3404"Engine cores register for interrupts (%#x) is not a PSOC scratchpad register\n",3405engine_core_intr_reg);3406}34073408rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,3409HL_PB_SINGLE_INSTANCE, HL_PB_NA,3410gaudi2_pb_psoc_global_conf, ARRAY_SIZE(gaudi2_pb_psoc_global_conf),3411user_regs_array, user_regs_array_size);34123413if (!hdev->asic_prop.fw_security_enabled)3414rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,3415HL_PB_SINGLE_INSTANCE, HL_PB_NA,3416gaudi2_pb_psoc, ARRAY_SIZE(gaudi2_pb_psoc),3417NULL, HL_PB_NA);34183419/* PMMU */3420rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,3421HL_PB_SINGLE_INSTANCE, HL_PB_NA,3422gaudi2_pb_pmmu, ARRAY_SIZE(gaudi2_pb_pmmu),3423NULL, HL_PB_NA);34243425/* PLL.3426* Skip PSOC/XFT PLL when security is enabled in F/W, because these blocks are protected by3427* privileged RR.3428*/3429rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,3430HL_PB_SINGLE_INSTANCE, HL_PB_NA,3431gaudi2_pb_pmmu_pll, ARRAY_SIZE(gaudi2_pb_pmmu_pll),3432NULL, HL_PB_NA);3433rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,3434HL_PB_SINGLE_INSTANCE, HL_PB_NA,3435gaudi2_pb_xbar_pll, ARRAY_SIZE(gaudi2_pb_xbar_pll),3436NULL, HL_PB_NA);34373438if (!hdev->asic_prop.fw_security_enabled) {3439rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,3440HL_PB_SINGLE_INSTANCE, HL_PB_NA,3441gaudi2_pb_psoc_pll, ARRAY_SIZE(gaudi2_pb_psoc_pll),3442NULL, HL_PB_NA);3443rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,3444HL_PB_SINGLE_INSTANCE, HL_PB_NA,3445gaudi2_pb_xft_pll, ARRAY_SIZE(gaudi2_pb_xft_pll),3446NULL, HL_PB_NA);3447}34483449/* PCIE */3450rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,3451HL_PB_SINGLE_INSTANCE, HL_PB_NA,3452gaudi2_pb_pcie, ARRAY_SIZE(gaudi2_pb_pcie),3453gaudi2_pb_pcie_unsecured_regs,3454ARRAY_SIZE(gaudi2_pb_pcie_unsecured_regs));34553456/* Thermal Sensor.3457* Skip when security is enabled in F/W, because the blocks are protected by privileged RR.3458*/3459if (!hdev->asic_prop.fw_security_enabled) {3460instance_offset = mmDCORE1_XFT_BASE - mmDCORE0_XFT_BASE;3461rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,3462gaudi2_pb_thermal_sensor0,3463ARRAY_SIZE(gaudi2_pb_thermal_sensor0), NULL, HL_PB_NA);3464}34653466/* Scheduler ARCs */3467instance_offset = mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE;3468rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA,3469NUM_OF_ARC_FARMS_ARC,3470instance_offset, gaudi2_pb_arc_sched,3471ARRAY_SIZE(gaudi2_pb_arc_sched),3472gaudi2_pb_arc_sched_unsecured_regs,3473ARRAY_SIZE(gaudi2_pb_arc_sched_unsecured_regs));34743475/* XBAR MIDs */3476instance_offset = mmXBAR_MID_1_BASE - mmXBAR_MID_0_BASE;3477rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,3478instance_offset, gaudi2_pb_xbar_mid,3479ARRAY_SIZE(gaudi2_pb_xbar_mid),3480gaudi2_pb_xbar_mid_unsecured_regs,3481ARRAY_SIZE(gaudi2_pb_xbar_mid_unsecured_regs));34823483/* XBAR EDGEs */3484instance_offset = mmXBAR_EDGE_1_BASE - mmXBAR_EDGE_0_BASE;3485rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,3486instance_offset, gaudi2_pb_xbar_edge,3487ARRAY_SIZE(gaudi2_pb_xbar_edge),3488gaudi2_pb_xbar_edge_unsecured_regs,3489ARRAY_SIZE(gaudi2_pb_xbar_edge_unsecured_regs),3490prop->xbar_edge_enabled_mask);34913492/* NIC */3493rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET,3494HL_PB_SINGLE_INSTANCE, HL_PB_NA,3495gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0),3496NULL, HL_PB_NA, hdev->nic_ports_mask);34973498/* NIC QM and QPC */3499rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET,3500NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET,3501gaudi2_pb_nic0_qm_qpc, ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc),3502gaudi2_pb_nic0_qm_qpc_unsecured_regs,3503ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc_unsecured_regs),3504hdev->nic_ports_mask);35053506/* NIC QM ARC */3507rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS,3508NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET,3509gaudi2_pb_nic0_qm_arc_aux0,3510ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0),3511gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs,3512ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs),3513hdev->nic_ports_mask);35143515/* NIC UMR */3516rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS,3517NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET,3518gaudi2_pb_nic0_umr,3519ARRAY_SIZE(gaudi2_pb_nic0_umr),3520gaudi2_pb_nic0_umr_unsecured_regs,3521ARRAY_SIZE(gaudi2_pb_nic0_umr_unsecured_regs),3522hdev->nic_ports_mask);35233524/* Rotators */3525instance_offset = mmROT1_BASE - mmROT0_BASE;3526rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT,3527instance_offset, gaudi2_pb_rot0,3528ARRAY_SIZE(gaudi2_pb_rot0),3529gaudi2_pb_rot0_unsecured_regs,3530ARRAY_SIZE(gaudi2_pb_rot0_unsecured_regs),3531(BIT(NUM_OF_ROT) - 1));35323533/* Rotators ARCS */3534rc |= hl_init_pb_ranges_with_mask(hdev, HL_PB_SHARED,3535HL_PB_NA, NUM_OF_ROT, instance_offset,3536gaudi2_pb_rot0_arc, ARRAY_SIZE(gaudi2_pb_rot0_arc),3537gaudi2_pb_rot0_arc_unsecured_regs,3538ARRAY_SIZE(gaudi2_pb_rot0_arc_unsecured_regs),3539(BIT(NUM_OF_ROT) - 1));35403541rc |= gaudi2_init_pb_sm_objs(hdev);35423543return rc;3544}35453546/**3547* gaudi2_init_security - Initialize security model3548*3549* @hdev: pointer to hl_device structure3550*3551* Initialize the security model of the device3552* That includes range registers and protection bit per register.3553*/3554int gaudi2_init_security(struct hl_device *hdev)3555{3556int rc;35573558rc = gaudi2_init_protection_bits(hdev);3559if (rc)3560return rc;35613562gaudi2_init_range_registers(hdev);35633564return 0;3565}35663567struct gaudi2_ack_pb_tpc_data {3568u32 tpc_regs_array_size;3569u32 arc_tpc_regs_array_size;3570};35713572static void gaudi2_ack_pb_tpc_config(struct hl_device *hdev, int dcore, int inst, u32 offset,3573struct iterate_module_ctx *ctx)3574{3575struct gaudi2_ack_pb_tpc_data *pb_data = ctx->data;35763577hl_ack_pb_single_dcore(hdev, offset, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3578gaudi2_pb_dcr0_tpc0, pb_data->tpc_regs_array_size);35793580hl_ack_pb_single_dcore(hdev, offset, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3581gaudi2_pb_dcr0_tpc0_arc, pb_data->arc_tpc_regs_array_size);3582}35833584static void gaudi2_ack_pb_tpc(struct hl_device *hdev)3585{3586struct iterate_module_ctx tpc_iter = {3587.fn = &gaudi2_ack_pb_tpc_config,3588};3589struct gaudi2_ack_pb_tpc_data data;35903591data.tpc_regs_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0);3592data.arc_tpc_regs_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc);3593tpc_iter.data = &data;35943595gaudi2_iterate_tpcs(hdev, &tpc_iter);3596}35973598/**3599* gaudi2_ack_protection_bits_errors - scan all blocks having protection bits3600* and for every protection error found, display the appropriate error message3601* and clear the error.3602*3603* @hdev: pointer to hl_device structure3604*3605* All protection bits are 1 by default, means not protected. Need to set to 03606* each bit that belongs to a protected register.3607*3608*/3609void gaudi2_ack_protection_bits_errors(struct hl_device *hdev)3610{3611struct asic_fixed_properties *prop = &hdev->asic_prop;3612u32 instance_offset;3613u8 i;36143615/* SFT */3616instance_offset = mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE;3617hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,3618gaudi2_pb_sft0, ARRAY_SIZE(gaudi2_pb_sft0));36193620/* HIF */3621instance_offset = mmDCORE0_HIF1_BASE - mmDCORE0_HIF0_BASE;3622hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,3623NUM_OF_HIF_PER_DCORE, instance_offset,3624gaudi2_pb_dcr0_hif, ARRAY_SIZE(gaudi2_pb_dcr0_hif),3625prop->hmmu_hif_enabled_mask);36263627/* RTR */3628instance_offset = mmDCORE0_RTR1_CTRL_BASE - mmDCORE0_RTR0_CTRL_BASE;3629hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,3630gaudi2_pb_dcr0_rtr0, ARRAY_SIZE(gaudi2_pb_dcr0_rtr0));36313632/* HMMU */3633hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,3634NUM_OF_HMMU_PER_DCORE, DCORE_HMMU_OFFSET,3635gaudi2_pb_dcr0_hmmu0, ARRAY_SIZE(gaudi2_pb_dcr0_hmmu0),3636prop->hmmu_hif_enabled_mask);36373638/* CPU.3639* Except for CPU_IF, skip when security is enabled in F/W, because the blocks are protected3640* by privileged RR.3641*/3642hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3643gaudi2_pb_cpu_if, ARRAY_SIZE(gaudi2_pb_cpu_if));3644if (!hdev->asic_prop.fw_security_enabled)3645hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3646gaudi2_pb_cpu, ARRAY_SIZE(gaudi2_pb_cpu));36473648/* KDMA */3649hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3650gaudi2_pb_kdma, ARRAY_SIZE(gaudi2_pb_kdma));36513652/* PDMA */3653instance_offset = mmPDMA1_CORE_BASE - mmPDMA0_CORE_BASE;3654hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,3655gaudi2_pb_pdma0, ARRAY_SIZE(gaudi2_pb_pdma0));36563657/* ARC PDMA */3658hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,3659gaudi2_pb_pdma0_arc, ARRAY_SIZE(gaudi2_pb_pdma0_arc));36603661/* EDMA */3662instance_offset = mmDCORE0_EDMA1_CORE_BASE - mmDCORE0_EDMA0_CORE_BASE;3663hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,3664instance_offset, gaudi2_pb_dcr0_edma0,3665ARRAY_SIZE(gaudi2_pb_dcr0_edma0),3666prop->edma_enabled_mask);36673668/* ARC EDMA */3669hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,3670instance_offset, gaudi2_pb_dcr0_edma0_arc,3671ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc),3672prop->edma_enabled_mask);36733674/* MME */3675instance_offset = mmDCORE0_MME_SBTE1_BASE - mmDCORE0_MME_SBTE0_BASE;36763677for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {3678/* MME SBTE */3679hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5,3680instance_offset, gaudi2_pb_dcr0_mme_sbte,3681ARRAY_SIZE(gaudi2_pb_dcr0_mme_sbte));36823683/* MME */3684hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),3685HL_PB_SINGLE_INSTANCE, HL_PB_NA,3686gaudi2_pb_dcr0_mme_eng,3687ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng));3688}36893690/*3691* we have special iteration for case in which we would like to3692* configure stubbed MME's ARC/QMAN3693*/3694for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {3695/* MME QM */3696hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),3697HL_PB_SINGLE_INSTANCE, HL_PB_NA,3698gaudi2_pb_dcr0_mme_qm,3699ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm));37003701/* ARC MME */3702hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),3703HL_PB_SINGLE_INSTANCE, HL_PB_NA,3704gaudi2_pb_dcr0_mme_arc,3705ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc));3706}37073708/* MME QM ARC ACP ENG */3709hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,3710HL_PB_SINGLE_INSTANCE, HL_PB_NA,3711gaudi2_pb_mme_qm_arc_acp_eng,3712ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng),3713(BIT(NUM_OF_DCORES * NUM_OF_MME_PER_DCORE) - 1));37143715/* TPC */3716gaudi2_ack_pb_tpc(hdev);37173718/* SRAM */3719instance_offset = mmDCORE0_SRAM1_BANK_BASE - mmDCORE0_SRAM0_BANK_BASE;3720hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,3721gaudi2_pb_dcr0_sram0, ARRAY_SIZE(gaudi2_pb_dcr0_sram0));37223723/* Sync Manager MSTR IF */3724hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3725gaudi2_pb_dcr0_sm_mstr_if, ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if));37263727/* Sync Manager */3728hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3729gaudi2_pb_dcr0_sm_glbl, ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl));37303731hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3732gaudi2_pb_dcr0_sm_mstr_if, ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if));37333734/* PSOC.3735* Except for PSOC_GLOBAL_CONF, skip when security is enabled in F/W, because the blocks are3736* protected by privileged RR.3737*/3738hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3739gaudi2_pb_psoc_global_conf, ARRAY_SIZE(gaudi2_pb_psoc_global_conf));3740if (!hdev->asic_prop.fw_security_enabled)3741hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3742gaudi2_pb_psoc, ARRAY_SIZE(gaudi2_pb_psoc));37433744/* PMMU */3745hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3746gaudi2_pb_pmmu, ARRAY_SIZE(gaudi2_pb_pmmu));37473748/* PLL.3749* Skip PSOC/XFT PLL when security is enabled in F/W, because these blocks are protected by3750* privileged RR.3751*/3752hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3753gaudi2_pb_pmmu_pll, ARRAY_SIZE(gaudi2_pb_pmmu_pll));3754hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3755gaudi2_pb_xbar_pll, ARRAY_SIZE(gaudi2_pb_xbar_pll));3756if (!hdev->asic_prop.fw_security_enabled) {3757hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3758gaudi2_pb_psoc_pll, ARRAY_SIZE(gaudi2_pb_psoc_pll));3759hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3760gaudi2_pb_xft_pll, ARRAY_SIZE(gaudi2_pb_xft_pll));3761}37623763/* PCIE */3764hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3765gaudi2_pb_pcie, ARRAY_SIZE(gaudi2_pb_pcie));37663767/* Thermal Sensor.3768* Skip when security is enabled in F/W, because the blocks are protected by privileged RR.3769*/3770if (!hdev->asic_prop.fw_security_enabled) {3771instance_offset = mmDCORE1_XFT_BASE - mmDCORE0_XFT_BASE;3772hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,3773gaudi2_pb_thermal_sensor0, ARRAY_SIZE(gaudi2_pb_thermal_sensor0));3774}37753776/* HBM */3777instance_offset = mmHBM1_MC0_BASE - mmHBM0_MC0_BASE;3778hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, GAUDI2_HBM_NUM,3779instance_offset, gaudi2_pb_hbm,3780ARRAY_SIZE(gaudi2_pb_hbm), prop->dram_enabled_mask);37813782/* Scheduler ARCs */3783instance_offset = mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE;3784hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ARC_FARMS_ARC,3785instance_offset, gaudi2_pb_arc_sched,3786ARRAY_SIZE(gaudi2_pb_arc_sched));37873788/* XBAR MIDs */3789instance_offset = mmXBAR_MID_1_BASE - mmXBAR_MID_0_BASE;3790hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,3791instance_offset, gaudi2_pb_xbar_mid,3792ARRAY_SIZE(gaudi2_pb_xbar_mid));37933794/* XBAR EDGEs */3795instance_offset = mmXBAR_EDGE_1_BASE - mmXBAR_EDGE_0_BASE;3796hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,3797instance_offset, gaudi2_pb_xbar_edge,3798ARRAY_SIZE(gaudi2_pb_xbar_edge), prop->xbar_edge_enabled_mask);37993800/* NIC */3801hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,3802gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0), hdev->nic_ports_mask);38033804/* NIC QM and QPC */3805hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,3806NIC_QM_OFFSET, gaudi2_pb_nic0_qm_qpc, ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc),3807hdev->nic_ports_mask);38083809/* NIC QM ARC */3810hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,3811NIC_QM_OFFSET, gaudi2_pb_nic0_qm_arc_aux0,3812ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0), hdev->nic_ports_mask);38133814/* NIC UMR */3815hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,3816NIC_QM_OFFSET, gaudi2_pb_nic0_umr, ARRAY_SIZE(gaudi2_pb_nic0_umr),3817hdev->nic_ports_mask);38183819/* Rotators */3820instance_offset = mmROT1_BASE - mmROT0_BASE;3821hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset,3822gaudi2_pb_rot0, ARRAY_SIZE(gaudi2_pb_rot0), (BIT(NUM_OF_ROT) - 1));38233824/* Rotators ARCS */3825hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset,3826gaudi2_pb_rot0_arc, ARRAY_SIZE(gaudi2_pb_rot0_arc), (BIT(NUM_OF_ROT) - 1));3827}38283829/*3830* Print PB security errors3831*/38323833void gaudi2_pb_print_security_errors(struct hl_device *hdev, u32 block_addr, u32 cause,3834u32 offended_addr)3835{3836int i = 0;3837const char *error_format =3838"Security error at block 0x%x, offending address 0x%x\n"3839"Cause 0x%x: %s %s %s %s %s %s %s %s\n";3840char *mcause[8] = {"Unknown", "", "", "", "", "", "", "" };38413842if (!cause)3843return;38443845if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD)3846mcause[i++] = "APB_PRIV_RD";38473848if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD)3849mcause[i++] = "APB_SEC_RD";38503851if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD)3852mcause[i++] = "APB_UNMAPPED_RD";38533854if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR)3855mcause[i++] = "APB_PRIV_WR";38563857if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR)3858mcause[i++] = "APB_SEC_WR";38593860if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR)3861mcause[i++] = "APB_UNMAPPED_WR";38623863if (cause & SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR)3864mcause[i++] = "EXT_SEC_WR";38653866if (cause & SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR)3867mcause[i++] = "APB_EXT_UNMAPPED_WR";38683869dev_err_ratelimited(hdev->dev, error_format, block_addr, offended_addr,3870cause, mcause[0], mcause[1], mcause[2], mcause[3],3871mcause[4], mcause[5], mcause[6], mcause[7]);3872}387338743875