Book a Demo!
CoCalc Logo Icon
StoreFeaturesDocsShareSupportNewsAboutPoliciesSign UpSign In
torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h
26428 views
1
/* SPDX-License-Identifier: GPL-2.0-only */

2
/*

3
 * Copyright (C) 2020-2023 Intel Corporation

4
 */

5


6
#ifndef __IVPU_HW_BTRS_MTL_REG_H__

7
#define __IVPU_HW_BTRS_MTL_REG_H__

8


9
#include <linux/bits.h>

10


11
#define VPU_HW_BTRS_MTL_INTERRUPT_TYPE				0x00000000u

12


13
#define VPU_HW_BTRS_MTL_INTERRUPT_STAT				0x00000004u

14
#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_FREQ_CHANGE_MASK		BIT_MASK(0)

15
#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_ATS_ERR_MASK		BIT_MASK(1)

16
#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_UFI_ERR_MASK		BIT_MASK(2)

17


18
#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0				0x00000008u

19
#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0_MIN_RATIO_MASK		GENMASK(15, 0)

20
#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0_MAX_RATIO_MASK		GENMASK(31, 16)

21


22
#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1				0x0000000cu

23
#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK	GENMASK(15, 0)

24
#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1_EPP_MASK		GENMASK(31, 16)

25


26
#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2				0x00000010u

27
#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2_CONFIG_MASK		GENMASK(15, 0)

28


29
#define VPU_HW_BTRS_MTL_WP_REQ_CMD				0x00000014u

30
#define VPU_HW_BTRS_MTL_WP_REQ_CMD_SEND_MASK			BIT_MASK(0)

31


32
#define VPU_HW_BTRS_MTL_WP_DOWNLOAD				0x00000018u

33
#define VPU_HW_BTRS_MTL_WP_DOWNLOAD_TARGET_RATIO_MASK		GENMASK(15, 0)

34


35
#define VPU_HW_BTRS_MTL_CURRENT_PLL				0x0000001cu

36
#define VPU_HW_BTRS_MTL_CURRENT_PLL_RATIO_MASK			GENMASK(15, 0)

37


38
#define VPU_HW_BTRS_MTL_PLL_ENABLE				0x00000020u

39


40
#define VPU_HW_BTRS_MTL_FMIN_FUSE				0x00000024u

41
#define VPU_HW_BTRS_MTL_FMIN_FUSE_MIN_RATIO_MASK		GENMASK(7, 0)

42
#define VPU_HW_BTRS_MTL_FMIN_FUSE_PN_RATIO_MASK			GENMASK(15, 8)

43


44
#define VPU_HW_BTRS_MTL_FMAX_FUSE				0x00000028u

45
#define VPU_HW_BTRS_MTL_FMAX_FUSE_MAX_RATIO_MASK		GENMASK(7, 0)

46


47
#define VPU_HW_BTRS_MTL_TILE_FUSE				0x0000002cu

48
#define VPU_HW_BTRS_MTL_TILE_FUSE_VALID_MASK			BIT_MASK(0)

49
#define VPU_HW_BTRS_MTL_TILE_FUSE_SKU_MASK			GENMASK(3, 2)

50


51
#define VPU_HW_BTRS_MTL_LOCAL_INT_MASK				0x00000030u

52
#define VPU_HW_BTRS_MTL_GLOBAL_INT_MASK				0x00000034u

53


54
#define VPU_HW_BTRS_MTL_PLL_STATUS				0x00000040u

55
#define VPU_HW_BTRS_MTL_PLL_STATUS_LOCK_MASK			BIT_MASK(1)

56


57
#define VPU_HW_BTRS_MTL_VPU_STATUS				0x00000044u

58
#define VPU_HW_BTRS_MTL_VPU_STATUS_READY_MASK			BIT_MASK(0)

59
#define VPU_HW_BTRS_MTL_VPU_STATUS_IDLE_MASK			BIT_MASK(1)

60


61
#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL			0x00000060u

62
#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL_INPROGRESS_MASK	BIT_MASK(0)

63
#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL_I3_MASK		BIT_MASK(2)

64


65
#define VPU_HW_BTRS_MTL_VPU_IP_RESET				0x00000050u

66
#define VPU_HW_BTRS_MTL_VPU_IP_RESET_TRIGGER_MASK		BIT_MASK(0)

67


68
#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_OFFSET			0x00000080u

69
#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_SIZE			0x00000084u

70
#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_ENABLE			0x00000088u

71


72
#define VPU_HW_BTRS_MTL_ATS_ERR_LOG_0				0x000000a0u

73
#define VPU_HW_BTRS_MTL_ATS_ERR_LOG_1				0x000000a4u

74
#define VPU_HW_BTRS_MTL_ATS_ERR_CLEAR				0x000000a8u

75


76
#define VPU_HW_BTRS_MTL_UFI_ERR_LOG				0x000000b0u

77
#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_CQ_ID_MASK			GENMASK(11, 0)

78
#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_AXI_ID_MASK			GENMASK(19, 12)

79
#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_OPCODE_MASK			GENMASK(24, 20)

80


81
#define VPU_HW_BTRS_MTL_UFI_ERR_CLEAR				0x000000b4u

82


83
#endif /* __IVPU_HW_BTRS_MTL_REG_H__ */

84


85