CoCalc -- idt77252.c

GitHub Repository: torvalds/linux
Path: blob/master/drivers/atm/idt77252.c
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/******************************************************************* 
2
 *
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 * Copyright (c) 2000 ATecoM GmbH 
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 *
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 * The author may be reached at [email protected].
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 *
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 * This program is free software; you can redistribute  it and/or modify it
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 * under  the terms of  the GNU General  Public License as published by the
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 * Free Software Foundation;  either version 2 of the  License, or (at your
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 * option) any later version.
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 *
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 * THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR   IMPLIED
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 * WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
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 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
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 * NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
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 * USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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 * ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 *
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 * You should have received a copy of the  GNU General Public License along
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 * with this program; if not, write  to the Free Software Foundation, Inc.,
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 * 675 Mass Ave, Cambridge, MA 02139, USA.
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 *
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 *******************************************************************/
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#include <linux/module.h>
30
#include <linux/pci.h>
31
#include <linux/poison.h>
32
#include <linux/skbuff.h>
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#include <linux/kernel.h>
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#include <linux/vmalloc.h>
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#include <linux/netdevice.h>
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#include <linux/atmdev.h>
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#include <linux/atm.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/bitops.h>
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#include <linux/wait.h>
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#include <linux/jiffies.h>
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#include <linux/mutex.h>
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#include <linux/slab.h>
46

47
#include <asm/io.h>
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#include <linux/uaccess.h>
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#include <linux/atomic.h>
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#include <asm/byteorder.h>
51

52
#ifdef CONFIG_ATM_IDT77252_USE_SUNI
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#include "suni.h"
54
#endif /* CONFIG_ATM_IDT77252_USE_SUNI */
55

56

57
#include "idt77252.h"
58
#include "idt77252_tables.h"
59

60
static unsigned int vpibits = 1;
61

62

63
#define ATM_IDT77252_SEND_IDLE 1
64

65

66
/*
67
 * Debug HACKs.
68
 */
69
#define DEBUG_MODULE 1
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#undef HAVE_EEPROM	/* does not work, yet. */
71

72
#ifdef CONFIG_ATM_IDT77252_DEBUG
73
static unsigned long debug = DBG_GENERAL;
74
#endif
75

76

77
#define SAR_RX_DELAY	(SAR_CFG_RXINT_NODELAY)
78

79

80
/*
81
 * SCQ Handling.
82
 */
83
static struct scq_info *alloc_scq(struct idt77252_dev *, int);
84
static void free_scq(struct idt77252_dev *, struct scq_info *);
85
static int queue_skb(struct idt77252_dev *, struct vc_map *,
86
		     struct sk_buff *, int oam);
87
static void drain_scq(struct idt77252_dev *, struct vc_map *);
88
static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *);
89
static void fill_scd(struct idt77252_dev *, struct scq_info *, int);
90

91
/*
92
 * FBQ Handling.
93
 */
94
static int push_rx_skb(struct idt77252_dev *,
95
		       struct sk_buff *, int queue);
96
static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *);
97
static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *);
98
static void recycle_rx_pool_skb(struct idt77252_dev *,
99
				struct rx_pool *);
100
static void add_rx_skb(struct idt77252_dev *, int queue,
101
		       unsigned int size, unsigned int count);
102

103
/*
104
 * RSQ Handling.
105
 */
106
static int init_rsq(struct idt77252_dev *);
107
static void deinit_rsq(struct idt77252_dev *);
108
static void idt77252_rx(struct idt77252_dev *);
109

110
/*
111
 * TSQ handling.
112
 */
113
static int init_tsq(struct idt77252_dev *);
114
static void deinit_tsq(struct idt77252_dev *);
115
static void idt77252_tx(struct idt77252_dev *);
116

117

118
/*
119
 * ATM Interface.
120
 */
121
static void idt77252_dev_close(struct atm_dev *dev);
122
static int idt77252_open(struct atm_vcc *vcc);
123
static void idt77252_close(struct atm_vcc *vcc);
124
static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb);
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static int idt77252_send_oam(struct atm_vcc *vcc, void *cell,
126
			     int flags);
127
static void idt77252_phy_put(struct atm_dev *dev, unsigned char value,
128
			     unsigned long addr);
129
static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr);
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static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos,
131
			       int flags);
132
static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos,
133
			      char *page);
134
static void idt77252_softint(struct work_struct *work);
135

136

137
static const struct atmdev_ops idt77252_ops =
138
{
139
	.dev_close	= idt77252_dev_close,
140
	.open		= idt77252_open,
141
	.close		= idt77252_close,
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	.send		= idt77252_send,
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	.send_oam	= idt77252_send_oam,
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	.phy_put	= idt77252_phy_put,
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	.phy_get	= idt77252_phy_get,
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	.change_qos	= idt77252_change_qos,
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	.proc_read	= idt77252_proc_read,
148
	.owner		= THIS_MODULE
149
};
150

151
static struct idt77252_dev *idt77252_chain = NULL;
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static unsigned int idt77252_sram_write_errors = 0;
153

154
/*****************************************************************************/
155
/*                                                                           */
156
/* I/O and Utility Bus                                                       */
157
/*                                                                           */
158
/*****************************************************************************/
159

160
static void
161
waitfor_idle(struct idt77252_dev *card)
162
{
163
	u32 stat;
164

165
	stat = readl(SAR_REG_STAT);
166
	while (stat & SAR_STAT_CMDBZ)
167
		stat = readl(SAR_REG_STAT);
168
}
169

170
static u32
171
read_sram(struct idt77252_dev *card, unsigned long addr)
172
{
173
	unsigned long flags;
174
	u32 value;
175

176
	spin_lock_irqsave(&card->cmd_lock, flags);
177
	writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD);
178
	waitfor_idle(card);
179
	value = readl(SAR_REG_DR0);
180
	spin_unlock_irqrestore(&card->cmd_lock, flags);
181
	return value;
182
}
183

184
static void
185
write_sram(struct idt77252_dev *card, unsigned long addr, u32 value)
186
{
187
	unsigned long flags;
188

189
	if ((idt77252_sram_write_errors == 0) &&
190
	    (((addr > card->tst[0] + card->tst_size - 2) &&
191
	      (addr < card->tst[0] + card->tst_size)) ||
192
	     ((addr > card->tst[1] + card->tst_size - 2) &&
193
	      (addr < card->tst[1] + card->tst_size)))) {
194
		printk("%s: ERROR: TST JMP section at %08lx written: %08x\n",
195
		       card->name, addr, value);
196
	}
197

198
	spin_lock_irqsave(&card->cmd_lock, flags);
199
	writel(value, SAR_REG_DR0);
200
	writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
201
	waitfor_idle(card);
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	spin_unlock_irqrestore(&card->cmd_lock, flags);
203
}
204

205
static u8
206
read_utility(void *dev, unsigned long ubus_addr)
207
{
208
	struct idt77252_dev *card = dev;
209
	unsigned long flags;
210
	u8 value;
211

212
	if (!card) {
213
		printk("Error: No such device.\n");
214
		return -1;
215
	}
216

217
	spin_lock_irqsave(&card->cmd_lock, flags);
218
	writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD);
219
	waitfor_idle(card);
220
	value = readl(SAR_REG_DR0);
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	spin_unlock_irqrestore(&card->cmd_lock, flags);
222
	return value;
223
}
224

225
static void
226
write_utility(void *dev, unsigned long ubus_addr, u8 value)
227
{
228
	struct idt77252_dev *card = dev;
229
	unsigned long flags;
230

231
	if (!card) {
232
		printk("Error: No such device.\n");
233
		return;
234
	}
235

236
	spin_lock_irqsave(&card->cmd_lock, flags);
237
	writel((u32) value, SAR_REG_DR0);
238
	writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD);
239
	waitfor_idle(card);
240
	spin_unlock_irqrestore(&card->cmd_lock, flags);
241
}
242

243
#ifdef HAVE_EEPROM
244
static u32 rdsrtab[] =
245
{
246
	SAR_GP_EECS | SAR_GP_EESCLK,
247
	0,
248
	SAR_GP_EESCLK,			/* 0 */
249
	0,
250
	SAR_GP_EESCLK,			/* 0 */
251
	0,
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	SAR_GP_EESCLK,			/* 0 */
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	0,
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	SAR_GP_EESCLK,			/* 0 */
255
	0,
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	SAR_GP_EESCLK,			/* 0 */
257
	SAR_GP_EEDO,
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	SAR_GP_EESCLK | SAR_GP_EEDO,	/* 1 */
259
	0,
260
	SAR_GP_EESCLK,			/* 0 */
261
	SAR_GP_EEDO,
262
	SAR_GP_EESCLK | SAR_GP_EEDO	/* 1 */
263
};
264

265
static u32 wrentab[] =
266
{
267
	SAR_GP_EECS | SAR_GP_EESCLK,
268
	0,
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	SAR_GP_EESCLK,			/* 0 */
270
	0,
271
	SAR_GP_EESCLK,			/* 0 */
272
	0,
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	SAR_GP_EESCLK,			/* 0 */
274
	0,
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	SAR_GP_EESCLK,			/* 0 */
276
	SAR_GP_EEDO,
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	SAR_GP_EESCLK | SAR_GP_EEDO,	/* 1 */
278
	SAR_GP_EEDO,
279
	SAR_GP_EESCLK | SAR_GP_EEDO,	/* 1 */
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	0,
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	SAR_GP_EESCLK,			/* 0 */
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	0,
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	SAR_GP_EESCLK			/* 0 */
284
};
285

286
static u32 rdtab[] =
287
{
288
	SAR_GP_EECS | SAR_GP_EESCLK,
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	0,
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	SAR_GP_EESCLK,			/* 0 */
291
	0,
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	SAR_GP_EESCLK,			/* 0 */
293
	0,
294
	SAR_GP_EESCLK,			/* 0 */
295
	0,
296
	SAR_GP_EESCLK,			/* 0 */
297
	0,
298
	SAR_GP_EESCLK,			/* 0 */
299
	0,
300
	SAR_GP_EESCLK,			/* 0 */
301
	SAR_GP_EEDO,
302
	SAR_GP_EESCLK | SAR_GP_EEDO,	/* 1 */
303
	SAR_GP_EEDO,
304
	SAR_GP_EESCLK | SAR_GP_EEDO	/* 1 */
305
};
306

307
static u32 wrtab[] =
308
{
309
	SAR_GP_EECS | SAR_GP_EESCLK,
310
	0,
311
	SAR_GP_EESCLK,			/* 0 */
312
	0,
313
	SAR_GP_EESCLK,			/* 0 */
314
	0,
315
	SAR_GP_EESCLK,			/* 0 */
316
	0,
317
	SAR_GP_EESCLK,			/* 0 */
318
	0,
319
	SAR_GP_EESCLK,			/* 0 */
320
	0,
321
	SAR_GP_EESCLK,			/* 0 */
322
	SAR_GP_EEDO,
323
	SAR_GP_EESCLK | SAR_GP_EEDO,	/* 1 */
324
	0,
325
	SAR_GP_EESCLK			/* 0 */
326
};
327

328
static u32 clktab[] =
329
{
330
	0,
331
	SAR_GP_EESCLK,
332
	0,
333
	SAR_GP_EESCLK,
334
	0,
335
	SAR_GP_EESCLK,
336
	0,
337
	SAR_GP_EESCLK,
338
	0,
339
	SAR_GP_EESCLK,
340
	0,
341
	SAR_GP_EESCLK,
342
	0,
343
	SAR_GP_EESCLK,
344
	0,
345
	SAR_GP_EESCLK,
346
	0
347
};
348

349
static u32
350
idt77252_read_gp(struct idt77252_dev *card)
351
{
352
	u32 gp;
353

354
	gp = readl(SAR_REG_GP);
355
#if 0
356
	printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0");
357
#endif
358
	return gp;
359
}
360

361
static void
362
idt77252_write_gp(struct idt77252_dev *card, u32 value)
363
{
364
	unsigned long flags;
365

366
#if 0
367
	printk("WR: %s %s %s\n", value & SAR_GP_EECS ? "   " : "/CS",
368
	       value & SAR_GP_EESCLK ? "HIGH" : "LOW ",
369
	       value & SAR_GP_EEDO   ? "1" : "0");
370
#endif
371

372
	spin_lock_irqsave(&card->cmd_lock, flags);
373
	waitfor_idle(card);
374
	writel(value, SAR_REG_GP);
375
	spin_unlock_irqrestore(&card->cmd_lock, flags);
376
}
377

378
static u8
379
idt77252_eeprom_read_status(struct idt77252_dev *card)
380
{
381
	u8 byte;
382
	u32 gp;
383
	int i, j;
384

385
	gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
386

387
	for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) {
388
		idt77252_write_gp(card, gp | rdsrtab[i]);
389
		udelay(5);
390
	}
391
	idt77252_write_gp(card, gp | SAR_GP_EECS);
392
	udelay(5);
393

394
	byte = 0;
395
	for (i = 0, j = 0; i < 8; i++) {
396
		byte <<= 1;
397

398
		idt77252_write_gp(card, gp | clktab[j++]);
399
		udelay(5);
400

401
		byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
402

403
		idt77252_write_gp(card, gp | clktab[j++]);
404
		udelay(5);
405
	}
406
	idt77252_write_gp(card, gp | SAR_GP_EECS);
407
	udelay(5);
408

409
	return byte;
410
}
411

412
static u8
413
idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset)
414
{
415
	u8 byte;
416
	u32 gp;
417
	int i, j;
418

419
	gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
420

421
	for (i = 0; i < ARRAY_SIZE(rdtab); i++) {
422
		idt77252_write_gp(card, gp | rdtab[i]);
423
		udelay(5);
424
	}
425
	idt77252_write_gp(card, gp | SAR_GP_EECS);
426
	udelay(5);
427

428
	for (i = 0, j = 0; i < 8; i++) {
429
		idt77252_write_gp(card, gp | clktab[j++] |
430
					(offset & 1 ? SAR_GP_EEDO : 0));
431
		udelay(5);
432

433
		idt77252_write_gp(card, gp | clktab[j++] |
434
					(offset & 1 ? SAR_GP_EEDO : 0));
435
		udelay(5);
436

437
		offset >>= 1;
438
	}
439
	idt77252_write_gp(card, gp | SAR_GP_EECS);
440
	udelay(5);
441

442
	byte = 0;
443
	for (i = 0, j = 0; i < 8; i++) {
444
		byte <<= 1;
445

446
		idt77252_write_gp(card, gp | clktab[j++]);
447
		udelay(5);
448

449
		byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
450

451
		idt77252_write_gp(card, gp | clktab[j++]);
452
		udelay(5);
453
	}
454
	idt77252_write_gp(card, gp | SAR_GP_EECS);
455
	udelay(5);
456

457
	return byte;
458
}
459

460
static void
461
idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data)
462
{
463
	u32 gp;
464
	int i, j;
465

466
	gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
467

468
	for (i = 0; i < ARRAY_SIZE(wrentab); i++) {
469
		idt77252_write_gp(card, gp | wrentab[i]);
470
		udelay(5);
471
	}
472
	idt77252_write_gp(card, gp | SAR_GP_EECS);
473
	udelay(5);
474

475
	for (i = 0; i < ARRAY_SIZE(wrtab); i++) {
476
		idt77252_write_gp(card, gp | wrtab[i]);
477
		udelay(5);
478
	}
479
	idt77252_write_gp(card, gp | SAR_GP_EECS);
480
	udelay(5);
481

482
	for (i = 0, j = 0; i < 8; i++) {
483
		idt77252_write_gp(card, gp | clktab[j++] |
484
					(offset & 1 ? SAR_GP_EEDO : 0));
485
		udelay(5);
486

487
		idt77252_write_gp(card, gp | clktab[j++] |
488
					(offset & 1 ? SAR_GP_EEDO : 0));
489
		udelay(5);
490

491
		offset >>= 1;
492
	}
493
	idt77252_write_gp(card, gp | SAR_GP_EECS);
494
	udelay(5);
495

496
	for (i = 0, j = 0; i < 8; i++) {
497
		idt77252_write_gp(card, gp | clktab[j++] |
498
					(data & 1 ? SAR_GP_EEDO : 0));
499
		udelay(5);
500

501
		idt77252_write_gp(card, gp | clktab[j++] |
502
					(data & 1 ? SAR_GP_EEDO : 0));
503
		udelay(5);
504

505
		data >>= 1;
506
	}
507
	idt77252_write_gp(card, gp | SAR_GP_EECS);
508
	udelay(5);
509
}
510

511
static void
512
idt77252_eeprom_init(struct idt77252_dev *card)
513
{
514
	u32 gp;
515

516
	gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
517

518
	idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
519
	udelay(5);
520
	idt77252_write_gp(card, gp | SAR_GP_EECS);
521
	udelay(5);
522
	idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
523
	udelay(5);
524
	idt77252_write_gp(card, gp | SAR_GP_EECS);
525
	udelay(5);
526
}
527
#endif /* HAVE_EEPROM */
528

529

530
#ifdef CONFIG_ATM_IDT77252_DEBUG
531
static void
532
dump_tct(struct idt77252_dev *card, int index)
533
{
534
	unsigned long tct;
535
	int i;
536

537
	tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE);
538

539
	printk("%s: TCT %x:", card->name, index);
540
	for (i = 0; i < 8; i++) {
541
		printk(" %08x", read_sram(card, tct + i));
542
	}
543
	printk("\n");
544
}
545

546
static void
547
idt77252_tx_dump(struct idt77252_dev *card)
548
{
549
	struct atm_vcc *vcc;
550
	struct vc_map *vc;
551
	int i;
552

553
	printk("%s\n", __func__);
554
	for (i = 0; i < card->tct_size; i++) {
555
		vc = card->vcs[i];
556
		if (!vc)
557
			continue;
558

559
		vcc = NULL;
560
		if (vc->rx_vcc)
561
			vcc = vc->rx_vcc;
562
		else if (vc->tx_vcc)
563
			vcc = vc->tx_vcc;
564

565
		if (!vcc)
566
			continue;
567

568
		printk("%s: Connection %d:\n", card->name, vc->index);
569
		dump_tct(card, vc->index);
570
	}
571
}
572
#endif
573

574

575
/*****************************************************************************/
576
/*                                                                           */
577
/* SCQ Handling                                                              */
578
/*                                                                           */
579
/*****************************************************************************/
580

581
static int
582
sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue)
583
{
584
	struct sb_pool *pool = &card->sbpool[queue];
585
	int index;
586

587
	index = pool->index;
588
	while (pool->skb[index]) {
589
		index = (index + 1) & FBQ_MASK;
590
		if (index == pool->index)
591
			return -ENOBUFS;
592
	}
593

594
	pool->skb[index] = skb;
595
	IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index);
596

597
	pool->index = (index + 1) & FBQ_MASK;
598
	return 0;
599
}
600

601
static void
602
sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb)
603
{
604
	unsigned int queue, index;
605
	u32 handle;
606

607
	handle = IDT77252_PRV_POOL(skb);
608

609
	queue = POOL_QUEUE(handle);
610
	if (queue > 3)
611
		return;
612

613
	index = POOL_INDEX(handle);
614
	if (index > FBQ_SIZE - 1)
615
		return;
616

617
	card->sbpool[queue].skb[index] = NULL;
618
}
619

620
static struct sk_buff *
621
sb_pool_skb(struct idt77252_dev *card, u32 handle)
622
{
623
	unsigned int queue, index;
624

625
	queue = POOL_QUEUE(handle);
626
	if (queue > 3)
627
		return NULL;
628

629
	index = POOL_INDEX(handle);
630
	if (index > FBQ_SIZE - 1)
631
		return NULL;
632

633
	return card->sbpool[queue].skb[index];
634
}
635

636
static struct scq_info *
637
alloc_scq(struct idt77252_dev *card, int class)
638
{
639
	struct scq_info *scq;
640

641
	scq = kzalloc(sizeof(struct scq_info), GFP_KERNEL);
642
	if (!scq)
643
		return NULL;
644
	scq->base = dma_alloc_coherent(&card->pcidev->dev, SCQ_SIZE,
645
				       &scq->paddr, GFP_KERNEL);
646
	if (scq->base == NULL) {
647
		kfree(scq);
648
		return NULL;
649
	}
650

651
	scq->next = scq->base;
652
	scq->last = scq->base + (SCQ_ENTRIES - 1);
653
	atomic_set(&scq->used, 0);
654

655
	spin_lock_init(&scq->lock);
656
	spin_lock_init(&scq->skblock);
657

658
	skb_queue_head_init(&scq->transmit);
659
	skb_queue_head_init(&scq->pending);
660

661
	TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n",
662
		 scq->base, scq->next, scq->last, (unsigned long long)scq->paddr);
663

664
	return scq;
665
}
666

667
static void
668
free_scq(struct idt77252_dev *card, struct scq_info *scq)
669
{
670
	struct sk_buff *skb;
671
	struct atm_vcc *vcc;
672

673
	dma_free_coherent(&card->pcidev->dev, SCQ_SIZE,
674
			  scq->base, scq->paddr);
675

676
	while ((skb = skb_dequeue(&scq->transmit))) {
677
		dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
678
				 skb->len, DMA_TO_DEVICE);
679

680
		vcc = ATM_SKB(skb)->vcc;
681
		if (vcc->pop)
682
			vcc->pop(vcc, skb);
683
		else
684
			dev_kfree_skb(skb);
685
	}
686

687
	while ((skb = skb_dequeue(&scq->pending))) {
688
		dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
689
				 skb->len, DMA_TO_DEVICE);
690

691
		vcc = ATM_SKB(skb)->vcc;
692
		if (vcc->pop)
693
			vcc->pop(vcc, skb);
694
		else
695
			dev_kfree_skb(skb);
696
	}
697

698
	kfree(scq);
699
}
700

701

702
static int
703
push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb)
704
{
705
	struct scq_info *scq = vc->scq;
706
	unsigned long flags;
707
	struct scqe *tbd;
708
	int entries;
709

710
	TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next);
711

712
	atomic_inc(&scq->used);
713
	entries = atomic_read(&scq->used);
714
	if (entries > (SCQ_ENTRIES - 1)) {
715
		atomic_dec(&scq->used);
716
		goto out;
717
	}
718

719
	skb_queue_tail(&scq->transmit, skb);
720

721
	spin_lock_irqsave(&vc->lock, flags);
722
	if (vc->estimator) {
723
		struct atm_vcc *vcc = vc->tx_vcc;
724
		struct sock *sk = sk_atm(vcc);
725

726
		vc->estimator->cells += (skb->len + 47) / 48;
727
		if (refcount_read(&sk->sk_wmem_alloc) >
728
		    (sk->sk_sndbuf >> 1)) {
729
			u32 cps = vc->estimator->maxcps;
730

731
			vc->estimator->cps = cps;
732
			vc->estimator->avcps = cps << 5;
733
			if (vc->lacr < vc->init_er) {
734
				vc->lacr = vc->init_er;
735
				writel(TCMDQ_LACR | (vc->lacr << 16) |
736
				       vc->index, SAR_REG_TCMDQ);
737
			}
738
		}
739
	}
740
	spin_unlock_irqrestore(&vc->lock, flags);
741

742
	tbd = &IDT77252_PRV_TBD(skb);
743

744
	spin_lock_irqsave(&scq->lock, flags);
745
	scq->next->word_1 = cpu_to_le32(tbd->word_1 |
746
					SAR_TBD_TSIF | SAR_TBD_GTSI);
747
	scq->next->word_2 = cpu_to_le32(tbd->word_2);
748
	scq->next->word_3 = cpu_to_le32(tbd->word_3);
749
	scq->next->word_4 = cpu_to_le32(tbd->word_4);
750

751
	if (scq->next == scq->last)
752
		scq->next = scq->base;
753
	else
754
		scq->next++;
755

756
	write_sram(card, scq->scd,
757
		   scq->paddr +
758
		   (u32)((unsigned long)scq->next - (unsigned long)scq->base));
759
	spin_unlock_irqrestore(&scq->lock, flags);
760

761
	scq->trans_start = jiffies;
762

763
	if (test_and_clear_bit(VCF_IDLE, &vc->flags)) {
764
		writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index,
765
		       SAR_REG_TCMDQ);
766
	}
767

768
	TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used));
769

770
	XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n",
771
		card->name, atomic_read(&scq->used),
772
		read_sram(card, scq->scd + 1), scq->next);
773

774
	return 0;
775

776
out:
777
	if (time_after(jiffies, scq->trans_start + HZ)) {
778
		printk("%s: Error pushing TBD for %d.%d\n",
779
		       card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci);
780
#ifdef CONFIG_ATM_IDT77252_DEBUG
781
		idt77252_tx_dump(card);
782
#endif
783
		scq->trans_start = jiffies;
784
	}
785

786
	return -ENOBUFS;
787
}
788

789

790
static void
791
drain_scq(struct idt77252_dev *card, struct vc_map *vc)
792
{
793
	struct scq_info *scq = vc->scq;
794
	struct sk_buff *skb;
795
	struct atm_vcc *vcc;
796

797
	TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n",
798
		 card->name, atomic_read(&scq->used), scq->next);
799

800
	skb = skb_dequeue(&scq->transmit);
801
	if (skb) {
802
		TXPRINTK("%s: freeing skb at %p.\n", card->name, skb);
803

804
		dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
805
				 skb->len, DMA_TO_DEVICE);
806

807
		vcc = ATM_SKB(skb)->vcc;
808

809
		if (vcc->pop)
810
			vcc->pop(vcc, skb);
811
		else
812
			dev_kfree_skb(skb);
813

814
		atomic_inc(&vcc->stats->tx);
815
	}
816

817
	atomic_dec(&scq->used);
818

819
	spin_lock(&scq->skblock);
820
	while ((skb = skb_dequeue(&scq->pending))) {
821
		if (push_on_scq(card, vc, skb)) {
822
			skb_queue_head(&vc->scq->pending, skb);
823
			break;
824
		}
825
	}
826
	spin_unlock(&scq->skblock);
827
}
828

829
static int
830
queue_skb(struct idt77252_dev *card, struct vc_map *vc,
831
	  struct sk_buff *skb, int oam)
832
{
833
	struct atm_vcc *vcc;
834
	struct scqe *tbd;
835
	unsigned long flags;
836
	int error;
837
	int aal;
838
	u32 word4;
839

840
	if (skb->len == 0) {
841
		printk("%s: invalid skb->len (%d)\n", card->name, skb->len);
842
		return -EINVAL;
843
	}
844

845
	TXPRINTK("%s: Sending %d bytes of data.\n",
846
		 card->name, skb->len);
847

848
	tbd = &IDT77252_PRV_TBD(skb);
849
	vcc = ATM_SKB(skb)->vcc;
850
	word4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
851
			(skb->data[2] <<  8) | (skb->data[3] <<  0);
852

853
	IDT77252_PRV_PADDR(skb) = dma_map_single(&card->pcidev->dev, skb->data,
854
						 skb->len, DMA_TO_DEVICE);
855
	if (dma_mapping_error(&card->pcidev->dev, IDT77252_PRV_PADDR(skb)))
856
		return -ENOMEM;
857

858
	error = -EINVAL;
859

860
	if (oam) {
861
		if (skb->len != 52)
862
			goto errout;
863

864
		tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU;
865
		tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
866
		tbd->word_3 = 0x00000000;
867
		tbd->word_4 = word4;
868

869
		if (test_bit(VCF_RSV, &vc->flags))
870
			vc = card->vcs[0];
871

872
		goto done;
873
	}
874

875
	if (test_bit(VCF_RSV, &vc->flags)) {
876
		printk("%s: Trying to transmit on reserved VC\n", card->name);
877
		goto errout;
878
	}
879

880
	aal = vcc->qos.aal;
881

882
	switch (aal) {
883
	case ATM_AAL0:
884
	case ATM_AAL34:
885
		if (skb->len > 52)
886
			goto errout;
887

888
		if (aal == ATM_AAL0)
889
			tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 |
890
				      ATM_CELL_PAYLOAD;
891
		else
892
			tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 |
893
				      ATM_CELL_PAYLOAD;
894

895
		tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
896
		tbd->word_3 = 0x00000000;
897
		tbd->word_4 = word4;
898
		break;
899

900
	case ATM_AAL5:
901
		tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len;
902
		tbd->word_2 = IDT77252_PRV_PADDR(skb);
903
		tbd->word_3 = skb->len;
904
		tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) |
905
			      (vcc->vci << SAR_TBD_VCI_SHIFT);
906
		break;
907

908
	case ATM_AAL1:
909
	case ATM_AAL2:
910
	default:
911
		printk("%s: Traffic type not supported.\n", card->name);
912
		error = -EPROTONOSUPPORT;
913
		goto errout;
914
	}
915

916
done:
917
	spin_lock_irqsave(&vc->scq->skblock, flags);
918
	skb_queue_tail(&vc->scq->pending, skb);
919

920
	while ((skb = skb_dequeue(&vc->scq->pending))) {
921
		if (push_on_scq(card, vc, skb)) {
922
			skb_queue_head(&vc->scq->pending, skb);
923
			break;
924
		}
925
	}
926
	spin_unlock_irqrestore(&vc->scq->skblock, flags);
927

928
	return 0;
929

930
errout:
931
	dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
932
			 skb->len, DMA_TO_DEVICE);
933
	return error;
934
}
935

936
static unsigned long
937
get_free_scd(struct idt77252_dev *card, struct vc_map *vc)
938
{
939
	int i;
940

941
	for (i = 0; i < card->scd_size; i++) {
942
		if (!card->scd2vc[i]) {
943
			card->scd2vc[i] = vc;
944
			vc->scd_index = i;
945
			return card->scd_base + i * SAR_SRAM_SCD_SIZE;
946
		}
947
	}
948
	return 0;
949
}
950

951
static void
952
fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
953
{
954
	write_sram(card, scq->scd, scq->paddr);
955
	write_sram(card, scq->scd + 1, 0x00000000);
956
	write_sram(card, scq->scd + 2, 0xffffffff);
957
	write_sram(card, scq->scd + 3, 0x00000000);
958
}
959

960
static void
961
clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
962
{
963
	return;
964
}
965

966
/*****************************************************************************/
967
/*                                                                           */
968
/* RSQ Handling                                                              */
969
/*                                                                           */
970
/*****************************************************************************/
971

972
static int
973
init_rsq(struct idt77252_dev *card)
974
{
975
	struct rsq_entry *rsqe;
976

977
	card->rsq.base = dma_alloc_coherent(&card->pcidev->dev, RSQSIZE,
978
					    &card->rsq.paddr, GFP_KERNEL);
979
	if (card->rsq.base == NULL) {
980
		printk("%s: can't allocate RSQ.\n", card->name);
981
		return -1;
982
	}
983

984
	card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1;
985
	card->rsq.next = card->rsq.last;
986
	for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++)
987
		rsqe->word_4 = 0;
988

989
	writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base,
990
	       SAR_REG_RSQH);
991
	writel(card->rsq.paddr, SAR_REG_RSQB);
992

993
	IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name,
994
		(unsigned long) card->rsq.base,
995
		readl(SAR_REG_RSQB));
996
	IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n",
997
		card->name,
998
		readl(SAR_REG_RSQH),
999
		readl(SAR_REG_RSQB),
1000
		readl(SAR_REG_RSQT));
1001

1002
	return 0;
1003
}
1004

1005
static void
1006
deinit_rsq(struct idt77252_dev *card)
1007
{
1008
	dma_free_coherent(&card->pcidev->dev, RSQSIZE,
1009
			  card->rsq.base, card->rsq.paddr);
1010
}
1011

1012
static void
1013
dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe)
1014
{
1015
	struct atm_vcc *vcc;
1016
	struct sk_buff *skb;
1017
	struct rx_pool *rpp;
1018
	struct vc_map *vc;
1019
	u32 header, vpi, vci;
1020
	u32 stat;
1021
	int i;
1022

1023
	stat = le32_to_cpu(rsqe->word_4);
1024

1025
	if (stat & SAR_RSQE_IDLE) {
1026
		RXPRINTK("%s: message about inactive connection.\n",
1027
			 card->name);
1028
		return;
1029
	}
1030

1031
	skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2));
1032
	if (skb == NULL) {
1033
		printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n",
1034
		       card->name, __func__,
1035
		       le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2),
1036
		       le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4));
1037
		return;
1038
	}
1039

1040
	header = le32_to_cpu(rsqe->word_1);
1041
	vpi = (header >> 16) & 0x00ff;
1042
	vci = (header >>  0) & 0xffff;
1043

1044
	RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n",
1045
		 card->name, vpi, vci, skb, skb->data);
1046

1047
	if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) {
1048
		printk("%s: SDU received for out-of-range vc %u.%u\n",
1049
		       card->name, vpi, vci);
1050
		recycle_rx_skb(card, skb);
1051
		return;
1052
	}
1053

1054
	vc = card->vcs[VPCI2VC(card, vpi, vci)];
1055
	if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1056
		printk("%s: SDU received on non RX vc %u.%u\n",
1057
		       card->name, vpi, vci);
1058
		recycle_rx_skb(card, skb);
1059
		return;
1060
	}
1061

1062
	vcc = vc->rx_vcc;
1063

1064
	dma_sync_single_for_cpu(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
1065
				skb_end_pointer(skb) - skb->data,
1066
				DMA_FROM_DEVICE);
1067

1068
	if ((vcc->qos.aal == ATM_AAL0) ||
1069
	    (vcc->qos.aal == ATM_AAL34)) {
1070
		struct sk_buff *sb;
1071
		unsigned char *cell;
1072
		u32 aal0;
1073

1074
		cell = skb->data;
1075
		for (i = (stat & SAR_RSQE_CELLCNT); i; i--) {
1076
			if ((sb = dev_alloc_skb(64)) == NULL) {
1077
				printk("%s: Can't allocate buffers for aal0.\n",
1078
				       card->name);
1079
				atomic_add(i, &vcc->stats->rx_drop);
1080
				break;
1081
			}
1082
			if (!atm_charge(vcc, sb->truesize)) {
1083
				RXPRINTK("%s: atm_charge() dropped aal0 packets.\n",
1084
					 card->name);
1085
				atomic_add(i - 1, &vcc->stats->rx_drop);
1086
				dev_kfree_skb(sb);
1087
				break;
1088
			}
1089
			aal0 = (vpi << ATM_HDR_VPI_SHIFT) |
1090
			       (vci << ATM_HDR_VCI_SHIFT);
1091
			aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0;
1092
			aal0 |= (stat & SAR_RSQE_CLP)  ? 0x00000001 : 0;
1093

1094
			*((u32 *) sb->data) = aal0;
1095
			skb_put(sb, sizeof(u32));
1096
			skb_put_data(sb, cell, ATM_CELL_PAYLOAD);
1097

1098
			ATM_SKB(sb)->vcc = vcc;
1099
			__net_timestamp(sb);
1100
			vcc->push(vcc, sb);
1101
			atomic_inc(&vcc->stats->rx);
1102

1103
			cell += ATM_CELL_PAYLOAD;
1104
		}
1105

1106
		recycle_rx_skb(card, skb);
1107
		return;
1108
	}
1109
	if (vcc->qos.aal != ATM_AAL5) {
1110
		printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n",
1111
		       card->name, vcc->qos.aal);
1112
		recycle_rx_skb(card, skb);
1113
		return;
1114
	}
1115
	skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD;
1116

1117
	rpp = &vc->rcv.rx_pool;
1118

1119
	__skb_queue_tail(&rpp->queue, skb);
1120
	rpp->len += skb->len;
1121

1122
	if (stat & SAR_RSQE_EPDU) {
1123
		unsigned int len, truesize;
1124
		unsigned char *l1l2;
1125

1126
		l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6);
1127

1128
		len = (l1l2[0] << 8) | l1l2[1];
1129
		len = len ? len : 0x10000;
1130

1131
		RXPRINTK("%s: PDU has %d bytes.\n", card->name, len);
1132

1133
		if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) {
1134
			RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. "
1135
			         "(CDC: %08x)\n",
1136
			         card->name, len, rpp->len, readl(SAR_REG_CDC));
1137
			recycle_rx_pool_skb(card, rpp);
1138
			atomic_inc(&vcc->stats->rx_err);
1139
			return;
1140
		}
1141
		if (stat & SAR_RSQE_CRC) {
1142
			RXPRINTK("%s: AAL5 CRC error.\n", card->name);
1143
			recycle_rx_pool_skb(card, rpp);
1144
			atomic_inc(&vcc->stats->rx_err);
1145
			return;
1146
		}
1147
		if (skb_queue_len(&rpp->queue) > 1) {
1148
			struct sk_buff *sb;
1149

1150
			skb = dev_alloc_skb(rpp->len);
1151
			if (!skb) {
1152
				RXPRINTK("%s: Can't alloc RX skb.\n",
1153
					 card->name);
1154
				recycle_rx_pool_skb(card, rpp);
1155
				atomic_inc(&vcc->stats->rx_err);
1156
				return;
1157
			}
1158
			if (!atm_charge(vcc, skb->truesize)) {
1159
				recycle_rx_pool_skb(card, rpp);
1160
				dev_kfree_skb(skb);
1161
				return;
1162
			}
1163
			skb_queue_walk(&rpp->queue, sb)
1164
				skb_put_data(skb, sb->data, sb->len);
1165

1166
			recycle_rx_pool_skb(card, rpp);
1167

1168
			skb_trim(skb, len);
1169
			ATM_SKB(skb)->vcc = vcc;
1170
			__net_timestamp(skb);
1171

1172
			vcc->push(vcc, skb);
1173
			atomic_inc(&vcc->stats->rx);
1174

1175
			return;
1176
		}
1177

1178
		flush_rx_pool(card, rpp);
1179

1180
		if (!atm_charge(vcc, skb->truesize)) {
1181
			recycle_rx_skb(card, skb);
1182
			return;
1183
		}
1184

1185
		dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
1186
				 skb_end_pointer(skb) - skb->data,
1187
				 DMA_FROM_DEVICE);
1188
		sb_pool_remove(card, skb);
1189

1190
		skb_trim(skb, len);
1191
		ATM_SKB(skb)->vcc = vcc;
1192
		__net_timestamp(skb);
1193

1194
		truesize = skb->truesize;
1195
		vcc->push(vcc, skb);
1196
		atomic_inc(&vcc->stats->rx);
1197

1198
		if (truesize > SAR_FB_SIZE_3)
1199
			add_rx_skb(card, 3, SAR_FB_SIZE_3, 1);
1200
		else if (truesize > SAR_FB_SIZE_2)
1201
			add_rx_skb(card, 2, SAR_FB_SIZE_2, 1);
1202
		else if (truesize > SAR_FB_SIZE_1)
1203
			add_rx_skb(card, 1, SAR_FB_SIZE_1, 1);
1204
		else
1205
			add_rx_skb(card, 0, SAR_FB_SIZE_0, 1);
1206
		return;
1207
	}
1208
}
1209

1210
static void
1211
idt77252_rx(struct idt77252_dev *card)
1212
{
1213
	struct rsq_entry *rsqe;
1214

1215
	if (card->rsq.next == card->rsq.last)
1216
		rsqe = card->rsq.base;
1217
	else
1218
		rsqe = card->rsq.next + 1;
1219

1220
	if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) {
1221
		RXPRINTK("%s: no entry in RSQ.\n", card->name);
1222
		return;
1223
	}
1224

1225
	do {
1226
		dequeue_rx(card, rsqe);
1227
		rsqe->word_4 = 0;
1228
		card->rsq.next = rsqe;
1229
		if (card->rsq.next == card->rsq.last)
1230
			rsqe = card->rsq.base;
1231
		else
1232
			rsqe = card->rsq.next + 1;
1233
	} while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID);
1234

1235
	writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base,
1236
	       SAR_REG_RSQH);
1237
}
1238

1239
static void
1240
idt77252_rx_raw(struct idt77252_dev *card)
1241
{
1242
	struct sk_buff	*queue;
1243
	u32		head, tail;
1244
	struct atm_vcc	*vcc;
1245
	struct vc_map	*vc;
1246
	struct sk_buff	*sb;
1247

1248
	if (card->raw_cell_head == NULL) {
1249
		u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1));
1250
		card->raw_cell_head = sb_pool_skb(card, handle);
1251
	}
1252

1253
	queue = card->raw_cell_head;
1254
	if (!queue)
1255
		return;
1256

1257
	head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16);
1258
	tail = readl(SAR_REG_RAWCT);
1259

1260
	dma_sync_single_for_cpu(&card->pcidev->dev, IDT77252_PRV_PADDR(queue),
1261
				skb_end_offset(queue) - 16,
1262
				DMA_FROM_DEVICE);
1263

1264
	while (head != tail) {
1265
		unsigned int vpi, vci;
1266
		u32 header;
1267

1268
		header = le32_to_cpu(*(u32 *) &queue->data[0]);
1269

1270
		vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT;
1271
		vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT;
1272

1273
#ifdef CONFIG_ATM_IDT77252_DEBUG
1274
		if (debug & DBG_RAW_CELL) {
1275
			int i;
1276

1277
			printk("%s: raw cell %x.%02x.%04x.%x.%x\n",
1278
			       card->name, (header >> 28) & 0x000f,
1279
			       (header >> 20) & 0x00ff,
1280
			       (header >>  4) & 0xffff,
1281
			       (header >>  1) & 0x0007,
1282
			       (header >>  0) & 0x0001);
1283
			for (i = 16; i < 64; i++)
1284
				printk(" %02x", queue->data[i]);
1285
			printk("\n");
1286
		}
1287
#endif
1288

1289
		if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) {
1290
			RPRINTK("%s: SDU received for out-of-range vc %u.%u\n",
1291
				card->name, vpi, vci);
1292
			goto drop;
1293
		}
1294

1295
		vc = card->vcs[VPCI2VC(card, vpi, vci)];
1296
		if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1297
			RPRINTK("%s: SDU received on non RX vc %u.%u\n",
1298
				card->name, vpi, vci);
1299
			goto drop;
1300
		}
1301

1302
		vcc = vc->rx_vcc;
1303

1304
		if (vcc->qos.aal != ATM_AAL0) {
1305
			RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n",
1306
				card->name, vpi, vci);
1307
			atomic_inc(&vcc->stats->rx_drop);
1308
			goto drop;
1309
		}
1310
	
1311
		if ((sb = dev_alloc_skb(64)) == NULL) {
1312
			printk("%s: Can't allocate buffers for AAL0.\n",
1313
			       card->name);
1314
			atomic_inc(&vcc->stats->rx_err);
1315
			goto drop;
1316
		}
1317

1318
		if (!atm_charge(vcc, sb->truesize)) {
1319
			RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n",
1320
				 card->name);
1321
			dev_kfree_skb(sb);
1322
			goto drop;
1323
		}
1324

1325
		*((u32 *) sb->data) = header;
1326
		skb_put(sb, sizeof(u32));
1327
		skb_put_data(sb, &(queue->data[16]), ATM_CELL_PAYLOAD);
1328

1329
		ATM_SKB(sb)->vcc = vcc;
1330
		__net_timestamp(sb);
1331
		vcc->push(vcc, sb);
1332
		atomic_inc(&vcc->stats->rx);
1333

1334
drop:
1335
		skb_pull(queue, 64);
1336

1337
		head = IDT77252_PRV_PADDR(queue)
1338
					+ (queue->data - queue->head - 16);
1339

1340
		if (queue->len < 128) {
1341
			struct sk_buff *next;
1342
			u32 handle;
1343

1344
			head = le32_to_cpu(*(u32 *) &queue->data[0]);
1345
			handle = le32_to_cpu(*(u32 *) &queue->data[4]);
1346

1347
			next = sb_pool_skb(card, handle);
1348
			recycle_rx_skb(card, queue);
1349

1350
			if (next) {
1351
				card->raw_cell_head = next;
1352
				queue = card->raw_cell_head;
1353
				dma_sync_single_for_cpu(&card->pcidev->dev,
1354
							IDT77252_PRV_PADDR(queue),
1355
							(skb_end_pointer(queue) -
1356
							 queue->data),
1357
							DMA_FROM_DEVICE);
1358
			} else {
1359
				card->raw_cell_head = NULL;
1360
				printk("%s: raw cell queue overrun\n",
1361
				       card->name);
1362
				break;
1363
			}
1364
		}
1365
	}
1366
}
1367

1368

1369
/*****************************************************************************/
1370
/*                                                                           */
1371
/* TSQ Handling                                                              */
1372
/*                                                                           */
1373
/*****************************************************************************/
1374

1375
static int
1376
init_tsq(struct idt77252_dev *card)
1377
{
1378
	struct tsq_entry *tsqe;
1379

1380
	card->tsq.base = dma_alloc_coherent(&card->pcidev->dev, RSQSIZE,
1381
					    &card->tsq.paddr, GFP_KERNEL);
1382
	if (card->tsq.base == NULL) {
1383
		printk("%s: can't allocate TSQ.\n", card->name);
1384
		return -1;
1385
	}
1386

1387
	card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1;
1388
	card->tsq.next = card->tsq.last;
1389
	for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++)
1390
		tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1391

1392
	writel(card->tsq.paddr, SAR_REG_TSQB);
1393
	writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base,
1394
	       SAR_REG_TSQH);
1395

1396
	return 0;
1397
}
1398

1399
static void
1400
deinit_tsq(struct idt77252_dev *card)
1401
{
1402
	dma_free_coherent(&card->pcidev->dev, TSQSIZE,
1403
			  card->tsq.base, card->tsq.paddr);
1404
}
1405

1406
static void
1407
idt77252_tx(struct idt77252_dev *card)
1408
{
1409
	struct tsq_entry *tsqe;
1410
	unsigned int vpi, vci;
1411
	struct vc_map *vc;
1412
	u32 conn, stat;
1413

1414
	if (card->tsq.next == card->tsq.last)
1415
		tsqe = card->tsq.base;
1416
	else
1417
		tsqe = card->tsq.next + 1;
1418

1419
	TXPRINTK("idt77252_tx: tsq  %p: base %p, next %p, last %p\n", tsqe,
1420
		 card->tsq.base, card->tsq.next, card->tsq.last);
1421
	TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n",
1422
		 readl(SAR_REG_TSQB),
1423
		 readl(SAR_REG_TSQT),
1424
		 readl(SAR_REG_TSQH));
1425

1426
	stat = le32_to_cpu(tsqe->word_2);
1427

1428
	if (stat & SAR_TSQE_INVALID)
1429
		return;
1430

1431
	do {
1432
		TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe,
1433
			 le32_to_cpu(tsqe->word_1),
1434
			 le32_to_cpu(tsqe->word_2));
1435

1436
		switch (stat & SAR_TSQE_TYPE) {
1437
		case SAR_TSQE_TYPE_TIMER:
1438
			TXPRINTK("%s: Timer RollOver detected.\n", card->name);
1439
			break;
1440

1441
		case SAR_TSQE_TYPE_IDLE:
1442

1443
			conn = le32_to_cpu(tsqe->word_1);
1444

1445
			if (SAR_TSQE_TAG(stat) == 0x10) {
1446
#ifdef	NOTDEF
1447
				printk("%s: Connection %d halted.\n",
1448
				       card->name,
1449
				       le32_to_cpu(tsqe->word_1) & 0x1fff);
1450
#endif
1451
				break;
1452
			}
1453

1454
			vc = card->vcs[conn & 0x1fff];
1455
			if (!vc) {
1456
				printk("%s: could not find VC from conn %d\n",
1457
				       card->name, conn & 0x1fff);
1458
				break;
1459
			}
1460

1461
			printk("%s: Connection %d IDLE.\n",
1462
			       card->name, vc->index);
1463

1464
			set_bit(VCF_IDLE, &vc->flags);
1465
			break;
1466

1467
		case SAR_TSQE_TYPE_TSR:
1468

1469
			conn = le32_to_cpu(tsqe->word_1);
1470

1471
			vc = card->vcs[conn & 0x1fff];
1472
			if (!vc) {
1473
				printk("%s: no VC at index %d\n",
1474
				       card->name,
1475
				       le32_to_cpu(tsqe->word_1) & 0x1fff);
1476
				break;
1477
			}
1478

1479
			drain_scq(card, vc);
1480
			break;
1481

1482
		case SAR_TSQE_TYPE_TBD_COMP:
1483

1484
			conn = le32_to_cpu(tsqe->word_1);
1485

1486
			vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff;
1487
			vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff;
1488

1489
			if (vpi >= (1 << card->vpibits) ||
1490
			    vci >= (1 << card->vcibits)) {
1491
				printk("%s: TBD complete: "
1492
				       "out of range VPI.VCI %u.%u\n",
1493
				       card->name, vpi, vci);
1494
				break;
1495
			}
1496

1497
			vc = card->vcs[VPCI2VC(card, vpi, vci)];
1498
			if (!vc) {
1499
				printk("%s: TBD complete: "
1500
				       "no VC at VPI.VCI %u.%u\n",
1501
				       card->name, vpi, vci);
1502
				break;
1503
			}
1504

1505
			drain_scq(card, vc);
1506
			break;
1507
		}
1508

1509
		tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1510

1511
		card->tsq.next = tsqe;
1512
		if (card->tsq.next == card->tsq.last)
1513
			tsqe = card->tsq.base;
1514
		else
1515
			tsqe = card->tsq.next + 1;
1516

1517
		TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe,
1518
			 card->tsq.base, card->tsq.next, card->tsq.last);
1519

1520
		stat = le32_to_cpu(tsqe->word_2);
1521

1522
	} while (!(stat & SAR_TSQE_INVALID));
1523

1524
	writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base,
1525
	       SAR_REG_TSQH);
1526

1527
	XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n",
1528
		card->index, readl(SAR_REG_TSQH),
1529
		readl(SAR_REG_TSQT), card->tsq.next);
1530
}
1531

1532

1533
static void
1534
tst_timer(struct timer_list *t)
1535
{
1536
	struct idt77252_dev *card = timer_container_of(card, t, tst_timer);
1537
	unsigned long base, idle, jump;
1538
	unsigned long flags;
1539
	u32 pc;
1540
	int e;
1541

1542
	spin_lock_irqsave(&card->tst_lock, flags);
1543

1544
	base = card->tst[card->tst_index];
1545
	idle = card->tst[card->tst_index ^ 1];
1546

1547
	if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) {
1548
		jump = base + card->tst_size - 2;
1549

1550
		pc = readl(SAR_REG_NOW) >> 2;
1551
		if ((pc ^ idle) & ~(card->tst_size - 1)) {
1552
			mod_timer(&card->tst_timer, jiffies + 1);
1553
			goto out;
1554
		}
1555

1556
		clear_bit(TST_SWITCH_WAIT, &card->tst_state);
1557

1558
		card->tst_index ^= 1;
1559
		write_sram(card, jump, TSTE_OPC_JMP | (base << 2));
1560

1561
		base = card->tst[card->tst_index];
1562
		idle = card->tst[card->tst_index ^ 1];
1563

1564
		for (e = 0; e < card->tst_size - 2; e++) {
1565
			if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) {
1566
				write_sram(card, idle + e,
1567
					   card->soft_tst[e].tste & TSTE_MASK);
1568
				card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE);
1569
			}
1570
		}
1571
	}
1572

1573
	if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) {
1574

1575
		for (e = 0; e < card->tst_size - 2; e++) {
1576
			if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) {
1577
				write_sram(card, idle + e,
1578
					   card->soft_tst[e].tste & TSTE_MASK);
1579
				card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE);
1580
				card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1581
			}
1582
		}
1583

1584
		jump = base + card->tst_size - 2;
1585

1586
		write_sram(card, jump, TSTE_OPC_NULL);
1587
		set_bit(TST_SWITCH_WAIT, &card->tst_state);
1588

1589
		mod_timer(&card->tst_timer, jiffies + 1);
1590
	}
1591

1592
out:
1593
	spin_unlock_irqrestore(&card->tst_lock, flags);
1594
}
1595

1596
static int
1597
__fill_tst(struct idt77252_dev *card, struct vc_map *vc,
1598
	   int n, unsigned int opc)
1599
{
1600
	unsigned long cl, avail;
1601
	unsigned long idle;
1602
	int e, r;
1603
	u32 data;
1604

1605
	avail = card->tst_size - 2;
1606
	for (e = 0; e < avail; e++) {
1607
		if (card->soft_tst[e].vc == NULL)
1608
			break;
1609
	}
1610
	if (e >= avail) {
1611
		printk("%s: No free TST entries found\n", card->name);
1612
		return -1;
1613
	}
1614

1615
	NPRINTK("%s: conn %d: first TST entry at %d.\n",
1616
		card->name, vc ? vc->index : -1, e);
1617

1618
	r = n;
1619
	cl = avail;
1620
	data = opc & TSTE_OPC_MASK;
1621
	if (vc && (opc != TSTE_OPC_NULL))
1622
		data = opc | vc->index;
1623

1624
	idle = card->tst[card->tst_index ^ 1];
1625

1626
	/*
1627
	 * Fill Soft TST.
1628
	 */
1629
	while (r > 0) {
1630
		if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) {
1631
			if (vc)
1632
				card->soft_tst[e].vc = vc;
1633
			else
1634
				card->soft_tst[e].vc = (void *)-1;
1635

1636
			card->soft_tst[e].tste = data;
1637
			if (timer_pending(&card->tst_timer))
1638
				card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1639
			else {
1640
				write_sram(card, idle + e, data);
1641
				card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1642
			}
1643

1644
			cl -= card->tst_size;
1645
			r--;
1646
		}
1647

1648
		if (++e == avail)
1649
			e = 0;
1650
		cl += n;
1651
	}
1652

1653
	return 0;
1654
}
1655

1656
static int
1657
fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc)
1658
{
1659
	unsigned long flags;
1660
	int res;
1661

1662
	spin_lock_irqsave(&card->tst_lock, flags);
1663

1664
	res = __fill_tst(card, vc, n, opc);
1665

1666
	set_bit(TST_SWITCH_PENDING, &card->tst_state);
1667
	if (!timer_pending(&card->tst_timer))
1668
		mod_timer(&card->tst_timer, jiffies + 1);
1669

1670
	spin_unlock_irqrestore(&card->tst_lock, flags);
1671
	return res;
1672
}
1673

1674
static int
1675
__clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1676
{
1677
	unsigned long idle;
1678
	int e;
1679

1680
	idle = card->tst[card->tst_index ^ 1];
1681

1682
	for (e = 0; e < card->tst_size - 2; e++) {
1683
		if (card->soft_tst[e].vc == vc) {
1684
			card->soft_tst[e].vc = NULL;
1685

1686
			card->soft_tst[e].tste = TSTE_OPC_VAR;
1687
			if (timer_pending(&card->tst_timer))
1688
				card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1689
			else {
1690
				write_sram(card, idle + e, TSTE_OPC_VAR);
1691
				card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1692
			}
1693
		}
1694
	}
1695

1696
	return 0;
1697
}
1698

1699
static int
1700
clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1701
{
1702
	unsigned long flags;
1703
	int res;
1704

1705
	spin_lock_irqsave(&card->tst_lock, flags);
1706

1707
	res = __clear_tst(card, vc);
1708

1709
	set_bit(TST_SWITCH_PENDING, &card->tst_state);
1710
	if (!timer_pending(&card->tst_timer))
1711
		mod_timer(&card->tst_timer, jiffies + 1);
1712

1713
	spin_unlock_irqrestore(&card->tst_lock, flags);
1714
	return res;
1715
}
1716

1717
static int
1718
change_tst(struct idt77252_dev *card, struct vc_map *vc,
1719
	   int n, unsigned int opc)
1720
{
1721
	unsigned long flags;
1722
	int res;
1723

1724
	spin_lock_irqsave(&card->tst_lock, flags);
1725

1726
	__clear_tst(card, vc);
1727
	res = __fill_tst(card, vc, n, opc);
1728

1729
	set_bit(TST_SWITCH_PENDING, &card->tst_state);
1730
	if (!timer_pending(&card->tst_timer))
1731
		mod_timer(&card->tst_timer, jiffies + 1);
1732

1733
	spin_unlock_irqrestore(&card->tst_lock, flags);
1734
	return res;
1735
}
1736

1737

1738
static int
1739
set_tct(struct idt77252_dev *card, struct vc_map *vc)
1740
{
1741
	unsigned long tct;
1742

1743
	tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE);
1744

1745
	switch (vc->class) {
1746
	case SCHED_CBR:
1747
		OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1748
		        card->name, tct, vc->scq->scd);
1749

1750
		write_sram(card, tct + 0, TCT_CBR | vc->scq->scd);
1751
		write_sram(card, tct + 1, 0);
1752
		write_sram(card, tct + 2, 0);
1753
		write_sram(card, tct + 3, 0);
1754
		write_sram(card, tct + 4, 0);
1755
		write_sram(card, tct + 5, 0);
1756
		write_sram(card, tct + 6, 0);
1757
		write_sram(card, tct + 7, 0);
1758
		break;
1759

1760
	case SCHED_UBR:
1761
		OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1762
		        card->name, tct, vc->scq->scd);
1763

1764
		write_sram(card, tct + 0, TCT_UBR | vc->scq->scd);
1765
		write_sram(card, tct + 1, 0);
1766
		write_sram(card, tct + 2, TCT_TSIF);
1767
		write_sram(card, tct + 3, TCT_HALT | TCT_IDLE);
1768
		write_sram(card, tct + 4, 0);
1769
		write_sram(card, tct + 5, vc->init_er);
1770
		write_sram(card, tct + 6, 0);
1771
		write_sram(card, tct + 7, TCT_FLAG_UBR);
1772
		break;
1773

1774
	case SCHED_VBR:
1775
	case SCHED_ABR:
1776
	default:
1777
		return -ENOSYS;
1778
	}
1779

1780
	return 0;
1781
}
1782

1783
/*****************************************************************************/
1784
/*                                                                           */
1785
/* FBQ Handling                                                              */
1786
/*                                                                           */
1787
/*****************************************************************************/
1788

1789
static __inline__ int
1790
idt77252_fbq_full(struct idt77252_dev *card, int queue)
1791
{
1792
	return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f;
1793
}
1794

1795
static int
1796
push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue)
1797
{
1798
	unsigned long flags;
1799
	u32 handle;
1800
	u32 addr;
1801

1802
	skb->data = skb->head;
1803
	skb_reset_tail_pointer(skb);
1804
	skb->len = 0;
1805

1806
	skb_reserve(skb, 16);
1807

1808
	switch (queue) {
1809
	case 0:
1810
		skb_put(skb, SAR_FB_SIZE_0);
1811
		break;
1812
	case 1:
1813
		skb_put(skb, SAR_FB_SIZE_1);
1814
		break;
1815
	case 2:
1816
		skb_put(skb, SAR_FB_SIZE_2);
1817
		break;
1818
	case 3:
1819
		skb_put(skb, SAR_FB_SIZE_3);
1820
		break;
1821
	default:
1822
		return -1;
1823
	}
1824

1825
	if (idt77252_fbq_full(card, queue))
1826
		return -1;
1827

1828
	memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32));
1829

1830
	handle = IDT77252_PRV_POOL(skb);
1831
	addr = IDT77252_PRV_PADDR(skb);
1832

1833
	spin_lock_irqsave(&card->cmd_lock, flags);
1834
	writel(handle, card->fbq[queue]);
1835
	writel(addr, card->fbq[queue]);
1836
	spin_unlock_irqrestore(&card->cmd_lock, flags);
1837

1838
	return 0;
1839
}
1840

1841
static void
1842
add_rx_skb(struct idt77252_dev *card, int queue,
1843
	   unsigned int size, unsigned int count)
1844
{
1845
	struct sk_buff *skb;
1846
	dma_addr_t paddr;
1847
	u32 handle;
1848

1849
	while (count--) {
1850
		skb = dev_alloc_skb(size);
1851
		if (!skb)
1852
			return;
1853

1854
		if (sb_pool_add(card, skb, queue)) {
1855
			printk("%s: SB POOL full\n", __func__);
1856
			goto outfree;
1857
		}
1858

1859
		paddr = dma_map_single(&card->pcidev->dev, skb->data,
1860
				       skb_end_pointer(skb) - skb->data,
1861
				       DMA_FROM_DEVICE);
1862
		if (dma_mapping_error(&card->pcidev->dev, paddr))
1863
			goto outpoolrm;
1864
		IDT77252_PRV_PADDR(skb) = paddr;
1865

1866
		if (push_rx_skb(card, skb, queue)) {
1867
			printk("%s: FB QUEUE full\n", __func__);
1868
			goto outunmap;
1869
		}
1870
	}
1871

1872
	return;
1873

1874
outunmap:
1875
	dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
1876
			 skb_end_pointer(skb) - skb->data, DMA_FROM_DEVICE);
1877

1878
outpoolrm:
1879
	handle = IDT77252_PRV_POOL(skb);
1880
	card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL;
1881

1882
outfree:
1883
	dev_kfree_skb(skb);
1884
}
1885

1886

1887
static void
1888
recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb)
1889
{
1890
	u32 handle = IDT77252_PRV_POOL(skb);
1891
	int err;
1892

1893
	dma_sync_single_for_device(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
1894
				   skb_end_pointer(skb) - skb->data,
1895
				   DMA_FROM_DEVICE);
1896

1897
	err = push_rx_skb(card, skb, POOL_QUEUE(handle));
1898
	if (err) {
1899
		dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
1900
				 skb_end_pointer(skb) - skb->data,
1901
				 DMA_FROM_DEVICE);
1902
		sb_pool_remove(card, skb);
1903
		dev_kfree_skb(skb);
1904
	}
1905
}
1906

1907
static void
1908
flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp)
1909
{
1910
	skb_queue_head_init(&rpp->queue);
1911
	rpp->len = 0;
1912
}
1913

1914
static void
1915
recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp)
1916
{
1917
	struct sk_buff *skb, *tmp;
1918

1919
	skb_queue_walk_safe(&rpp->queue, skb, tmp)
1920
		recycle_rx_skb(card, skb);
1921

1922
	flush_rx_pool(card, rpp);
1923
}
1924

1925
/*****************************************************************************/
1926
/*                                                                           */
1927
/* ATM Interface                                                             */
1928
/*                                                                           */
1929
/*****************************************************************************/
1930

1931
static void
1932
idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr)
1933
{
1934
	write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value);
1935
}
1936

1937
static unsigned char
1938
idt77252_phy_get(struct atm_dev *dev, unsigned long addr)
1939
{
1940
	return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff));
1941
}
1942

1943
static inline int
1944
idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam)
1945
{
1946
	struct atm_dev *dev = vcc->dev;
1947
	struct idt77252_dev *card = dev->dev_data;
1948
	struct vc_map *vc = vcc->dev_data;
1949
	int err;
1950

1951
	if (vc == NULL) {
1952
		printk("%s: NULL connection in send().\n", card->name);
1953
		atomic_inc(&vcc->stats->tx_err);
1954
		dev_kfree_skb(skb);
1955
		return -EINVAL;
1956
	}
1957
	if (!test_bit(VCF_TX, &vc->flags)) {
1958
		printk("%s: Trying to transmit on a non-tx VC.\n", card->name);
1959
		atomic_inc(&vcc->stats->tx_err);
1960
		dev_kfree_skb(skb);
1961
		return -EINVAL;
1962
	}
1963

1964
	switch (vcc->qos.aal) {
1965
	case ATM_AAL0:
1966
	case ATM_AAL1:
1967
	case ATM_AAL5:
1968
		break;
1969
	default:
1970
		printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
1971
		atomic_inc(&vcc->stats->tx_err);
1972
		dev_kfree_skb(skb);
1973
		return -EINVAL;
1974
	}
1975

1976
	if (skb_shinfo(skb)->nr_frags != 0) {
1977
		printk("%s: No scatter-gather yet.\n", card->name);
1978
		atomic_inc(&vcc->stats->tx_err);
1979
		dev_kfree_skb(skb);
1980
		return -EINVAL;
1981
	}
1982
	ATM_SKB(skb)->vcc = vcc;
1983

1984
	err = queue_skb(card, vc, skb, oam);
1985
	if (err) {
1986
		atomic_inc(&vcc->stats->tx_err);
1987
		dev_kfree_skb(skb);
1988
		return err;
1989
	}
1990

1991
	return 0;
1992
}
1993

1994
static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb)
1995
{
1996
	return idt77252_send_skb(vcc, skb, 0);
1997
}
1998

1999
static int
2000
idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags)
2001
{
2002
	struct atm_dev *dev = vcc->dev;
2003
	struct idt77252_dev *card = dev->dev_data;
2004
	struct sk_buff *skb;
2005

2006
	skb = dev_alloc_skb(64);
2007
	if (!skb) {
2008
		printk("%s: Out of memory in send_oam().\n", card->name);
2009
		atomic_inc(&vcc->stats->tx_err);
2010
		return -ENOMEM;
2011
	}
2012
	refcount_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc);
2013

2014
	skb_put_data(skb, cell, 52);
2015

2016
	return idt77252_send_skb(vcc, skb, 1);
2017
}
2018

2019
static __inline__ unsigned int
2020
idt77252_fls(unsigned int x)
2021
{
2022
	int r = 1;
2023

2024
	if (x == 0)
2025
		return 0;
2026
	if (x & 0xffff0000) {
2027
		x >>= 16;
2028
		r += 16;
2029
	}
2030
	if (x & 0xff00) {
2031
		x >>= 8;
2032
		r += 8;
2033
	}
2034
	if (x & 0xf0) {
2035
		x >>= 4;
2036
		r += 4;
2037
	}
2038
	if (x & 0xc) {
2039
		x >>= 2;
2040
		r += 2;
2041
	}
2042
	if (x & 0x2)
2043
		r += 1;
2044
	return r;
2045
}
2046

2047
static u16
2048
idt77252_int_to_atmfp(unsigned int rate)
2049
{
2050
	u16 m, e;
2051

2052
	if (rate == 0)
2053
		return 0;
2054
	e = idt77252_fls(rate) - 1;
2055
	if (e < 9)
2056
		m = (rate - (1 << e)) << (9 - e);
2057
	else if (e == 9)
2058
		m = (rate - (1 << e));
2059
	else /* e > 9 */
2060
		m = (rate - (1 << e)) >> (e - 9);
2061
	return 0x4000 | (e << 9) | m;
2062
}
2063

2064
static u8
2065
idt77252_rate_logindex(struct idt77252_dev *card, int pcr)
2066
{
2067
	u16 afp;
2068

2069
	afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr);
2070
	if (pcr < 0)
2071
		return rate_to_log[(afp >> 5) & 0x1ff];
2072
	return rate_to_log[((afp >> 5) + 1) & 0x1ff];
2073
}
2074

2075
static void
2076
idt77252_est_timer(struct timer_list *t)
2077
{
2078
	struct rate_estimator *est = timer_container_of(est, t, timer);
2079
	struct vc_map *vc = est->vc;
2080
	struct idt77252_dev *card = vc->card;
2081
	unsigned long flags;
2082
	u32 rate, cps;
2083
	u64 ncells;
2084
	u8 lacr;
2085

2086
	spin_lock_irqsave(&vc->lock, flags);
2087
	if (!vc->estimator)
2088
		goto out;
2089
	ncells = est->cells;
2090

2091
	rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval);
2092
	est->last_cells = ncells;
2093
	est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log;
2094
	est->cps = (est->avcps + 0x1f) >> 5;
2095

2096
	cps = est->cps;
2097
	if (cps < (est->maxcps >> 4))
2098
		cps = est->maxcps >> 4;
2099

2100
	lacr = idt77252_rate_logindex(card, cps);
2101
	if (lacr > vc->max_er)
2102
		lacr = vc->max_er;
2103

2104
	if (lacr != vc->lacr) {
2105
		vc->lacr = lacr;
2106
		writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ);
2107
	}
2108

2109
	est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2110
	add_timer(&est->timer);
2111

2112
out:
2113
	spin_unlock_irqrestore(&vc->lock, flags);
2114
}
2115

2116
static struct rate_estimator *
2117
idt77252_init_est(struct vc_map *vc, int pcr)
2118
{
2119
	struct rate_estimator *est;
2120

2121
	est = kzalloc(sizeof(struct rate_estimator), GFP_KERNEL);
2122
	if (!est)
2123
		return NULL;
2124
	est->maxcps = pcr < 0 ? -pcr : pcr;
2125
	est->cps = est->maxcps;
2126
	est->avcps = est->cps << 5;
2127
	est->vc = vc;
2128

2129
	est->interval = 2;		/* XXX: make this configurable */
2130
	est->ewma_log = 2;		/* XXX: make this configurable */
2131
	timer_setup(&est->timer, idt77252_est_timer, 0);
2132
	mod_timer(&est->timer, jiffies + ((HZ / 4) << est->interval));
2133

2134
	return est;
2135
}
2136

2137
static int
2138
idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc,
2139
		  struct atm_vcc *vcc, struct atm_qos *qos)
2140
{
2141
	int tst_free, tst_used, tst_entries;
2142
	unsigned long tmpl, modl;
2143
	int tcr, tcra;
2144

2145
	if ((qos->txtp.max_pcr == 0) &&
2146
	    (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) {
2147
		printk("%s: trying to open a CBR VC with cell rate = 0\n",
2148
		       card->name);
2149
		return -EINVAL;
2150
	}
2151

2152
	tst_used = 0;
2153
	tst_free = card->tst_free;
2154
	if (test_bit(VCF_TX, &vc->flags))
2155
		tst_used = vc->ntste;
2156
	tst_free += tst_used;
2157

2158
	tcr = atm_pcr_goal(&qos->txtp);
2159
	tcra = tcr >= 0 ? tcr : -tcr;
2160

2161
	TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra);
2162

2163
	tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2);
2164
	modl = tmpl % (unsigned long)card->utopia_pcr;
2165

2166
	tst_entries = (int) (tmpl / card->utopia_pcr);
2167
	if (tcr > 0) {
2168
		if (modl > 0)
2169
			tst_entries++;
2170
	} else if (tcr == 0) {
2171
		tst_entries = tst_free - SAR_TST_RESERVED;
2172
		if (tst_entries <= 0) {
2173
			printk("%s: no CBR bandwidth free.\n", card->name);
2174
			return -ENOSR;
2175
		}
2176
	}
2177

2178
	if (tst_entries == 0) {
2179
		printk("%s: selected CBR bandwidth < granularity.\n",
2180
		       card->name);
2181
		return -EINVAL;
2182
	}
2183

2184
	if (tst_entries > (tst_free - SAR_TST_RESERVED)) {
2185
		printk("%s: not enough CBR bandwidth free.\n", card->name);
2186
		return -ENOSR;
2187
	}
2188

2189
	vc->ntste = tst_entries;
2190

2191
	card->tst_free = tst_free - tst_entries;
2192
	if (test_bit(VCF_TX, &vc->flags)) {
2193
		if (tst_used == tst_entries)
2194
			return 0;
2195

2196
		OPRINTK("%s: modify %d -> %d entries in TST.\n",
2197
			card->name, tst_used, tst_entries);
2198
		change_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2199
		return 0;
2200
	}
2201

2202
	OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries);
2203
	fill_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2204
	return 0;
2205
}
2206

2207
static int
2208
idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc,
2209
		  struct atm_vcc *vcc, struct atm_qos *qos)
2210
{
2211
	struct rate_estimator *est = NULL;
2212
	unsigned long flags;
2213
	int tcr;
2214

2215
	spin_lock_irqsave(&vc->lock, flags);
2216
	if (vc->estimator) {
2217
		est = vc->estimator;
2218
		vc->estimator = NULL;
2219
	}
2220
	spin_unlock_irqrestore(&vc->lock, flags);
2221
	if (est) {
2222
		timer_shutdown_sync(&est->timer);
2223
		kfree(est);
2224
	}
2225

2226
	tcr = atm_pcr_goal(&qos->txtp);
2227
	if (tcr == 0)
2228
		tcr = card->link_pcr;
2229

2230
	vc->estimator = idt77252_init_est(vc, tcr);
2231

2232
	vc->class = SCHED_UBR;
2233
	vc->init_er = idt77252_rate_logindex(card, tcr);
2234
	vc->lacr = vc->init_er;
2235
	if (tcr < 0)
2236
		vc->max_er = vc->init_er;
2237
	else
2238
		vc->max_er = 0xff;
2239

2240
	return 0;
2241
}
2242

2243
static int
2244
idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc,
2245
		 struct atm_vcc *vcc, struct atm_qos *qos)
2246
{
2247
	int error;
2248

2249
	if (test_bit(VCF_TX, &vc->flags))
2250
		return -EBUSY;
2251

2252
	switch (qos->txtp.traffic_class) {
2253
		case ATM_CBR:
2254
			vc->class = SCHED_CBR;
2255
			break;
2256

2257
		case ATM_UBR:
2258
			vc->class = SCHED_UBR;
2259
			break;
2260

2261
		case ATM_VBR:
2262
		case ATM_ABR:
2263
		default:
2264
			return -EPROTONOSUPPORT;
2265
	}
2266

2267
	vc->scq = alloc_scq(card, vc->class);
2268
	if (!vc->scq) {
2269
		printk("%s: can't get SCQ.\n", card->name);
2270
		return -ENOMEM;
2271
	}
2272

2273
	vc->scq->scd = get_free_scd(card, vc);
2274
	if (vc->scq->scd == 0) {
2275
		printk("%s: no SCD available.\n", card->name);
2276
		free_scq(card, vc->scq);
2277
		return -ENOMEM;
2278
	}
2279

2280
	fill_scd(card, vc->scq, vc->class);
2281

2282
	if (set_tct(card, vc)) {
2283
		printk("%s: class %d not supported.\n",
2284
		       card->name, qos->txtp.traffic_class);
2285

2286
		card->scd2vc[vc->scd_index] = NULL;
2287
		free_scq(card, vc->scq);
2288
		return -EPROTONOSUPPORT;
2289
	}
2290

2291
	switch (vc->class) {
2292
		case SCHED_CBR:
2293
			error = idt77252_init_cbr(card, vc, vcc, qos);
2294
			if (error) {
2295
				card->scd2vc[vc->scd_index] = NULL;
2296
				free_scq(card, vc->scq);
2297
				return error;
2298
			}
2299

2300
			clear_bit(VCF_IDLE, &vc->flags);
2301
			writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ);
2302
			break;
2303

2304
		case SCHED_UBR:
2305
			error = idt77252_init_ubr(card, vc, vcc, qos);
2306
			if (error) {
2307
				card->scd2vc[vc->scd_index] = NULL;
2308
				free_scq(card, vc->scq);
2309
				return error;
2310
			}
2311

2312
			set_bit(VCF_IDLE, &vc->flags);
2313
			break;
2314
	}
2315

2316
	vc->tx_vcc = vcc;
2317
	set_bit(VCF_TX, &vc->flags);
2318
	return 0;
2319
}
2320

2321
static int
2322
idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc,
2323
		 struct atm_vcc *vcc, struct atm_qos *qos)
2324
{
2325
	unsigned long flags;
2326
	unsigned long addr;
2327
	u32 rcte = 0;
2328

2329
	if (test_bit(VCF_RX, &vc->flags))
2330
		return -EBUSY;
2331

2332
	vc->rx_vcc = vcc;
2333
	set_bit(VCF_RX, &vc->flags);
2334

2335
	if ((vcc->vci == 3) || (vcc->vci == 4))
2336
		return 0;
2337

2338
	flush_rx_pool(card, &vc->rcv.rx_pool);
2339

2340
	rcte |= SAR_RCTE_CONNECTOPEN;
2341
	rcte |= SAR_RCTE_RAWCELLINTEN;
2342

2343
	switch (qos->aal) {
2344
		case ATM_AAL0:
2345
			rcte |= SAR_RCTE_RCQ;
2346
			break;
2347
		case ATM_AAL1:
2348
			rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */
2349
			break;
2350
		case ATM_AAL34:
2351
			rcte |= SAR_RCTE_AAL34;
2352
			break;
2353
		case ATM_AAL5:
2354
			rcte |= SAR_RCTE_AAL5;
2355
			break;
2356
		default:
2357
			rcte |= SAR_RCTE_RCQ;
2358
			break;
2359
	}
2360

2361
	if (qos->aal != ATM_AAL5)
2362
		rcte |= SAR_RCTE_FBP_1;
2363
	else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2)
2364
		rcte |= SAR_RCTE_FBP_3;
2365
	else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1)
2366
		rcte |= SAR_RCTE_FBP_2;
2367
	else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0)
2368
		rcte |= SAR_RCTE_FBP_1;
2369
	else
2370
		rcte |= SAR_RCTE_FBP_01;
2371

2372
	addr = card->rct_base + (vc->index << 2);
2373

2374
	OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr);
2375
	write_sram(card, addr, rcte);
2376

2377
	spin_lock_irqsave(&card->cmd_lock, flags);
2378
	writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD);
2379
	waitfor_idle(card);
2380
	spin_unlock_irqrestore(&card->cmd_lock, flags);
2381

2382
	return 0;
2383
}
2384

2385
static int
2386
idt77252_open(struct atm_vcc *vcc)
2387
{
2388
	struct atm_dev *dev = vcc->dev;
2389
	struct idt77252_dev *card = dev->dev_data;
2390
	struct vc_map *vc;
2391
	unsigned int index;
2392
	unsigned int inuse;
2393
	int error;
2394
	int vci = vcc->vci;
2395
	short vpi = vcc->vpi;
2396

2397
	if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC)
2398
		return 0;
2399

2400
	if (vpi >= (1 << card->vpibits)) {
2401
		printk("%s: unsupported VPI: %d\n", card->name, vpi);
2402
		return -EINVAL;
2403
	}
2404

2405
	if (vci >= (1 << card->vcibits)) {
2406
		printk("%s: unsupported VCI: %d\n", card->name, vci);
2407
		return -EINVAL;
2408
	}
2409

2410
	set_bit(ATM_VF_ADDR, &vcc->flags);
2411

2412
	mutex_lock(&card->mutex);
2413

2414
	OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci);
2415

2416
	switch (vcc->qos.aal) {
2417
	case ATM_AAL0:
2418
	case ATM_AAL1:
2419
	case ATM_AAL5:
2420
		break;
2421
	default:
2422
		printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
2423
		mutex_unlock(&card->mutex);
2424
		return -EPROTONOSUPPORT;
2425
	}
2426

2427
	index = VPCI2VC(card, vpi, vci);
2428
	if (!card->vcs[index]) {
2429
		card->vcs[index] = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2430
		if (!card->vcs[index]) {
2431
			printk("%s: can't alloc vc in open()\n", card->name);
2432
			mutex_unlock(&card->mutex);
2433
			return -ENOMEM;
2434
		}
2435
		card->vcs[index]->card = card;
2436
		card->vcs[index]->index = index;
2437

2438
		spin_lock_init(&card->vcs[index]->lock);
2439
	}
2440
	vc = card->vcs[index];
2441

2442
	vcc->dev_data = vc;
2443

2444
	IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n",
2445
	        card->name, vc->index, vcc->vpi, vcc->vci,
2446
	        vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--",
2447
	        vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--",
2448
	        vcc->qos.rxtp.max_sdu);
2449

2450
	inuse = 0;
2451
	if (vcc->qos.txtp.traffic_class != ATM_NONE &&
2452
	    test_bit(VCF_TX, &vc->flags))
2453
		inuse = 1;
2454
	if (vcc->qos.rxtp.traffic_class != ATM_NONE &&
2455
	    test_bit(VCF_RX, &vc->flags))
2456
		inuse += 2;
2457

2458
	if (inuse) {
2459
		printk("%s: %s vci already in use.\n", card->name,
2460
		       inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
2461
		mutex_unlock(&card->mutex);
2462
		return -EADDRINUSE;
2463
	}
2464

2465
	if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2466
		error = idt77252_init_tx(card, vc, vcc, &vcc->qos);
2467
		if (error) {
2468
			mutex_unlock(&card->mutex);
2469
			return error;
2470
		}
2471
	}
2472

2473
	if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2474
		error = idt77252_init_rx(card, vc, vcc, &vcc->qos);
2475
		if (error) {
2476
			mutex_unlock(&card->mutex);
2477
			return error;
2478
		}
2479
	}
2480

2481
	set_bit(ATM_VF_READY, &vcc->flags);
2482

2483
	mutex_unlock(&card->mutex);
2484
	return 0;
2485
}
2486

2487
static void
2488
idt77252_close(struct atm_vcc *vcc)
2489
{
2490
	struct atm_dev *dev = vcc->dev;
2491
	struct idt77252_dev *card = dev->dev_data;
2492
	struct vc_map *vc = vcc->dev_data;
2493
	unsigned long flags;
2494
	unsigned long addr;
2495
	unsigned long timeout;
2496

2497
	mutex_lock(&card->mutex);
2498

2499
	IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n",
2500
		card->name, vc->index, vcc->vpi, vcc->vci);
2501

2502
	clear_bit(ATM_VF_READY, &vcc->flags);
2503

2504
	if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2505

2506
		spin_lock_irqsave(&vc->lock, flags);
2507
		clear_bit(VCF_RX, &vc->flags);
2508
		vc->rx_vcc = NULL;
2509
		spin_unlock_irqrestore(&vc->lock, flags);
2510

2511
		if ((vcc->vci == 3) || (vcc->vci == 4))
2512
			goto done;
2513

2514
		addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2515

2516
		spin_lock_irqsave(&card->cmd_lock, flags);
2517
		writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD);
2518
		waitfor_idle(card);
2519
		spin_unlock_irqrestore(&card->cmd_lock, flags);
2520

2521
		if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) {
2522
			DPRINTK("%s: closing a VC with pending rx buffers.\n",
2523
				card->name);
2524

2525
			recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2526
		}
2527
	}
2528

2529
done:
2530
	if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2531

2532
		spin_lock_irqsave(&vc->lock, flags);
2533
		clear_bit(VCF_TX, &vc->flags);
2534
		clear_bit(VCF_IDLE, &vc->flags);
2535
		clear_bit(VCF_RSV, &vc->flags);
2536
		vc->tx_vcc = NULL;
2537

2538
		if (vc->estimator) {
2539
			timer_shutdown(&vc->estimator->timer);
2540
			kfree(vc->estimator);
2541
			vc->estimator = NULL;
2542
		}
2543
		spin_unlock_irqrestore(&vc->lock, flags);
2544

2545
		timeout = 5 * 1000;
2546
		while (atomic_read(&vc->scq->used) > 0) {
2547
			timeout = msleep_interruptible(timeout);
2548
			if (!timeout) {
2549
				pr_warn("%s: SCQ drain timeout: %u used\n",
2550
					card->name, atomic_read(&vc->scq->used));
2551
				break;
2552
			}
2553
		}
2554

2555
		writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ);
2556
		clear_scd(card, vc->scq, vc->class);
2557

2558
		if (vc->class == SCHED_CBR) {
2559
			clear_tst(card, vc);
2560
			card->tst_free += vc->ntste;
2561
			vc->ntste = 0;
2562
		}
2563

2564
		card->scd2vc[vc->scd_index] = NULL;
2565
		free_scq(card, vc->scq);
2566
	}
2567

2568
	mutex_unlock(&card->mutex);
2569
}
2570

2571
static int
2572
idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
2573
{
2574
	struct atm_dev *dev = vcc->dev;
2575
	struct idt77252_dev *card = dev->dev_data;
2576
	struct vc_map *vc = vcc->dev_data;
2577
	int error = 0;
2578

2579
	mutex_lock(&card->mutex);
2580

2581
	if (qos->txtp.traffic_class != ATM_NONE) {
2582
	    	if (!test_bit(VCF_TX, &vc->flags)) {
2583
			error = idt77252_init_tx(card, vc, vcc, qos);
2584
			if (error)
2585
				goto out;
2586
		} else {
2587
			switch (qos->txtp.traffic_class) {
2588
			case ATM_CBR:
2589
				error = idt77252_init_cbr(card, vc, vcc, qos);
2590
				if (error)
2591
					goto out;
2592
				break;
2593

2594
			case ATM_UBR:
2595
				error = idt77252_init_ubr(card, vc, vcc, qos);
2596
				if (error)
2597
					goto out;
2598

2599
				if (!test_bit(VCF_IDLE, &vc->flags)) {
2600
					writel(TCMDQ_LACR | (vc->lacr << 16) |
2601
					       vc->index, SAR_REG_TCMDQ);
2602
				}
2603
				break;
2604

2605
			case ATM_VBR:
2606
			case ATM_ABR:
2607
				error = -EOPNOTSUPP;
2608
				goto out;
2609
			}
2610
		}
2611
	}
2612

2613
	if ((qos->rxtp.traffic_class != ATM_NONE) &&
2614
	    !test_bit(VCF_RX, &vc->flags)) {
2615
		error = idt77252_init_rx(card, vc, vcc, qos);
2616
		if (error)
2617
			goto out;
2618
	}
2619

2620
	memcpy(&vcc->qos, qos, sizeof(struct atm_qos));
2621

2622
	set_bit(ATM_VF_HASQOS, &vcc->flags);
2623

2624
out:
2625
	mutex_unlock(&card->mutex);
2626
	return error;
2627
}
2628

2629
static int
2630
idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2631
{
2632
	struct idt77252_dev *card = dev->dev_data;
2633
	int i, left;
2634

2635
	left = (int) *pos;
2636
	if (!left--)
2637
		return sprintf(page, "IDT77252 Interrupts:\n");
2638
	if (!left--)
2639
		return sprintf(page, "TSIF:  %lu\n", card->irqstat[15]);
2640
	if (!left--)
2641
		return sprintf(page, "TXICP: %lu\n", card->irqstat[14]);
2642
	if (!left--)
2643
		return sprintf(page, "TSQF:  %lu\n", card->irqstat[12]);
2644
	if (!left--)
2645
		return sprintf(page, "TMROF: %lu\n", card->irqstat[11]);
2646
	if (!left--)
2647
		return sprintf(page, "PHYI:  %lu\n", card->irqstat[10]);
2648
	if (!left--)
2649
		return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]);
2650
	if (!left--)
2651
		return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]);
2652
	if (!left--)
2653
		return sprintf(page, "RSQF:  %lu\n", card->irqstat[6]);
2654
	if (!left--)
2655
		return sprintf(page, "EPDU:  %lu\n", card->irqstat[5]);
2656
	if (!left--)
2657
		return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]);
2658
	if (!left--)
2659
		return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]);
2660
	if (!left--)
2661
		return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]);
2662
	if (!left--)
2663
		return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]);
2664
	if (!left--)
2665
		return sprintf(page, "IDT77252 Transmit Connection Table:\n");
2666

2667
	for (i = 0; i < card->tct_size; i++) {
2668
		unsigned long tct;
2669
		struct atm_vcc *vcc;
2670
		struct vc_map *vc;
2671
		char *p;
2672

2673
		vc = card->vcs[i];
2674
		if (!vc)
2675
			continue;
2676

2677
		vcc = NULL;
2678
		if (vc->tx_vcc)
2679
			vcc = vc->tx_vcc;
2680
		if (!vcc)
2681
			continue;
2682
		if (left--)
2683
			continue;
2684

2685
		p = page;
2686
		p += sprintf(p, "  %4u: %u.%u: ", i, vcc->vpi, vcc->vci);
2687
		tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE);
2688

2689
		for (i = 0; i < 8; i++)
2690
			p += sprintf(p, " %08x", read_sram(card, tct + i));
2691
		p += sprintf(p, "\n");
2692
		return p - page;
2693
	}
2694
	return 0;
2695
}
2696

2697
/*****************************************************************************/
2698
/*                                                                           */
2699
/* Interrupt handler                                                         */
2700
/*                                                                           */
2701
/*****************************************************************************/
2702

2703
static void
2704
idt77252_collect_stat(struct idt77252_dev *card)
2705
{
2706
	(void) readl(SAR_REG_CDC);
2707
	(void) readl(SAR_REG_VPEC);
2708
	(void) readl(SAR_REG_ICC);
2709

2710
}
2711

2712
static irqreturn_t
2713
idt77252_interrupt(int irq, void *dev_id)
2714
{
2715
	struct idt77252_dev *card = dev_id;
2716
	u32 stat;
2717

2718
	stat = readl(SAR_REG_STAT) & 0xffff;
2719
	if (!stat)	/* no interrupt for us */
2720
		return IRQ_NONE;
2721

2722
	if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) {
2723
		printk("%s: Re-entering irq_handler()\n", card->name);
2724
		goto out;
2725
	}
2726

2727
	writel(stat, SAR_REG_STAT);	/* reset interrupt */
2728

2729
	if (stat & SAR_STAT_TSIF) {	/* entry written to TSQ  */
2730
		INTPRINTK("%s: TSIF\n", card->name);
2731
		card->irqstat[15]++;
2732
		idt77252_tx(card);
2733
	}
2734
	if (stat & SAR_STAT_TXICP) {	/* Incomplete CS-PDU has  */
2735
		INTPRINTK("%s: TXICP\n", card->name);
2736
		card->irqstat[14]++;
2737
#ifdef CONFIG_ATM_IDT77252_DEBUG
2738
		idt77252_tx_dump(card);
2739
#endif
2740
	}
2741
	if (stat & SAR_STAT_TSQF) {	/* TSQ 7/8 full           */
2742
		INTPRINTK("%s: TSQF\n", card->name);
2743
		card->irqstat[12]++;
2744
		idt77252_tx(card);
2745
	}
2746
	if (stat & SAR_STAT_TMROF) {	/* Timer overflow         */
2747
		INTPRINTK("%s: TMROF\n", card->name);
2748
		card->irqstat[11]++;
2749
		idt77252_collect_stat(card);
2750
	}
2751

2752
	if (stat & SAR_STAT_EPDU) {	/* Got complete CS-PDU    */
2753
		INTPRINTK("%s: EPDU\n", card->name);
2754
		card->irqstat[5]++;
2755
		idt77252_rx(card);
2756
	}
2757
	if (stat & SAR_STAT_RSQAF) {	/* RSQ is 7/8 full        */
2758
		INTPRINTK("%s: RSQAF\n", card->name);
2759
		card->irqstat[1]++;
2760
		idt77252_rx(card);
2761
	}
2762
	if (stat & SAR_STAT_RSQF) {	/* RSQ is full            */
2763
		INTPRINTK("%s: RSQF\n", card->name);
2764
		card->irqstat[6]++;
2765
		idt77252_rx(card);
2766
	}
2767
	if (stat & SAR_STAT_RAWCF) {	/* Raw cell received      */
2768
		INTPRINTK("%s: RAWCF\n", card->name);
2769
		card->irqstat[4]++;
2770
		idt77252_rx_raw(card);
2771
	}
2772

2773
	if (stat & SAR_STAT_PHYI) {	/* PHY device interrupt   */
2774
		INTPRINTK("%s: PHYI", card->name);
2775
		card->irqstat[10]++;
2776
		if (card->atmdev->phy && card->atmdev->phy->interrupt)
2777
			card->atmdev->phy->interrupt(card->atmdev);
2778
	}
2779

2780
	if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A |
2781
		    SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) {
2782

2783
		writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG);
2784

2785
		INTPRINTK("%s: FBQA: %04x\n", card->name, stat);
2786

2787
		if (stat & SAR_STAT_FBQ0A)
2788
			card->irqstat[2]++;
2789
		if (stat & SAR_STAT_FBQ1A)
2790
			card->irqstat[3]++;
2791
		if (stat & SAR_STAT_FBQ2A)
2792
			card->irqstat[7]++;
2793
		if (stat & SAR_STAT_FBQ3A)
2794
			card->irqstat[8]++;
2795

2796
		schedule_work(&card->tqueue);
2797
	}
2798

2799
out:
2800
	clear_bit(IDT77252_BIT_INTERRUPT, &card->flags);
2801
	return IRQ_HANDLED;
2802
}
2803

2804
static void
2805
idt77252_softint(struct work_struct *work)
2806
{
2807
	struct idt77252_dev *card =
2808
		container_of(work, struct idt77252_dev, tqueue);
2809
	u32 stat;
2810
	int done;
2811

2812
	for (done = 1; ; done = 1) {
2813
		stat = readl(SAR_REG_STAT) >> 16;
2814

2815
		if ((stat & 0x0f) < SAR_FBQ0_HIGH) {
2816
			add_rx_skb(card, 0, SAR_FB_SIZE_0, 32);
2817
			done = 0;
2818
		}
2819

2820
		stat >>= 4;
2821
		if ((stat & 0x0f) < SAR_FBQ1_HIGH) {
2822
			add_rx_skb(card, 1, SAR_FB_SIZE_1, 32);
2823
			done = 0;
2824
		}
2825

2826
		stat >>= 4;
2827
		if ((stat & 0x0f) < SAR_FBQ2_HIGH) {
2828
			add_rx_skb(card, 2, SAR_FB_SIZE_2, 32);
2829
			done = 0;
2830
		}
2831

2832
		stat >>= 4;
2833
		if ((stat & 0x0f) < SAR_FBQ3_HIGH) {
2834
			add_rx_skb(card, 3, SAR_FB_SIZE_3, 32);
2835
			done = 0;
2836
		}
2837

2838
		if (done)
2839
			break;
2840
	}
2841

2842
	writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG);
2843
}
2844

2845

2846
static int
2847
open_card_oam(struct idt77252_dev *card)
2848
{
2849
	unsigned long flags;
2850
	unsigned long addr;
2851
	struct vc_map *vc;
2852
	int vpi, vci;
2853
	int index;
2854
	u32 rcte;
2855

2856
	for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2857
		for (vci = 3; vci < 5; vci++) {
2858
			index = VPCI2VC(card, vpi, vci);
2859

2860
			vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2861
			if (!vc) {
2862
				printk("%s: can't alloc vc\n", card->name);
2863
				return -ENOMEM;
2864
			}
2865
			vc->index = index;
2866
			card->vcs[index] = vc;
2867

2868
			flush_rx_pool(card, &vc->rcv.rx_pool);
2869

2870
			rcte = SAR_RCTE_CONNECTOPEN |
2871
			       SAR_RCTE_RAWCELLINTEN |
2872
			       SAR_RCTE_RCQ |
2873
			       SAR_RCTE_FBP_1;
2874

2875
			addr = card->rct_base + (vc->index << 2);
2876
			write_sram(card, addr, rcte);
2877

2878
			spin_lock_irqsave(&card->cmd_lock, flags);
2879
			writel(SAR_CMD_OPEN_CONNECTION | (addr << 2),
2880
			       SAR_REG_CMD);
2881
			waitfor_idle(card);
2882
			spin_unlock_irqrestore(&card->cmd_lock, flags);
2883
		}
2884
	}
2885

2886
	return 0;
2887
}
2888

2889
static void
2890
close_card_oam(struct idt77252_dev *card)
2891
{
2892
	unsigned long flags;
2893
	unsigned long addr;
2894
	struct vc_map *vc;
2895
	int vpi, vci;
2896
	int index;
2897

2898
	for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2899
		for (vci = 3; vci < 5; vci++) {
2900
			index = VPCI2VC(card, vpi, vci);
2901
			vc = card->vcs[index];
2902

2903
			addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2904

2905
			spin_lock_irqsave(&card->cmd_lock, flags);
2906
			writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2),
2907
			       SAR_REG_CMD);
2908
			waitfor_idle(card);
2909
			spin_unlock_irqrestore(&card->cmd_lock, flags);
2910

2911
			if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) {
2912
				DPRINTK("%s: closing a VC "
2913
					"with pending rx buffers.\n",
2914
					card->name);
2915

2916
				recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2917
			}
2918
			kfree(vc);
2919
		}
2920
	}
2921
}
2922

2923
static int
2924
open_card_ubr0(struct idt77252_dev *card)
2925
{
2926
	struct vc_map *vc;
2927

2928
	vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2929
	if (!vc) {
2930
		printk("%s: can't alloc vc\n", card->name);
2931
		return -ENOMEM;
2932
	}
2933
	card->vcs[0] = vc;
2934
	vc->class = SCHED_UBR0;
2935

2936
	vc->scq = alloc_scq(card, vc->class);
2937
	if (!vc->scq) {
2938
		printk("%s: can't get SCQ.\n", card->name);
2939
		kfree(card->vcs[0]);
2940
		card->vcs[0] = NULL;
2941
		return -ENOMEM;
2942
	}
2943

2944
	card->scd2vc[0] = vc;
2945
	vc->scd_index = 0;
2946
	vc->scq->scd = card->scd_base;
2947

2948
	fill_scd(card, vc->scq, vc->class);
2949

2950
	write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base);
2951
	write_sram(card, card->tct_base + 1, 0);
2952
	write_sram(card, card->tct_base + 2, 0);
2953
	write_sram(card, card->tct_base + 3, 0);
2954
	write_sram(card, card->tct_base + 4, 0);
2955
	write_sram(card, card->tct_base + 5, 0);
2956
	write_sram(card, card->tct_base + 6, 0);
2957
	write_sram(card, card->tct_base + 7, TCT_FLAG_UBR);
2958

2959
	clear_bit(VCF_IDLE, &vc->flags);
2960
	writel(TCMDQ_START | 0, SAR_REG_TCMDQ);
2961
	return 0;
2962
}
2963

2964
static void
2965
close_card_ubr0(struct idt77252_dev *card)
2966
{
2967
	struct vc_map *vc = card->vcs[0];
2968

2969
	free_scq(card, vc->scq);
2970
	kfree(vc);
2971
}
2972

2973
static int
2974
idt77252_dev_open(struct idt77252_dev *card)
2975
{
2976
	u32 conf;
2977

2978
	if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
2979
		printk("%s: SAR not yet initialized.\n", card->name);
2980
		return -1;
2981
	}
2982

2983
	conf = SAR_CFG_RXPTH|	/* enable receive path                  */
2984
	    SAR_RX_DELAY |	/* interrupt on complete PDU		*/
2985
	    SAR_CFG_RAWIE |	/* interrupt enable on raw cells        */
2986
	    SAR_CFG_RQFIE |	/* interrupt on RSQ almost full         */
2987
	    SAR_CFG_TMOIE |	/* interrupt on timer overflow          */
2988
	    SAR_CFG_FBIE |	/* interrupt on low free buffers        */
2989
	    SAR_CFG_TXEN |	/* transmit operation enable            */
2990
	    SAR_CFG_TXINT |	/* interrupt on transmit status         */
2991
	    SAR_CFG_TXUIE |	/* interrupt on transmit underrun       */
2992
	    SAR_CFG_TXSFI |	/* interrupt on TSQ almost full         */
2993
	    SAR_CFG_PHYIE	/* enable PHY interrupts		*/
2994
	    ;
2995

2996
#ifdef CONFIG_ATM_IDT77252_RCV_ALL
2997
	/* Test RAW cell receive. */
2998
	conf |= SAR_CFG_VPECA;
2999
#endif
3000

3001
	writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3002

3003
	if (open_card_oam(card)) {
3004
		printk("%s: Error initializing OAM.\n", card->name);
3005
		return -1;
3006
	}
3007

3008
	if (open_card_ubr0(card)) {
3009
		printk("%s: Error initializing UBR0.\n", card->name);
3010
		return -1;
3011
	}
3012

3013
	IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name);
3014
	return 0;
3015
}
3016

3017
static void idt77252_dev_close(struct atm_dev *dev)
3018
{
3019
	struct idt77252_dev *card = dev->dev_data;
3020
	u32 conf;
3021

3022
	close_card_ubr0(card);
3023
	close_card_oam(card);
3024

3025
	conf = SAR_CFG_RXPTH |	/* enable receive path           */
3026
	    SAR_RX_DELAY |	/* interrupt on complete PDU     */
3027
	    SAR_CFG_RAWIE |	/* interrupt enable on raw cells */
3028
	    SAR_CFG_RQFIE |	/* interrupt on RSQ almost full  */
3029
	    SAR_CFG_TMOIE |	/* interrupt on timer overflow   */
3030
	    SAR_CFG_FBIE |	/* interrupt on low free buffers */
3031
	    SAR_CFG_TXEN |	/* transmit operation enable     */
3032
	    SAR_CFG_TXINT |	/* interrupt on transmit status  */
3033
	    SAR_CFG_TXUIE |	/* interrupt on xmit underrun    */
3034
	    SAR_CFG_TXSFI	/* interrupt on TSQ almost full  */
3035
	    ;
3036

3037
	writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG);
3038

3039
	DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name);
3040
}
3041

3042

3043
/*****************************************************************************/
3044
/*                                                                           */
3045
/* Initialisation and Deinitialization of IDT77252                           */
3046
/*                                                                           */
3047
/*****************************************************************************/
3048

3049

3050
static void
3051
deinit_card(struct idt77252_dev *card)
3052
{
3053
	struct sk_buff *skb;
3054
	int i, j;
3055

3056
	if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3057
		printk("%s: SAR not yet initialized.\n", card->name);
3058
		return;
3059
	}
3060
	DIPRINTK("idt77252: deinitialize card %u\n", card->index);
3061

3062
	writel(0, SAR_REG_CFG);
3063

3064
	if (card->atmdev)
3065
		atm_dev_deregister(card->atmdev);
3066

3067
	for (i = 0; i < 4; i++) {
3068
		for (j = 0; j < FBQ_SIZE; j++) {
3069
			skb = card->sbpool[i].skb[j];
3070
			if (skb) {
3071
				dma_unmap_single(&card->pcidev->dev,
3072
						 IDT77252_PRV_PADDR(skb),
3073
						 (skb_end_pointer(skb) -
3074
						  skb->data),
3075
						 DMA_FROM_DEVICE);
3076
				card->sbpool[i].skb[j] = NULL;
3077
				dev_kfree_skb(skb);
3078
			}
3079
		}
3080
	}
3081

3082
	vfree(card->soft_tst);
3083

3084
	vfree(card->scd2vc);
3085

3086
	vfree(card->vcs);
3087

3088
	if (card->raw_cell_hnd) {
3089
		dma_free_coherent(&card->pcidev->dev, 2 * sizeof(u32),
3090
				  card->raw_cell_hnd, card->raw_cell_paddr);
3091
	}
3092

3093
	if (card->rsq.base) {
3094
		DIPRINTK("%s: Release RSQ ...\n", card->name);
3095
		deinit_rsq(card);
3096
	}
3097

3098
	if (card->tsq.base) {
3099
		DIPRINTK("%s: Release TSQ ...\n", card->name);
3100
		deinit_tsq(card);
3101
	}
3102

3103
	DIPRINTK("idt77252: Release IRQ.\n");
3104
	free_irq(card->pcidev->irq, card);
3105

3106
	for (i = 0; i < 4; i++) {
3107
		if (card->fbq[i])
3108
			iounmap(card->fbq[i]);
3109
	}
3110

3111
	if (card->membase)
3112
		iounmap(card->membase);
3113

3114
	clear_bit(IDT77252_BIT_INIT, &card->flags);
3115
	DIPRINTK("%s: Card deinitialized.\n", card->name);
3116
}
3117

3118

3119
static void init_sram(struct idt77252_dev *card)
3120
{
3121
	int i;
3122

3123
	for (i = 0; i < card->sramsize; i += 4)
3124
		write_sram(card, (i >> 2), 0);
3125

3126
	/* set SRAM layout for THIS card */
3127
	if (card->sramsize == (512 * 1024)) {
3128
		card->tct_base = SAR_SRAM_TCT_128_BASE;
3129
		card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1)
3130
		    / SAR_SRAM_TCT_SIZE;
3131
		card->rct_base = SAR_SRAM_RCT_128_BASE;
3132
		card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1)
3133
		    / SAR_SRAM_RCT_SIZE;
3134
		card->rt_base = SAR_SRAM_RT_128_BASE;
3135
		card->scd_base = SAR_SRAM_SCD_128_BASE;
3136
		card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1)
3137
		    / SAR_SRAM_SCD_SIZE;
3138
		card->tst[0] = SAR_SRAM_TST1_128_BASE;
3139
		card->tst[1] = SAR_SRAM_TST2_128_BASE;
3140
		card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1;
3141
		card->abrst_base = SAR_SRAM_ABRSTD_128_BASE;
3142
		card->abrst_size = SAR_ABRSTD_SIZE_8K;
3143
		card->fifo_base = SAR_SRAM_FIFO_128_BASE;
3144
		card->fifo_size = SAR_RXFD_SIZE_32K;
3145
	} else {
3146
		card->tct_base = SAR_SRAM_TCT_32_BASE;
3147
		card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1)
3148
		    / SAR_SRAM_TCT_SIZE;
3149
		card->rct_base = SAR_SRAM_RCT_32_BASE;
3150
		card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1)
3151
		    / SAR_SRAM_RCT_SIZE;
3152
		card->rt_base = SAR_SRAM_RT_32_BASE;
3153
		card->scd_base = SAR_SRAM_SCD_32_BASE;
3154
		card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1)
3155
		    / SAR_SRAM_SCD_SIZE;
3156
		card->tst[0] = SAR_SRAM_TST1_32_BASE;
3157
		card->tst[1] = SAR_SRAM_TST2_32_BASE;
3158
		card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1);
3159
		card->abrst_base = SAR_SRAM_ABRSTD_32_BASE;
3160
		card->abrst_size = SAR_ABRSTD_SIZE_1K;
3161
		card->fifo_base = SAR_SRAM_FIFO_32_BASE;
3162
		card->fifo_size = SAR_RXFD_SIZE_4K;
3163
	}
3164

3165
	/* Initialize TCT */
3166
	for (i = 0; i < card->tct_size; i++) {
3167
		write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0);
3168
		write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0);
3169
		write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0);
3170
		write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0);
3171
		write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0);
3172
		write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0);
3173
		write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0);
3174
		write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0);
3175
	}
3176

3177
	/* Initialize RCT */
3178
	for (i = 0; i < card->rct_size; i++) {
3179
		write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE,
3180
				    (u32) SAR_RCTE_RAWCELLINTEN);
3181
		write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1,
3182
				    (u32) 0);
3183
		write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2,
3184
				    (u32) 0);
3185
		write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3,
3186
				    (u32) 0xffffffff);
3187
	}
3188

3189
	writel((SAR_FBQ0_LOW << 28) | (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0);
3190
	writel((SAR_FBQ1_LOW << 28) | (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1);
3191
	writel((SAR_FBQ2_LOW << 28) | (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2);
3192
	writel((SAR_FBQ3_LOW << 28) | (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3);
3193

3194
	/* Initialize rate table  */
3195
	for (i = 0; i < 256; i++) {
3196
		write_sram(card, card->rt_base + i, log_to_rate[i]);
3197
	}
3198

3199
	for (i = 0; i < 128; i++) {
3200
		unsigned int tmp;
3201

3202
		tmp  = rate_to_log[(i << 2) + 0] << 0;
3203
		tmp |= rate_to_log[(i << 2) + 1] << 8;
3204
		tmp |= rate_to_log[(i << 2) + 2] << 16;
3205
		tmp |= rate_to_log[(i << 2) + 3] << 24;
3206
		write_sram(card, card->rt_base + 256 + i, tmp);
3207
	}
3208

3209
#if 0 /* Fill RDF and AIR tables. */
3210
	for (i = 0; i < 128; i++) {
3211
		unsigned int tmp;
3212

3213
		tmp = RDF[0][(i << 1) + 0] << 16;
3214
		tmp |= RDF[0][(i << 1) + 1] << 0;
3215
		write_sram(card, card->rt_base + 512 + i, tmp);
3216
	}
3217

3218
	for (i = 0; i < 128; i++) {
3219
		unsigned int tmp;
3220

3221
		tmp = AIR[0][(i << 1) + 0] << 16;
3222
		tmp |= AIR[0][(i << 1) + 1] << 0;
3223
		write_sram(card, card->rt_base + 640 + i, tmp);
3224
	}
3225
#endif
3226

3227
	IPRINTK("%s: initialize rate table ...\n", card->name);
3228
	writel(card->rt_base << 2, SAR_REG_RTBL);
3229

3230
	/* Initialize TSTs */
3231
	IPRINTK("%s: initialize TST ...\n", card->name);
3232
	card->tst_free = card->tst_size - 2;	/* last two are jumps */
3233

3234
	for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++)
3235
		write_sram(card, i, TSTE_OPC_VAR);
3236
	write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3237
	idt77252_sram_write_errors = 1;
3238
	write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3239
	idt77252_sram_write_errors = 0;
3240
	for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++)
3241
		write_sram(card, i, TSTE_OPC_VAR);
3242
	write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3243
	idt77252_sram_write_errors = 1;
3244
	write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3245
	idt77252_sram_write_errors = 0;
3246

3247
	card->tst_index = 0;
3248
	writel(card->tst[0] << 2, SAR_REG_TSTB);
3249

3250
	/* Initialize ABRSTD and Receive FIFO */
3251
	IPRINTK("%s: initialize ABRSTD ...\n", card->name);
3252
	writel(card->abrst_size | (card->abrst_base << 2),
3253
	       SAR_REG_ABRSTD);
3254

3255
	IPRINTK("%s: initialize receive fifo ...\n", card->name);
3256
	writel(card->fifo_size | (card->fifo_base << 2),
3257
	       SAR_REG_RXFD);
3258

3259
	IPRINTK("%s: SRAM initialization complete.\n", card->name);
3260
}
3261

3262
static int init_card(struct atm_dev *dev)
3263
{
3264
	struct idt77252_dev *card = dev->dev_data;
3265
	struct pci_dev *pcidev = card->pcidev;
3266
	unsigned long tmpl, modl;
3267
	unsigned int linkrate, rsvdcr;
3268
	unsigned int tst_entries;
3269
	struct net_device *tmp;
3270
	char tname[10];
3271

3272
	u32 size;
3273
	u_char pci_byte;
3274
	u32 conf;
3275
	int i, k;
3276

3277
	if (test_bit(IDT77252_BIT_INIT, &card->flags)) {
3278
		printk("Error: SAR already initialized.\n");
3279
		return -1;
3280
	}
3281

3282
/*****************************************************************/
3283
/*   P C I   C O N F I G U R A T I O N                           */
3284
/*****************************************************************/
3285

3286
	/* Set PCI Retry-Timeout and TRDY timeout */
3287
	IPRINTK("%s: Checking PCI retries.\n", card->name);
3288
	if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) {
3289
		printk("%s: can't read PCI retry timeout.\n", card->name);
3290
		deinit_card(card);
3291
		return -1;
3292
	}
3293
	if (pci_byte != 0) {
3294
		IPRINTK("%s: PCI retry timeout: %d, set to 0.\n",
3295
			card->name, pci_byte);
3296
		if (pci_write_config_byte(pcidev, 0x40, 0) != 0) {
3297
			printk("%s: can't set PCI retry timeout.\n",
3298
			       card->name);
3299
			deinit_card(card);
3300
			return -1;
3301
		}
3302
	}
3303
	IPRINTK("%s: Checking PCI TRDY.\n", card->name);
3304
	if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) {
3305
		printk("%s: can't read PCI TRDY timeout.\n", card->name);
3306
		deinit_card(card);
3307
		return -1;
3308
	}
3309
	if (pci_byte != 0) {
3310
		IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n",
3311
		        card->name, pci_byte);
3312
		if (pci_write_config_byte(pcidev, 0x41, 0) != 0) {
3313
			printk("%s: can't set PCI TRDY timeout.\n", card->name);
3314
			deinit_card(card);
3315
			return -1;
3316
		}
3317
	}
3318
	/* Reset Timer register */
3319
	if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) {
3320
		printk("%s: resetting timer overflow.\n", card->name);
3321
		writel(SAR_STAT_TMROF, SAR_REG_STAT);
3322
	}
3323
	IPRINTK("%s: Request IRQ ... ", card->name);
3324
	if (request_irq(pcidev->irq, idt77252_interrupt, IRQF_SHARED,
3325
			card->name, card) != 0) {
3326
		printk("%s: can't allocate IRQ.\n", card->name);
3327
		deinit_card(card);
3328
		return -1;
3329
	}
3330
	IPRINTK("got %d.\n", pcidev->irq);
3331

3332
/*****************************************************************/
3333
/*   C H E C K   A N D   I N I T   S R A M                       */
3334
/*****************************************************************/
3335

3336
	IPRINTK("%s: Initializing SRAM\n", card->name);
3337

3338
	/* preset size of connecton table, so that init_sram() knows about it */
3339
	conf =	SAR_CFG_TX_FIFO_SIZE_9 |	/* Use maximum fifo size */
3340
		SAR_CFG_RXSTQ_SIZE_8k |		/* Receive Status Queue is 8k */
3341
		SAR_CFG_IDLE_CLP |		/* Set CLP on idle cells */
3342
#ifndef ATM_IDT77252_SEND_IDLE
3343
		SAR_CFG_NO_IDLE |		/* Do not send idle cells */
3344
#endif
3345
		0;
3346

3347
	if (card->sramsize == (512 * 1024))
3348
		conf |= SAR_CFG_CNTBL_1k;
3349
	else
3350
		conf |= SAR_CFG_CNTBL_512;
3351

3352
	switch (vpibits) {
3353
	case 0:
3354
		conf |= SAR_CFG_VPVCS_0;
3355
		break;
3356
	default:
3357
	case 1:
3358
		conf |= SAR_CFG_VPVCS_1;
3359
		break;
3360
	case 2:
3361
		conf |= SAR_CFG_VPVCS_2;
3362
		break;
3363
	case 8:
3364
		conf |= SAR_CFG_VPVCS_8;
3365
		break;
3366
	}
3367

3368
	writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3369

3370
	init_sram(card);
3371

3372
/********************************************************************/
3373
/*  A L L O C   R A M   A N D   S E T   V A R I O U S   T H I N G S */
3374
/********************************************************************/
3375
	/* Initialize TSQ */
3376
	if (0 != init_tsq(card)) {
3377
		deinit_card(card);
3378
		return -1;
3379
	}
3380
	/* Initialize RSQ */
3381
	if (0 != init_rsq(card)) {
3382
		deinit_card(card);
3383
		return -1;
3384
	}
3385

3386
	card->vpibits = vpibits;
3387
	if (card->sramsize == (512 * 1024)) {
3388
		card->vcibits = 10 - card->vpibits;
3389
	} else {
3390
		card->vcibits = 9 - card->vpibits;
3391
	}
3392

3393
	card->vcimask = 0;
3394
	for (k = 0, i = 1; k < card->vcibits; k++) {
3395
		card->vcimask |= i;
3396
		i <<= 1;
3397
	}
3398

3399
	IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name);
3400
	writel(0, SAR_REG_VPM);
3401

3402
	/* Little Endian Order   */
3403
	writel(0, SAR_REG_GP);
3404

3405
	/* Initialize RAW Cell Handle Register  */
3406
	card->raw_cell_hnd = dma_alloc_coherent(&card->pcidev->dev,
3407
						2 * sizeof(u32),
3408
						&card->raw_cell_paddr,
3409
						GFP_KERNEL);
3410
	if (!card->raw_cell_hnd) {
3411
		printk("%s: memory allocation failure.\n", card->name);
3412
		deinit_card(card);
3413
		return -1;
3414
	}
3415
	writel(card->raw_cell_paddr, SAR_REG_RAWHND);
3416
	IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name,
3417
		card->raw_cell_hnd);
3418

3419
	size = sizeof(struct vc_map *) * card->tct_size;
3420
	IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size);
3421
	card->vcs = vzalloc(size);
3422
	if (!card->vcs) {
3423
		printk("%s: memory allocation failure.\n", card->name);
3424
		deinit_card(card);
3425
		return -1;
3426
	}
3427

3428
	size = sizeof(struct vc_map *) * card->scd_size;
3429
	IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n",
3430
	        card->name, size);
3431
	card->scd2vc = vzalloc(size);
3432
	if (!card->scd2vc) {
3433
		printk("%s: memory allocation failure.\n", card->name);
3434
		deinit_card(card);
3435
		return -1;
3436
	}
3437

3438
	size = sizeof(struct tst_info) * (card->tst_size - 2);
3439
	IPRINTK("%s: allocate %d byte for TST to VC mapping.\n",
3440
		card->name, size);
3441
	card->soft_tst = vmalloc(size);
3442
	if (!card->soft_tst) {
3443
		printk("%s: memory allocation failure.\n", card->name);
3444
		deinit_card(card);
3445
		return -1;
3446
	}
3447
	for (i = 0; i < card->tst_size - 2; i++) {
3448
		card->soft_tst[i].tste = TSTE_OPC_VAR;
3449
		card->soft_tst[i].vc = NULL;
3450
	}
3451

3452
	if (dev->phy == NULL) {
3453
		printk("%s: No LT device defined.\n", card->name);
3454
		deinit_card(card);
3455
		return -1;
3456
	}
3457
	if (dev->phy->ioctl == NULL) {
3458
		printk("%s: LT had no IOCTL function defined.\n", card->name);
3459
		deinit_card(card);
3460
		return -1;
3461
	}
3462

3463
#ifdef	CONFIG_ATM_IDT77252_USE_SUNI
3464
	/*
3465
	 * this is a jhs hack to get around special functionality in the
3466
	 * phy driver for the atecom hardware; the functionality doesn't
3467
	 * exist in the linux atm suni driver
3468
	 *
3469
	 * it isn't the right way to do things, but as the guy from NIST
3470
	 * said, talking about their measurement of the fine structure
3471
	 * constant, "it's good enough for government work."
3472
	 */
3473
	linkrate = 149760000;
3474
#endif
3475

3476
	card->link_pcr = (linkrate / 8 / 53);
3477
	printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n",
3478
	       card->name, linkrate, card->link_pcr);
3479

3480
#ifdef ATM_IDT77252_SEND_IDLE
3481
	card->utopia_pcr = card->link_pcr;
3482
#else
3483
	card->utopia_pcr = (160000000 / 8 / 54);
3484
#endif
3485

3486
	rsvdcr = 0;
3487
	if (card->utopia_pcr > card->link_pcr)
3488
		rsvdcr = card->utopia_pcr - card->link_pcr;
3489

3490
	tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2);
3491
	modl = tmpl % (unsigned long)card->utopia_pcr;
3492
	tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr);
3493
	if (modl)
3494
		tst_entries++;
3495
	card->tst_free -= tst_entries;
3496
	fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL);
3497

3498
#ifdef HAVE_EEPROM
3499
	idt77252_eeprom_init(card);
3500
	printk("%s: EEPROM: %02x:", card->name,
3501
		idt77252_eeprom_read_status(card));
3502

3503
	for (i = 0; i < 0x80; i++) {
3504
		printk(" %02x", 
3505
		idt77252_eeprom_read_byte(card, i)
3506
		);
3507
	}
3508
	printk("\n");
3509
#endif /* HAVE_EEPROM */
3510

3511
	/*
3512
	 * XXX: <hack>
3513
	 */
3514
	sprintf(tname, "eth%d", card->index);
3515
	tmp = dev_get_by_name(&init_net, tname);	/* jhs: was "tmp = dev_get(tname);" */
3516
	if (tmp) {
3517
		memcpy(card->atmdev->esi, tmp->dev_addr, 6);
3518
		dev_put(tmp);
3519
		printk("%s: ESI %pM\n", card->name, card->atmdev->esi);
3520
	}
3521
	/*
3522
	 * XXX: </hack>
3523
	 */
3524

3525
	/* Set Maximum Deficit Count for now. */
3526
	writel(0xffff, SAR_REG_MDFCT);
3527

3528
	set_bit(IDT77252_BIT_INIT, &card->flags);
3529

3530
	XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name);
3531
	return 0;
3532
}
3533

3534

3535
/*****************************************************************************/
3536
/*                                                                           */
3537
/* Probing of IDT77252 ABR SAR                                               */
3538
/*                                                                           */
3539
/*****************************************************************************/
3540

3541

3542
static int idt77252_preset(struct idt77252_dev *card)
3543
{
3544
	u16 pci_command;
3545

3546
/*****************************************************************/
3547
/*   P C I   C O N F I G U R A T I O N                           */
3548
/*****************************************************************/
3549

3550
	XPRINTK("%s: Enable PCI master and memory access for SAR.\n",
3551
		card->name);
3552
	if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) {
3553
		printk("%s: can't read PCI_COMMAND.\n", card->name);
3554
		deinit_card(card);
3555
		return -1;
3556
	}
3557
	if (!(pci_command & PCI_COMMAND_IO)) {
3558
		printk("%s: PCI_COMMAND: %04x (?)\n",
3559
		       card->name, pci_command);
3560
		deinit_card(card);
3561
		return (-1);
3562
	}
3563
	pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
3564
	if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) {
3565
		printk("%s: can't write PCI_COMMAND.\n", card->name);
3566
		deinit_card(card);
3567
		return -1;
3568
	}
3569
/*****************************************************************/
3570
/*   G E N E R I C   R E S E T                                   */
3571
/*****************************************************************/
3572

3573
	/* Software reset */
3574
	writel(SAR_CFG_SWRST, SAR_REG_CFG);
3575
	mdelay(1);
3576
	writel(0, SAR_REG_CFG);
3577

3578
	IPRINTK("%s: Software resetted.\n", card->name);
3579
	return 0;
3580
}
3581

3582

3583
static unsigned long probe_sram(struct idt77252_dev *card)
3584
{
3585
	u32 data, addr;
3586

3587
	writel(0, SAR_REG_DR0);
3588
	writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD);
3589

3590
	for (addr = 0x4000; addr < 0x80000; addr += 0x4000) {
3591
		writel(ATM_POISON, SAR_REG_DR0);
3592
		writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
3593

3594
		writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD);
3595
		data = readl(SAR_REG_DR0);
3596

3597
		if (data != 0)
3598
			break;
3599
	}
3600

3601
	return addr * sizeof(u32);
3602
}
3603

3604
static int idt77252_init_one(struct pci_dev *pcidev,
3605
			     const struct pci_device_id *id)
3606
{
3607
	static struct idt77252_dev **last = &idt77252_chain;
3608
	static int index = 0;
3609

3610
	unsigned long membase, srambase;
3611
	struct idt77252_dev *card;
3612
	struct atm_dev *dev;
3613
	int i, err;
3614

3615

3616
	if ((err = pci_enable_device(pcidev))) {
3617
		printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev));
3618
		return err;
3619
	}
3620

3621
	if ((err = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)))) {
3622
		printk("idt77252: can't enable DMA for PCI device at %s\n", pci_name(pcidev));
3623
		goto err_out_disable_pdev;
3624
	}
3625

3626
	card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL);
3627
	if (!card) {
3628
		printk("idt77252-%d: can't allocate private data\n", index);
3629
		err = -ENOMEM;
3630
		goto err_out_disable_pdev;
3631
	}
3632
	card->revision = pcidev->revision;
3633
	card->index = index;
3634
	card->pcidev = pcidev;
3635
	sprintf(card->name, "idt77252-%d", card->index);
3636

3637
	INIT_WORK(&card->tqueue, idt77252_softint);
3638

3639
	membase = pci_resource_start(pcidev, 1);
3640
	srambase = pci_resource_start(pcidev, 2);
3641

3642
	mutex_init(&card->mutex);
3643
	spin_lock_init(&card->cmd_lock);
3644
	spin_lock_init(&card->tst_lock);
3645

3646
	timer_setup(&card->tst_timer, tst_timer, 0);
3647

3648
	/* Do the I/O remapping... */
3649
	card->membase = ioremap(membase, 1024);
3650
	if (!card->membase) {
3651
		printk("%s: can't ioremap() membase\n", card->name);
3652
		err = -EIO;
3653
		goto err_out_free_card;
3654
	}
3655

3656
	if (idt77252_preset(card)) {
3657
		printk("%s: preset failed\n", card->name);
3658
		err = -EIO;
3659
		goto err_out_iounmap;
3660
	}
3661

3662
	dev = atm_dev_register("idt77252", &pcidev->dev, &idt77252_ops, -1,
3663
			       NULL);
3664
	if (!dev) {
3665
		printk("%s: can't register atm device\n", card->name);
3666
		err = -EIO;
3667
		goto err_out_iounmap;
3668
	}
3669
	dev->dev_data = card;
3670
	card->atmdev = dev;
3671

3672
#ifdef	CONFIG_ATM_IDT77252_USE_SUNI
3673
	suni_init(dev);
3674
	if (!dev->phy) {
3675
		printk("%s: can't init SUNI\n", card->name);
3676
		err = -EIO;
3677
		goto err_out_deinit_card;
3678
	}
3679
#endif	/* CONFIG_ATM_IDT77252_USE_SUNI */
3680

3681
	card->sramsize = probe_sram(card);
3682

3683
	for (i = 0; i < 4; i++) {
3684
		card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4);
3685
		if (!card->fbq[i]) {
3686
			printk("%s: can't ioremap() FBQ%d\n", card->name, i);
3687
			err = -EIO;
3688
			goto err_out_deinit_card;
3689
		}
3690
	}
3691

3692
	printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n",
3693
	       card->name, ((card->revision > 1) && (card->revision < 25)) ?
3694
	       'A' + card->revision - 1 : '?', membase, srambase,
3695
	       card->sramsize / 1024);
3696

3697
	if (init_card(dev)) {
3698
		printk("%s: init_card failed\n", card->name);
3699
		err = -EIO;
3700
		goto err_out_deinit_card;
3701
	}
3702

3703
	dev->ci_range.vpi_bits = card->vpibits;
3704
	dev->ci_range.vci_bits = card->vcibits;
3705
	dev->link_rate = card->link_pcr;
3706

3707
	if (dev->phy->start)
3708
		dev->phy->start(dev);
3709

3710
	if (idt77252_dev_open(card)) {
3711
		printk("%s: dev_open failed\n", card->name);
3712
		err = -EIO;
3713
		goto err_out_stop;
3714
	}
3715

3716
	*last = card;
3717
	last = &card->next;
3718
	index++;
3719

3720
	return 0;
3721

3722
err_out_stop:
3723
	if (dev->phy->stop)
3724
		dev->phy->stop(dev);
3725

3726
err_out_deinit_card:
3727
	deinit_card(card);
3728

3729
err_out_iounmap:
3730
	iounmap(card->membase);
3731

3732
err_out_free_card:
3733
	kfree(card);
3734

3735
err_out_disable_pdev:
3736
	pci_disable_device(pcidev);
3737
	return err;
3738
}
3739

3740
static const struct pci_device_id idt77252_pci_tbl[] =
3741
{
3742
	{ PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77252), 0 },
3743
	{ 0, }
3744
};
3745

3746
MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl);
3747

3748
static struct pci_driver idt77252_driver = {
3749
	.name		= "idt77252",
3750
	.id_table	= idt77252_pci_tbl,
3751
	.probe		= idt77252_init_one,
3752
};
3753

3754
static int __init idt77252_init(void)
3755
{
3756
	struct sk_buff *skb;
3757

3758
	printk("%s: at %p\n", __func__, idt77252_init);
3759
	BUILD_BUG_ON(sizeof(skb->cb) < sizeof(struct idt77252_skb_prv) + sizeof(struct atm_skb_data));
3760
	return pci_register_driver(&idt77252_driver);
3761
}
3762

3763
static void __exit idt77252_exit(void)
3764
{
3765
	struct idt77252_dev *card;
3766
	struct atm_dev *dev;
3767

3768
	pci_unregister_driver(&idt77252_driver);
3769

3770
	while (idt77252_chain) {
3771
		card = idt77252_chain;
3772
		dev = card->atmdev;
3773
		idt77252_chain = card->next;
3774
		timer_shutdown_sync(&card->tst_timer);
3775

3776
		if (dev->phy->stop)
3777
			dev->phy->stop(dev);
3778
		deinit_card(card);
3779
		pci_disable_device(card->pcidev);
3780
		kfree(card);
3781
	}
3782

3783
	DIPRINTK("idt77252: finished cleanup-module().\n");
3784
}
3785

3786
module_init(idt77252_init);
3787
module_exit(idt77252_exit);
3788

3789
MODULE_LICENSE("GPL");
3790

3791
module_param(vpibits, uint, 0);
3792
MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)");
3793
#ifdef CONFIG_ATM_IDT77252_DEBUG
3794
module_param(debug, ulong, 0644);
3795
MODULE_PARM_DESC(debug,   "debug bitmap, see drivers/atm/idt77252.h");
3796
#endif
3797

3798
MODULE_AUTHOR("Eddie C. Dost <[email protected]>");
3799
MODULE_DESCRIPTION("IDT77252 ABR SAR Driver");
3800

3801
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