CoCalc -- stm32

GitHub Repository: torvalds/linux
Path: blob/master/drivers/bus/stm32_rifsc.c
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// SPDX-License-Identifier: GPL-2.0-only
2
/*
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 * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
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 */
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/debugfs.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
19

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#include "stm32_firewall.h"
21

22
/*
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 * RIFSC offset register
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 */
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#define RIFSC_RISC_SECCFGR0		0x10
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#define RIFSC_RISC_PRIVCFGR0		0x30
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#define RIFSC_RISC_PER0_CIDCFGR		0x100
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#define RIFSC_RISC_PER0_SEMCR		0x104
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#define RIFSC_RISC_REG0_ACFGR		0x900
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#define RIFSC_RISC_REG3_AADDR		0x924
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#define RIFSC_RISC_HWCFGR2		0xFEC
32

33
/*
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 * SEMCR register
35
 */
36
#define SEMCR_MUTEX			BIT(0)
37

38
/*
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 * HWCFGR2 register
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 */
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#define HWCFGR2_CONF1_MASK		GENMASK(15, 0)
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#define HWCFGR2_CONF2_MASK		GENMASK(23, 16)
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#define HWCFGR2_CONF3_MASK		GENMASK(31, 24)
44

45
/*
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 * RIFSC miscellaneous
47
 */
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#define RIFSC_RISC_CFEN_MASK		BIT(0)
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#define RIFSC_RISC_SEM_EN_MASK		BIT(1)
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#define RIFSC_RISC_SCID_MASK		GENMASK(6, 4)
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#define RIFSC_RISC_SEML_SHIFT		16
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#define RIFSC_RISC_SEMWL_MASK		GENMASK(23, 16)
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#define RIFSC_RISC_PER_ID_MASK		GENMASK(31, 24)
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#define RIFSC_RISC_PERx_CID_MASK	(RIFSC_RISC_CFEN_MASK | \
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					 RIFSC_RISC_SEM_EN_MASK | \
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					 RIFSC_RISC_SCID_MASK | \
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					 RIFSC_RISC_SEMWL_MASK)
59

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#define IDS_PER_RISC_SEC_PRIV_REGS	32
61

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/* RIF miscellaneous */
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/*
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 * CIDCFGR register fields
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 */
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#define CIDCFGR_CFEN			BIT(0)
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#define CIDCFGR_SEMEN			BIT(1)
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#define CIDCFGR_SEMWL(x)		BIT(RIFSC_RISC_SEML_SHIFT + (x))
69

70
#define SEMWL_SHIFT			16
71

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/* Compartiment IDs */
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#define RIF_CID0			0x0
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#define RIF_CID1			0x1
75

76
#if defined(CONFIG_DEBUG_FS)
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#define RIFSC_RISUP_ENTRIES		128
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#define RIFSC_RIMU_ENTRIES		16
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#define RIFSC_RISAL_SUBREGIONS		2
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#define RIFSC_RISAL_GRANULARITY		8
81

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#define RIFSC_RIMC_ATTR0		0xC10
83

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#define RIFSC_RIMC_CIDSEL		BIT(2)
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#define RIFSC_RIMC_MCID_MASK		GENMASK(6, 4)
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#define RIFSC_RIMC_MSEC			BIT(8)
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#define RIFSC_RIMC_MPRIV		BIT(9)
88

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#define RIFSC_RISC_SRCID_MASK		GENMASK(6, 4)
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#define RIFSC_RISC_SRPRIV		BIT(9)
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#define RIFSC_RISC_SRSEC		BIT(8)
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#define RIFSC_RISC_SRRLOCK		BIT(1)
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#define RIFSC_RISC_SREN			BIT(0)
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#define RIFSC_RISC_SRLENGTH_MASK	GENMASK(27, 16)
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#define RIFSC_RISC_SRSTART_MASK		GENMASK(10, 0)
96

97
static const char *stm32mp21_rifsc_rimu_names[RIFSC_RIMU_ENTRIES] = {
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	"ETR",
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	"SDMMC1",
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	"SDMMC2",
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	"SDMMC3",
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	"OTG_HS",
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	"USBH",
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	"ETH1",
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	"ETH2",
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	"RESERVED",
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	"RESERVED",
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	"DCMIPP",
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	"LTDC_L1/L2",
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	"LTDC_L3",
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	"RESERVED",
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	"RESERVED",
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	"RESERVED",
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};
115

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static const char *stm32mp25_rifsc_rimu_names[RIFSC_RIMU_ENTRIES] = {
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	"ETR",
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	"SDMMC1",
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	"SDMMC2",
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	"SDMMC3",
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	"USB3DR",
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	"USBH",
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	"ETH1",
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	"ETH2",
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	"PCIE",
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	"GPU",
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	"DMCIPP",
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	"LTDC_L0/L1",
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	"LTDC_L2",
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	"LTDC_ROT",
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	"VDEC",
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	"VENC"
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};
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static const char *stm32mp21_rifsc_risup_names[RIFSC_RISUP_ENTRIES] = {
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	"TIM1",
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	"TIM2",
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	"TIM3",
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	"TIM4",
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	"TIM5",
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	"TIM6",
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	"TIM7",
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	"TIM8",
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	"TIM10",
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	"TIM11",
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	"TIM12",
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	"TIM13",
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	"TIM14",
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	"TIM15",
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	"TIM16",
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	"TIM17",
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	"RESERVED",
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	"LPTIM1",
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	"LPTIM2",
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	"LPTIM3",
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	"LPTIM4",
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	"LPTIM5",
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	"SPI1",
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	"SPI2",
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	"SPI3",
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	"SPI4",
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	"SPI5",
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	"SPI6",
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	"RESERVED",
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	"RESERVED",
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	"SPDIFRX",
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	"USART1",
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	"USART2",
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	"USART3",
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	"UART4",
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	"UART5",
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	"USART6",
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	"UART7",
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	"RESERVED",
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	"RESERVED",
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	"LPUART1",
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	"I2C1",
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	"I2C2",
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	"I2C3",
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	"RESERVED",
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	"RESERVED",
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	"RESERVED",
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	"RESERVED",
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	"RESERVED",
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	"SAI1",
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	"SAI2",
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	"SAI3",
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	"SAI4",
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	"RESERVED",
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	"MDF1",
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	"RESERVED",
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	"FDCAN",
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	"HDP",
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	"ADC1",
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	"ADC2",
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	"ETH1",
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	"ETH2",
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	"RESERVED",
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	"USBH",
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	"RESERVED",
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	"RESERVED",
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	"OTG_HS",
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	"DDRPERFM",
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	"RESERVED",
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	"RESERVED",
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	"RESERVED",
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	"RESERVED",
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	"RESERVED",
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	"STGEN",
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	"OCTOSPI1",
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	"RESERVED",
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	"SDMMC1",
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	"SDMMC2",
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	"SDMMC3",
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	"RESERVED",
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	"LTDC_CMN",
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	"RESERVED",
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	"RESERVED",
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	"RESERVED",
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	"RESERVED",
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	"RESERVED",
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	"CSI",
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	"DCMIPP",
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	"DCMI_PSSI",
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	"RESERVED",
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	"RESERVED",
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	"RESERVED",
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	"RNG1",
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	"RNG2",
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	"PKA",
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	"SAES",
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	"HASH1",
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	"HASH2",
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	"CRYP1",
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	"CRYP2",
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	"IWDG1",
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	"IWDG2",
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	"IWDG3",
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	"IWDG4",
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	"WWDG1",
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	"RESERVED",
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	"VREFBUF",
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	"DTS",
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	"RAMCFG",
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	"CRC",
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	"SERC",
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	"RESERVED",
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	"RESERVED",
249
	"RESERVED",
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	"I3C1",
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	"I3C2",
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	"I3C3",
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	"RESERVED",
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	"ICACHE_DCACHE",
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	"LTDC_L1L2",
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	"LTDC_L3",
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	"RESERVED",
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	"RESERVED",
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	"RESERVED",
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	"RESERVED",
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	"OTFDEC1",
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	"RESERVED",
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	"IAC",
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};
265

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static const char *stm32mp25_rifsc_risup_names[RIFSC_RISUP_ENTRIES] = {
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	"TIM1",
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	"TIM2",
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	"TIM3",
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	"TIM4",
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	"TIM5",
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	"TIM6",
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	"TIM7",
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	"TIM8",
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	"TIM10",
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	"TIM11",
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	"TIM12",
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	"TIM13",
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	"TIM14",
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	"TIM15",
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	"TIM16",
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	"TIM17",
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	"TIM20",
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	"LPTIM1",
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	"LPTIM2",
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	"LPTIM3",
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	"LPTIM4",
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	"LPTIM5",
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	"SPI1",
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	"SPI2",
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	"SPI3",
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	"SPI4",
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	"SPI5",
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	"SPI6",
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	"SPI7",
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	"SPI8",
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	"SPDIFRX",
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	"USART1",
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	"USART2",
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	"USART3",
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	"UART4",
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	"UART5",
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	"USART6",
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	"UART7",
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	"UART8",
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	"UART9",
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	"LPUART1",
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	"I2C1",
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	"I2C2",
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	"I2C3",
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	"I2C4",
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	"I2C5",
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	"I2C6",
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	"I2C7",
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	"I2C8",
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	"SAI1",
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	"SAI2",
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	"SAI3",
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	"SAI4",
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	"RESERVED",
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	"MDF1",
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	"ADF1",
323
	"FDCAN",
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	"HDP",
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	"ADC12",
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	"ADC3",
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	"ETH1",
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	"ETH2",
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	"RESERVED",
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	"USBH",
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	"RESERVED",
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	"RESERVED",
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	"USB3DR",
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	"COMBOPHY",
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	"PCIE",
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	"UCPD1",
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	"ETHSW_DEIP",
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	"ETHSW_ACM_CF",
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	"ETHSW_ACM_MSGBU",
340
	"STGEN",
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	"OCTOSPI1",
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	"OCTOSPI2",
343
	"SDMMC1",
344
	"SDMMC2",
345
	"SDMMC3",
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	"GPU",
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	"LTDC_CMN",
348
	"DSI_CMN",
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	"RESERVED",
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	"RESERVED",
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	"LVDS",
352
	"RESERVED",
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	"CSI",
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	"DCMIPP",
355
	"DCMI_PSSI",
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	"VDEC",
357
	"VENC",
358
	"RESERVED",
359
	"RNG",
360
	"PKA",
361
	"SAES",
362
	"HASH",
363
	"CRYP1",
364
	"CRYP2",
365
	"IWDG1",
366
	"IWDG2",
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	"IWDG3",
368
	"IWDG4",
369
	"IWDG5",
370
	"WWDG1",
371
	"WWDG2",
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	"RESERVED",
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	"VREFBUF",
374
	"DTS",
375
	"RAMCFG",
376
	"CRC",
377
	"SERC",
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	"OCTOSPIM",
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	"GICV2M",
380
	"RESERVED",
381
	"I3C1",
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	"I3C2",
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	"I3C3",
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	"I3C4",
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	"ICACHE_DCACHE",
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	"LTDC_L0L1",
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	"LTDC_L2",
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	"LTDC_ROT",
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	"DSI_TRIG",
390
	"DSI_RDFIFO",
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	"RESERVED",
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	"OTFDEC1",
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	"OTFDEC2",
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	"IAC",
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};
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struct rifsc_risup_debug_data {
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	char dev_name[15];
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	u8 dev_cid;
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	u8 dev_sem_cids;
400
	u8 dev_id;
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	bool dev_cid_filt_en;
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	bool dev_sem_en;
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	bool dev_priv;
404
	bool dev_sec;
405
};
406

407
struct rifsc_rimu_debug_data {
408
	char m_name[11];
409
	u8 m_cid;
410
	bool cidsel;
411
	bool m_sec;
412
	bool m_priv;
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};
414

415
struct rifsc_subreg_debug_data {
416
	bool sr_sec;
417
	bool sr_priv;
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	u8 sr_cid;
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	bool sr_rlock;
420
	bool sr_enable;
421
	u16 sr_start;
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	u16 sr_length;
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};
424

425
struct stm32_rifsc_resources_names {
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	const char **device_names;
427
	const char **initiator_names;
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};
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struct rifsc_dbg_private {
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	const struct stm32_rifsc_resources_names *res_names;
431
	void __iomem *mmio;
432
	unsigned int nb_risup;
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	unsigned int nb_rimu;
434
	unsigned int nb_risal;
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};
436

437
static const struct stm32_rifsc_resources_names rifsc_mp21_res_names = {
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	.device_names = stm32mp21_rifsc_risup_names,
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	.initiator_names = stm32mp21_rifsc_rimu_names,
440
};
441

442
static const struct stm32_rifsc_resources_names rifsc_mp25_res_names = {
443
	.device_names = stm32mp25_rifsc_risup_names,
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	.initiator_names = stm32mp25_rifsc_rimu_names,
445
};
446

447
static void stm32_rifsc_fill_rimu_dbg_entry(struct rifsc_dbg_private *rifsc,
448
					    struct rifsc_rimu_debug_data *dbg_entry, int i)
449
{
450
	const struct stm32_rifsc_resources_names *dbg_names = rifsc->res_names;
451
	u32 rimc_attr = readl_relaxed(rifsc->mmio + RIFSC_RIMC_ATTR0 + 0x4 * i);
452

453
	snprintf(dbg_entry->m_name, sizeof(dbg_entry->m_name), "%s", dbg_names->initiator_names[i]);
454
	dbg_entry->m_cid = FIELD_GET(RIFSC_RIMC_MCID_MASK, rimc_attr);
455
	dbg_entry->cidsel = rimc_attr & RIFSC_RIMC_CIDSEL;
456
	dbg_entry->m_sec = rimc_attr & RIFSC_RIMC_MSEC;
457
	dbg_entry->m_priv = rimc_attr & RIFSC_RIMC_MPRIV;
458
}
459

460
static void stm32_rifsc_fill_dev_dbg_entry(struct rifsc_dbg_private *rifsc,
461
					   struct rifsc_risup_debug_data *dbg_entry, int i)
462
{
463
	const struct stm32_rifsc_resources_names *dbg_names = rifsc->res_names;
464
	u32 cid_cfgr, sec_cfgr, priv_cfgr;
465
	u8 reg_id = i / IDS_PER_RISC_SEC_PRIV_REGS;
466
	u8 reg_offset = i % IDS_PER_RISC_SEC_PRIV_REGS;
467

468
	cid_cfgr = readl_relaxed(rifsc->mmio + RIFSC_RISC_PER0_CIDCFGR + 0x8 * i);
469
	sec_cfgr = readl_relaxed(rifsc->mmio + RIFSC_RISC_SECCFGR0 + 0x4 * reg_id);
470
	priv_cfgr = readl_relaxed(rifsc->mmio + RIFSC_RISC_PRIVCFGR0 + 0x4 * reg_id);
471

472
	snprintf(dbg_entry->dev_name, sizeof(dbg_entry->dev_name), "%s",
473
		 dbg_names->device_names[i]);
474
	dbg_entry->dev_id = i;
475
	dbg_entry->dev_cid_filt_en = cid_cfgr & CIDCFGR_CFEN;
476
	dbg_entry->dev_sem_en = cid_cfgr & CIDCFGR_SEMEN;
477
	dbg_entry->dev_cid = FIELD_GET(RIFSC_RISC_SCID_MASK, cid_cfgr);
478
	dbg_entry->dev_sem_cids = FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_cfgr);
479
	dbg_entry->dev_sec = sec_cfgr & BIT(reg_offset) ?  true : false;
480
	dbg_entry->dev_priv = priv_cfgr & BIT(reg_offset) ?  true : false;
481
}
482

483

484
static void stm32_rifsc_fill_subreg_dbg_entry(struct rifsc_dbg_private *rifsc,
485
					      struct rifsc_subreg_debug_data *dbg_entry, int i,
486
					      int j)
487
{
488
	u32 risc_xcfgr = readl_relaxed(rifsc->mmio + RIFSC_RISC_REG0_ACFGR + 0x10 * i + 0x8 * j);
489
	u32 risc_xaddr;
490

491
	dbg_entry->sr_sec = risc_xcfgr & RIFSC_RISC_SRSEC;
492
	dbg_entry->sr_priv = risc_xcfgr & RIFSC_RISC_SRPRIV;
493
	dbg_entry->sr_cid = FIELD_GET(RIFSC_RISC_SRCID_MASK, risc_xcfgr);
494
	dbg_entry->sr_rlock = risc_xcfgr & RIFSC_RISC_SRRLOCK;
495
	dbg_entry->sr_enable = risc_xcfgr & RIFSC_RISC_SREN;
496
	if (i == 2) {
497
		risc_xaddr = readl_relaxed(rifsc->mmio + RIFSC_RISC_REG3_AADDR + 0x8 * j);
498
		dbg_entry->sr_length = FIELD_GET(RIFSC_RISC_SRLENGTH_MASK, risc_xaddr);
499
		dbg_entry->sr_start = FIELD_GET(RIFSC_RISC_SRSTART_MASK, risc_xaddr);
500
	} else {
501
		dbg_entry->sr_start = 0;
502
		dbg_entry->sr_length = U16_MAX;
503
	}
504
}
505

506
static int stm32_rifsc_conf_dump_show(struct seq_file *s, void *data)
507
{
508
	struct rifsc_dbg_private *rifsc = (struct rifsc_dbg_private *)s->private;
509
	int i, j;
510

511
	seq_puts(s, "\n=============================================\n");
512
	seq_puts(s, "                 RIFSC dump\n");
513
	seq_puts(s, "=============================================\n\n");
514

515
	seq_puts(s, "\n=============================================\n");
516
	seq_puts(s, "                 RISUP dump\n");
517
	seq_puts(s, "=============================================\n");
518

519
	seq_printf(s, "\n| %-15s |", "Peripheral name");
520
	seq_puts(s, "| Firewall ID |");
521
	seq_puts(s, "| N/SECURE |");
522
	seq_puts(s, "| N/PRIVILEGED |");
523
	seq_puts(s, "| CID filtering |");
524
	seq_puts(s, "| Semaphore mode |");
525
	seq_puts(s, "| SCID |");
526
	seq_printf(s, "| %7s |\n", "SEMWL");
527

528
	for (i = 0; i < RIFSC_RISUP_ENTRIES && i < rifsc->nb_risup; i++) {
529
		struct rifsc_risup_debug_data d_dbg_entry;
530

531
		stm32_rifsc_fill_dev_dbg_entry(rifsc, &d_dbg_entry, i);
532

533
		seq_printf(s, "| %-15s |", d_dbg_entry.dev_name);
534
		seq_printf(s, "| %-11d |", d_dbg_entry.dev_id);
535
		seq_printf(s, "| %-8s |", d_dbg_entry.dev_sec ? "SEC" : "NSEC");
536
		seq_printf(s, "| %-12s |", d_dbg_entry.dev_priv ? "PRIV" : "NPRIV");
537
		seq_printf(s, "| %-13s |", str_enabled_disabled(d_dbg_entry.dev_cid_filt_en));
538
		seq_printf(s, "| %-14s |", str_enabled_disabled(d_dbg_entry.dev_sem_en));
539
		seq_printf(s, "| %-4d |", d_dbg_entry.dev_cid);
540
		seq_printf(s, "| %#-7x |\n", d_dbg_entry.dev_sem_cids);
541
	}
542

543
	seq_puts(s, "\n=============================================\n");
544
	seq_puts(s, "                  RIMU dump\n");
545
	seq_puts(s, "=============================================\n");
546

547
	seq_puts(s, "| RIMU's name |");
548
	seq_puts(s, "| CIDSEL |");
549
	seq_puts(s, "| MCID |");
550
	seq_puts(s, "| N/SECURE |");
551
	seq_puts(s, "| N/PRIVILEGED |\n");
552

553
	for (i = 0; i < RIFSC_RIMU_ENTRIES && rifsc->nb_rimu; i++) {
554
		struct rifsc_rimu_debug_data m_dbg_entry;
555

556
		stm32_rifsc_fill_rimu_dbg_entry(rifsc, &m_dbg_entry, i);
557

558
		seq_printf(s, "| %-11s |", m_dbg_entry.m_name);
559
		seq_printf(s, "| %-6s |", m_dbg_entry.cidsel ? "CIDSEL" : "");
560
		seq_printf(s, "| %-4d |", m_dbg_entry.m_cid);
561
		seq_printf(s, "| %-8s |", m_dbg_entry.m_sec ? "SEC" : "NSEC");
562
		seq_printf(s, "| %-12s |\n", m_dbg_entry.m_priv ? "PRIV" : "NPRIV");
563
	}
564

565
	if (rifsc->nb_risal > 0) {
566
		seq_puts(s, "\n=============================================\n");
567
		seq_puts(s, "                  RISAL dump\n");
568
		seq_puts(s, "=============================================\n");
569

570
		seq_puts(s, "| Memory  |");
571
		seq_puts(s, "| Subreg. |");
572
		seq_puts(s, "| N/SECURE |");
573
		seq_puts(s, "| N/PRIVILEGED |");
574
		seq_puts(s, "| Subreg. CID |");
575
		seq_puts(s, "| Resource lock |");
576
		seq_puts(s, "| Subreg. enable |");
577
		seq_puts(s, "| Subreg. start |");
578
		seq_puts(s, "|  Subreg. end  |\n");
579

580
		for (i = 0; i < rifsc->nb_risal; i++) {
581
			for (j = 0; j < RIFSC_RISAL_SUBREGIONS; j++) {
582
				struct rifsc_subreg_debug_data sr_dbg_entry;
583

584
				stm32_rifsc_fill_subreg_dbg_entry(rifsc, &sr_dbg_entry, i, j);
585

586
				seq_printf(s, "| LPSRAM%1d |", i + 1);
587
				seq_printf(s, "|    %1s    |", (j == 0) ? "A" : "B");
588
				seq_printf(s, "| %-8s |", sr_dbg_entry.sr_sec ? "SEC" : "NSEC");
589
				seq_printf(s, "| %-12s |", sr_dbg_entry.sr_priv ? "PRIV" : "NPRIV");
590
				seq_printf(s, "| 0x%-9x |", sr_dbg_entry.sr_cid);
591
				seq_printf(s, "| %-13s |",
592
					   sr_dbg_entry.sr_rlock ? "locked (1)" : "unlocked (0)");
593
				seq_printf(s, "| %-14s |",
594
					   str_enabled_disabled(sr_dbg_entry.sr_enable));
595
				seq_printf(s, "| 0x%-11x |", sr_dbg_entry.sr_start);
596
				seq_printf(s, "| 0x%-11x |\n", sr_dbg_entry.sr_start +
597
					   sr_dbg_entry.sr_length - 1);
598
			}
599
		}
600
	}
601

602
	return 0;
603
}
604
DEFINE_SHOW_ATTRIBUTE(stm32_rifsc_conf_dump);
605

606
static int stm32_rifsc_register_debugfs(struct stm32_firewall_controller *rifsc_controller,
607
					u32 nb_risup, u32 nb_rimu, u32 nb_risal)
608
{
609
	struct rifsc_dbg_private *rifsc_priv;
610
	struct dentry *root = NULL;
611

612
	rifsc_priv = devm_kzalloc(rifsc_controller->dev, sizeof(*rifsc_priv), GFP_KERNEL);
613
	if (!rifsc_priv)
614
		return -ENOMEM;
615

616
	rifsc_priv->mmio = rifsc_controller->mmio;
617
	rifsc_priv->nb_risup = nb_risup;
618
	rifsc_priv->nb_rimu = nb_rimu;
619
	rifsc_priv->nb_risal = nb_risal;
620
	rifsc_priv->res_names = of_device_get_match_data(rifsc_controller->dev);
621

622
	root = debugfs_lookup("stm32_firewall", NULL);
623
	if (!root)
624
		root = debugfs_create_dir("stm32_firewall", NULL);
625

626
	if (IS_ERR(root))
627
		return PTR_ERR(root);
628

629
	debugfs_create_file("rifsc", 0444, root, rifsc_priv, &stm32_rifsc_conf_dump_fops);
630

631
	return 0;
632
}
633
#endif /* defined(CONFIG_DEBUG_FS) */
634

635
static bool stm32_rifsc_is_semaphore_available(void __iomem *addr)
636
{
637
	return !(readl(addr) & SEMCR_MUTEX);
638
}
639

640
static int stm32_rif_acquire_semaphore(struct stm32_firewall_controller *stm32_firewall_controller,
641
				       int id)
642
{
643
	void __iomem *addr = stm32_firewall_controller->mmio + RIFSC_RISC_PER0_SEMCR + 0x8 * id;
644

645
	writel(SEMCR_MUTEX, addr);
646

647
	/* Check that CID1 has the semaphore */
648
	if (stm32_rifsc_is_semaphore_available(addr) ||
649
	    FIELD_GET(RIFSC_RISC_SCID_MASK, readl(addr)) != RIF_CID1)
650
		return -EACCES;
651

652
	return 0;
653
}
654

655
static void stm32_rif_release_semaphore(struct stm32_firewall_controller *stm32_firewall_controller,
656
					int id)
657
{
658
	void __iomem *addr = stm32_firewall_controller->mmio + RIFSC_RISC_PER0_SEMCR + 0x8 * id;
659

660
	if (stm32_rifsc_is_semaphore_available(addr))
661
		return;
662

663
	writel(SEMCR_MUTEX, addr);
664

665
	/* Ok if another compartment takes the semaphore before the check */
666
	WARN_ON(!stm32_rifsc_is_semaphore_available(addr) &&
667
		FIELD_GET(RIFSC_RISC_SCID_MASK, readl(addr)) == RIF_CID1);
668
}
669

670
static int stm32_rifsc_grant_access(struct stm32_firewall_controller *ctrl, u32 firewall_id)
671
{
672
	struct stm32_firewall_controller *rifsc_controller = ctrl;
673
	u32 reg_offset, reg_id, sec_reg_value, cid_reg_value;
674
	int rc;
675

676
	if (firewall_id >= rifsc_controller->max_entries) {
677
		dev_err(rifsc_controller->dev, "Invalid sys bus ID %u", firewall_id);
678
		return -EINVAL;
679
	}
680

681
	/*
682
	 * RIFSC_RISC_PRIVCFGRx and RIFSC_RISC_SECCFGRx both handle configuration access for
683
	 * 32 peripherals. On the other hand, there is one _RIFSC_RISC_PERx_CIDCFGR register
684
	 * per peripheral
685
	 */
686
	reg_id = firewall_id / IDS_PER_RISC_SEC_PRIV_REGS;
687
	reg_offset = firewall_id % IDS_PER_RISC_SEC_PRIV_REGS;
688
	sec_reg_value = readl(rifsc_controller->mmio + RIFSC_RISC_SECCFGR0 + 0x4 * reg_id);
689
	cid_reg_value = readl(rifsc_controller->mmio + RIFSC_RISC_PER0_CIDCFGR + 0x8 * firewall_id);
690

691
	/* First check conditions for semaphore mode, which doesn't take into account static CID. */
692
	if ((cid_reg_value & CIDCFGR_SEMEN) && (cid_reg_value & CIDCFGR_CFEN)) {
693
		if (cid_reg_value & BIT(RIF_CID1 + SEMWL_SHIFT)) {
694
			/* Static CID is irrelevant if semaphore mode */
695
			goto skip_cid_check;
696
		} else {
697
			dev_dbg(rifsc_controller->dev,
698
				"Invalid bus semaphore configuration: index %d\n", firewall_id);
699
			return -EACCES;
700
		}
701
	}
702

703
	/*
704
	 * Skip CID check if CID filtering isn't enabled or filtering is enabled on CID0, which
705
	 * corresponds to whatever CID.
706
	 */
707
	if (!(cid_reg_value & CIDCFGR_CFEN) ||
708
	    FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) == RIF_CID0)
709
		goto skip_cid_check;
710

711
	/* Coherency check with the CID configuration */
712
	if (FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) != RIF_CID1) {
713
		dev_dbg(rifsc_controller->dev, "Invalid CID configuration for peripheral: %d\n",
714
			firewall_id);
715
		return -EACCES;
716
	}
717

718
skip_cid_check:
719
	/* Check security configuration */
720
	if (sec_reg_value & BIT(reg_offset)) {
721
		dev_dbg(rifsc_controller->dev,
722
			"Invalid security configuration for peripheral: %d\n", firewall_id);
723
		return -EACCES;
724
	}
725

726
	/*
727
	 * If the peripheral is in semaphore mode, take the semaphore so that
728
	 * the CID1 has the ownership.
729
	 */
730
	if ((cid_reg_value & CIDCFGR_SEMEN) && (cid_reg_value & CIDCFGR_CFEN)) {
731
		rc = stm32_rif_acquire_semaphore(rifsc_controller, firewall_id);
732
		if (rc) {
733
			dev_err(rifsc_controller->dev,
734
				"Couldn't acquire semaphore for peripheral: %d\n", firewall_id);
735
			return rc;
736
		}
737
	}
738

739
	return 0;
740
}
741

742
static void stm32_rifsc_release_access(struct stm32_firewall_controller *ctrl, u32 firewall_id)
743
{
744
	stm32_rif_release_semaphore(ctrl, firewall_id);
745
}
746

747
static int stm32_rifsc_probe(struct platform_device *pdev)
748
{
749
	struct stm32_firewall_controller *rifsc_controller;
750
	struct device_node *np = pdev->dev.of_node;
751
	u32 nb_risup, nb_rimu, nb_risal;
752
	struct resource *res;
753
	void __iomem *mmio;
754
	int rc;
755

756
	rifsc_controller = devm_kzalloc(&pdev->dev, sizeof(*rifsc_controller), GFP_KERNEL);
757
	if (!rifsc_controller)
758
		return -ENOMEM;
759

760
	mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
761
	if (IS_ERR(mmio))
762
		return PTR_ERR(mmio);
763

764
	rifsc_controller->dev = &pdev->dev;
765
	rifsc_controller->mmio = mmio;
766
	rifsc_controller->name = dev_driver_string(rifsc_controller->dev);
767
	rifsc_controller->type = STM32_PERIPHERAL_FIREWALL | STM32_MEMORY_FIREWALL;
768
	rifsc_controller->grant_access = stm32_rifsc_grant_access;
769
	rifsc_controller->release_access = stm32_rifsc_release_access;
770

771
	/* Get number of RIFSC entries*/
772
	nb_risup = FIELD_GET(HWCFGR2_CONF1_MASK,
773
			     readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2));
774
	nb_rimu = FIELD_GET(HWCFGR2_CONF2_MASK,
775
			    readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2));
776
	nb_risal = FIELD_GET(HWCFGR2_CONF3_MASK,
777
			     readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2));
778
	/*
779
	 * On STM32MP21, RIFSC_RISC_HWCFGR2 shows an incorrect number of RISAL (NUM_RISAL is 3
780
	 * instead of 0). A software workaround is implemented using the st,mem-map property in the
781
	 * device tree. This property is absent or left empty if there is no RISAL.
782
	 */
783
	if (of_device_is_compatible(np, "st,stm32mp21-rifsc"))
784
		nb_risal = 0;
785
	rifsc_controller->max_entries = nb_risup + nb_rimu + nb_risal;
786

787
	platform_set_drvdata(pdev, rifsc_controller);
788

789
	rc = stm32_firewall_controller_register(rifsc_controller);
790
	if (rc) {
791
		dev_err(rifsc_controller->dev, "Couldn't register as a firewall controller: %d",
792
			rc);
793
		return rc;
794
	}
795

796
	rc = stm32_firewall_populate_bus(rifsc_controller);
797
	if (rc) {
798
		dev_err(rifsc_controller->dev, "Couldn't populate RIFSC bus: %d",
799
			rc);
800
		return rc;
801
	}
802

803
#if defined(CONFIG_DEBUG_FS)
804
	rc = stm32_rifsc_register_debugfs(rifsc_controller, nb_risup, nb_rimu, nb_risal);
805
	if (rc)
806
		return dev_err_probe(rifsc_controller->dev, rc, "Failed creating debugfs entry\n");
807
#endif
808

809
	/* Populate all allowed nodes */
810
	return of_platform_populate(np, NULL, NULL, &pdev->dev);
811
}
812

813
static const struct of_device_id stm32_rifsc_of_match[] = {
814
	{
815
		.compatible = "st,stm32mp25-rifsc",
816
#if defined(CONFIG_DEBUG_FS)
817
		.data = &rifsc_mp25_res_names,
818
#endif
819
	},
820
	{
821
		.compatible = "st,stm32mp21-rifsc",
822
#if defined(CONFIG_DEBUG_FS)
823
		.data = &rifsc_mp21_res_names,
824
#endif
825
	},
826
	{}
827
};
828
MODULE_DEVICE_TABLE(of, stm32_rifsc_of_match);
829

830
static struct platform_driver stm32_rifsc_driver = {
831
	.probe  = stm32_rifsc_probe,
832
	.driver = {
833
		.name = "stm32-rifsc",
834
		.of_match_table = stm32_rifsc_of_match,
835
	},
836
};
837
module_platform_driver(stm32_rifsc_driver);
838

839
MODULE_AUTHOR("Gatien Chevallier <[email protected]>");
840
MODULE_DESCRIPTION("STMicroelectronics RIFSC driver");
841
MODULE_LICENSE("GPL");
842

843
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