/* SPDX-License-Identifier: GPL-2.0-only */1/*2* Copyright (C) 2020 BAIKAL ELECTRONICS, JSC3*4* Baikal-T1 CCU PLL interface driver5*/6#ifndef __CLK_BT1_CCU_PLL_H__7#define __CLK_BT1_CCU_PLL_H__89#include <linux/clk-provider.h>10#include <linux/spinlock.h>11#include <linux/regmap.h>12#include <linux/bits.h>13#include <linux/of.h>1415/*16* CCU PLL private flags17* @CCU_PLL_BASIC: Basic PLL required by the kernel as early as possible.18*/19#define CCU_PLL_BASIC BIT(0)2021/*22* struct ccu_pll_init_data - CCU PLL initialization data23* @id: Clock private identifier.24* @name: Clocks name.25* @parent_name: Clocks parent name in a fw node.26* @base: PLL registers base address with respect to the sys_regs base.27* @sys_regs: Baikal-T1 System Controller registers map.28* @np: Pointer to the node describing the CCU PLLs.29* @flags: PLL clock flags.30* @features: PLL private features.31*/32struct ccu_pll_init_data {33unsigned int id;34const char *name;35const char *parent_name;36unsigned int base;37struct regmap *sys_regs;38struct device_node *np;39unsigned long flags;40unsigned long features;41};4243/*44* struct ccu_pll - CCU PLL descriptor45* @hw: clk_hw of the PLL.46* @id: Clock private identifier.47* @reg_ctl: PLL control register base.48* @reg_ctl1: PLL control1 register base.49* @sys_regs: Baikal-T1 System Controller registers map.50* @lock: PLL state change spin-lock.51*/52struct ccu_pll {53struct clk_hw hw;54unsigned int id;55unsigned int reg_ctl;56unsigned int reg_ctl1;57struct regmap *sys_regs;58spinlock_t lock;59};60#define to_ccu_pll(_hw) container_of(_hw, struct ccu_pll, hw)6162static inline struct clk_hw *ccu_pll_get_clk_hw(struct ccu_pll *pll)63{64return pll ? &pll->hw : NULL;65}6667struct ccu_pll *ccu_pll_hw_register(const struct ccu_pll_init_data *init);6869void ccu_pll_hw_unregister(struct ccu_pll *pll);7071#endif /* __CLK_BT1_CCU_PLL_H__ */727374