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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/drivers/clk/clk-fsl-flexspi.c
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// SPDX-License-Identifier: GPL-2.0-only

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/*

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 * Layerscape FlexSPI clock driver

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 *

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 * Copyright 2020 Michael Walle <[email protected]>

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 */

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#include <linux/clk-provider.h>

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#include <linux/io.h>

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#include <linux/module.h>

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#include <linux/platform_device.h>

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static const struct clk_div_table ls1028a_flexspi_divs[] = {

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	{ .val = 0, .div = 1, },

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	{ .val = 1, .div = 2, },

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	{ .val = 2, .div = 3, },

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	{ .val = 3, .div = 4, },

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	{ .val = 4, .div = 5, },

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	{ .val = 5, .div = 6, },

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	{ .val = 6, .div = 7, },

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	{ .val = 7, .div = 8, },

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	{ .val = 11, .div = 12, },

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	{ .val = 15, .div = 16, },

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	{ .val = 16, .div = 20, },

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	{ .val = 17, .div = 24, },

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	{ .val = 18, .div = 28, },

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	{ .val = 19, .div = 32, },

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	{ .val = 20, .div = 80, },

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	{}

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};

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static const struct clk_div_table lx2160a_flexspi_divs[] = {

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	{ .val = 1, .div = 2, },

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	{ .val = 3, .div = 4, },

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	{ .val = 5, .div = 6, },

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	{ .val = 7, .div = 8, },

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	{ .val = 11, .div = 12, },

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	{ .val = 15, .div = 16, },

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	{ .val = 16, .div = 20, },

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	{ .val = 17, .div = 24, },

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	{ .val = 18, .div = 28, },

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	{ .val = 19, .div = 32, },

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	{ .val = 20, .div = 80, },

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	{}

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};

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static int fsl_flexspi_clk_probe(struct platform_device *pdev)

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{

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	struct device *dev = &pdev->dev;

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	struct device_node *np = dev->of_node;

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	const char *clk_name = np->name;

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	const char *clk_parent;

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	struct resource *res;

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	void __iomem *reg;

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	struct clk_hw *hw;

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	const struct clk_div_table *divs;

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	divs = device_get_match_data(dev);

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	if (!divs)

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		return -ENOENT;

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	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

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	if (!res)

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		return -ENOENT;

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	/*

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	 * Can't use devm_ioremap_resource() or devm_of_iomap() because the

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	 * resource might already be taken by the parent device.

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	 */

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	reg = devm_ioremap(dev, res->start, resource_size(res));

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	if (!reg)

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		return -ENOMEM;

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	clk_parent = of_clk_get_parent_name(np, 0);

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	if (!clk_parent)

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		return -EINVAL;

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	of_property_read_string(np, "clock-output-names", &clk_name);

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	hw = devm_clk_hw_register_divider_table(dev, clk_name, clk_parent, 0,

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						reg, 0, 5, 0, divs, NULL);

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	if (IS_ERR(hw))

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		return PTR_ERR(hw);

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	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);

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}

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static const struct of_device_id fsl_flexspi_clk_dt_ids[] = {

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	{ .compatible = "fsl,ls1028a-flexspi-clk", .data = &ls1028a_flexspi_divs },

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	{ .compatible = "fsl,lx2160a-flexspi-clk", .data = &lx2160a_flexspi_divs },

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	{}

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};

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MODULE_DEVICE_TABLE(of, fsl_flexspi_clk_dt_ids);

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static struct platform_driver fsl_flexspi_clk_driver = {

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	.driver = {

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		.name = "fsl-flexspi-clk",

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		.of_match_table = fsl_flexspi_clk_dt_ids,

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	},

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	.probe = fsl_flexspi_clk_probe,

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};

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module_platform_driver(fsl_flexspi_clk_driver);

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MODULE_DESCRIPTION("FlexSPI clock driver for Layerscape SoCs");

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MODULE_AUTHOR("Michael Walle <[email protected]>");

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MODULE_LICENSE("GPL");

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