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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/drivers/crypto/ccree/cc_hash.h
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/* SPDX-License-Identifier: GPL-2.0 */

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/* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */

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/* \file cc_hash.h

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 * ARM CryptoCell Hash Crypto API

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 */

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#ifndef __CC_HASH_H__

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#define __CC_HASH_H__

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#include "cc_buffer_mgr.h"

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#define HMAC_IPAD_CONST	0x36363636

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#define HMAC_OPAD_CONST	0x5C5C5C5C

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#define HASH_LEN_SIZE_712 16

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#define HASH_LEN_SIZE_630 8

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#define HASH_MAX_LEN_SIZE HASH_LEN_SIZE_712

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#define CC_MAX_HASH_DIGEST_SIZE	SHA512_DIGEST_SIZE

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#define CC_MAX_HASH_BLCK_SIZE SHA512_BLOCK_SIZE

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#define XCBC_MAC_K1_OFFSET 0

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#define XCBC_MAC_K2_OFFSET 16

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#define XCBC_MAC_K3_OFFSET 32

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#define CC_EXPORT_MAGIC 0xC2EE1070U

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/* this struct was taken from drivers/crypto/nx/nx-aes-xcbc.c and it is used

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 * for xcbc/cmac statesize

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 */

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struct aeshash_state {

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	u8 state[AES_BLOCK_SIZE];

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	unsigned int count;

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	u8 buffer[AES_BLOCK_SIZE];

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};

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/* ahash state */

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struct ahash_req_ctx {

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	u8 buffers[2][CC_MAX_HASH_BLCK_SIZE] ____cacheline_aligned;

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	u8 digest_result_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;

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	u8 digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;

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	u8 opad_digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;

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	u8 digest_bytes_len[HASH_MAX_LEN_SIZE] ____cacheline_aligned;

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	struct async_gen_req_ctx gen_ctx ____cacheline_aligned;

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	enum cc_req_dma_buf_type data_dma_buf_type;

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	dma_addr_t opad_digest_dma_addr;

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	dma_addr_t digest_buff_dma_addr;

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	dma_addr_t digest_bytes_len_dma_addr;

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	dma_addr_t digest_result_dma_addr;

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	u32 buf_cnt[2];

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	u32 buff_index;

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	u32 xcbc_count; /* count xcbc update operatations */

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	struct scatterlist buff_sg[2];

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	struct scatterlist *curr_sg;

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	u32 in_nents;

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	u32 mlli_nents;

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	struct mlli_params mlli_params;

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};

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static inline u32 *cc_hash_buf_cnt(struct ahash_req_ctx *state)

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{

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	return &state->buf_cnt[state->buff_index];

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}

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static inline u8 *cc_hash_buf(struct ahash_req_ctx *state)

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{

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	return state->buffers[state->buff_index];

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}

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static inline u32 *cc_next_buf_cnt(struct ahash_req_ctx *state)

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{

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	return &state->buf_cnt[state->buff_index ^ 1];

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}

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static inline u8 *cc_next_buf(struct ahash_req_ctx *state)

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{

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	return state->buffers[state->buff_index ^ 1];

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}

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int cc_hash_alloc(struct cc_drvdata *drvdata);

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int cc_init_hash_sram(struct cc_drvdata *drvdata);

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int cc_hash_free(struct cc_drvdata *drvdata);

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/**

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 * cc_digest_len_addr() - Gets the initial digest length

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 *

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 * @drvdata: Associated device driver context

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 * @mode: The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256/SHA384/SHA512

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 *

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 * Return:

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 * Returns the address of the initial digest length in SRAM

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 */

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u32 cc_digest_len_addr(void *drvdata, u32 mode);

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/**

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 * cc_larval_digest_addr() - Gets the address of the initial digest in SRAM

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 * according to the given hash mode

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 *

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 * @drvdata: Associated device driver context

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 * @mode: The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256/SHA384/SHA512

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 *

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 * Return:

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 * The address of the initial digest in SRAM

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 */

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u32 cc_larval_digest_addr(void *drvdata, u32 mode);

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#endif /*__CC_HASH_H__*/

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