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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/drivers/crypto/ccree/cc_host_regs.h
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1
/* SPDX-License-Identifier: GPL-2.0 */

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/* Copyright (C) 2012-2019 ARM Limited or its affiliates. */

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#ifndef __CC_HOST_H__

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#define __CC_HOST_H__

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// --------------------------------------

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// BLOCK: HOST_P

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// --------------------------------------

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/* IRR */

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#define CC_HOST_IRR_REG_OFFSET	0xA00UL

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#define CC_HOST_IRR_REE_OP_ABORTED_AES_0_INT_BIT_SHIFT	0x1UL

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#define CC_HOST_IRR_REE_OP_ABORTED_AES_0_INT_BIT_SIZE	0x1UL

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#define CC_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SHIFT	0x2UL

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#define CC_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SIZE	0x1UL

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#define CC_HOST_IRR_REE_OP_ABORTED_AES_1_INT_BIT_SHIFT	0x3UL

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#define CC_HOST_IRR_REE_OP_ABORTED_AES_1_INT_BIT_SIZE	0x1UL

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#define CC_HOST_IRR_REE_OP_ABORTED_AES_2_INT_BIT_SHIFT	0x4UL

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#define CC_HOST_IRR_REE_OP_ABORTED_AES_2_INT_BIT_SIZE	0x1UL

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#define CC_HOST_IRR_REE_OP_ABORTED_AES_3_INT_BIT_SHIFT	0x5UL

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#define CC_HOST_IRR_REE_OP_ABORTED_AES_3_INT_BIT_SIZE	0x1UL

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#define CC_HOST_IRR_REE_OP_ABORTED_AES_4_INT_BIT_SHIFT	0x6UL

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#define CC_HOST_IRR_REE_OP_ABORTED_AES_4_INT_BIT_SIZE	0x1UL

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#define CC_HOST_IRR_REE_OP_ABORTED_AES_5_INT_BIT_SHIFT	0x7UL

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#define CC_HOST_IRR_REE_OP_ABORTED_AES_5_INT_BIT_SIZE	0x1UL

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#define CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT	0x8UL

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#define CC_HOST_IRR_AXI_ERR_INT_BIT_SIZE	0x1UL

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#define CC_HOST_IRR_REE_OP_ABORTED_AES_6_INT_BIT_SHIFT	0x9UL

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#define CC_HOST_IRR_REE_OP_ABORTED_AES_6_INT_BIT_SIZE	0x1UL

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#define CC_HOST_IRR_REE_OP_ABORTED_AES_7_INT_BIT_SHIFT	0xAUL

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#define CC_HOST_IRR_REE_OP_ABORTED_AES_7_INT_BIT_SIZE	0x1UL

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#define CC_HOST_IRR_GPR0_BIT_SHIFT	0xBUL

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#define CC_HOST_IRR_GPR0_BIT_SIZE	0x1UL

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#define CC_HOST_IRR_REE_OP_ABORTED_SM_0_INT_BIT_SHIFT	0xCUL

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#define CC_HOST_IRR_REE_OP_ABORTED_SM_0_INT_BIT_SIZE	0x1UL

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#define CC_HOST_IRR_REE_OP_ABORTED_SM_1_INT_BIT_SHIFT	0xDUL

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#define CC_HOST_IRR_REE_OP_ABORTED_SM_1_INT_BIT_SIZE	0x1UL

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#define CC_HOST_IRR_REE_OP_ABORTED_SM_2_INT_BIT_SHIFT	0xEUL

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#define CC_HOST_IRR_REE_OP_ABORTED_SM_2_INT_BIT_SIZE	0x1UL

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#define CC_HOST_IRR_REE_OP_ABORTED_SM_3_INT_BIT_SHIFT	0xFUL

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#define CC_HOST_IRR_REE_OP_ABORTED_SM_3_INT_BIT_SIZE	0x1UL

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#define CC_HOST_IRR_REE_OP_ABORTED_SM_4_INT_BIT_SHIFT	0x10UL

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#define CC_HOST_IRR_REE_OP_ABORTED_SM_4_INT_BIT_SIZE	0x1UL

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#define CC_HOST_IRR_REE_OP_ABORTED_SM_5_INT_BIT_SHIFT	0x11UL

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#define CC_HOST_IRR_REE_OP_ABORTED_SM_5_INT_BIT_SIZE	0x1UL

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#define CC_HOST_IRR_REE_OP_ABORTED_SM_6_INT_BIT_SHIFT	0x12UL

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#define CC_HOST_IRR_REE_OP_ABORTED_SM_6_INT_BIT_SIZE	0x1UL

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#define CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SHIFT	0x13UL

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#define CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SIZE	0x1UL

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#define CC_HOST_IRR_REE_OP_ABORTED_SM_7_INT_BIT_SHIFT	0x14UL

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#define CC_HOST_IRR_REE_OP_ABORTED_SM_7_INT_BIT_SIZE	0x1UL

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#define CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT	0x17UL

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#define CC_HOST_IRR_AXIM_COMP_INT_BIT_SIZE	0x1UL

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#define CC_HOST_SEP_SRAM_THRESHOLD_REG_OFFSET	0xA10UL

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#define CC_HOST_SEP_SRAM_THRESHOLD_VALUE_BIT_SHIFT	0x0UL

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#define CC_HOST_SEP_SRAM_THRESHOLD_VALUE_BIT_SIZE	0xCUL

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/* IMR */

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#define CC_HOST_IMR_REG_OFFSET	0x0A04UL

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#define CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SHIFT	0x1UL

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#define CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SIZE	0x1UL

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#define CC_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SHIFT	0x2UL

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#define CC_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SIZE	0x1UL

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#define CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SHIFT	0x3UL

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#define CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SIZE	0x1UL

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#define CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SHIFT	0x4UL

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#define CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SIZE	0x1UL

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#define CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SHIFT	0x5UL

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#define CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SIZE	0x1UL

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#define CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SHIFT	0x6UL

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#define CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SIZE	0x1UL

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#define CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SHIFT	0x7UL

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#define CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SIZE	0x1UL

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#define CC_HOST_IMR_AXI_ERR_MASK_BIT_SHIFT	0x8UL

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#define CC_HOST_IMR_AXI_ERR_MASK_BIT_SIZE	0x1UL

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#define CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SHIFT	0x9UL

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#define CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SIZE	0x1UL

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#define CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SHIFT	0xAUL

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#define CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SIZE	0x1UL

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#define CC_HOST_IMR_GPR0_BIT_SHIFT	0xBUL

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#define CC_HOST_IMR_GPR0_BIT_SIZE	0x1UL

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#define CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SHIFT	0xCUL

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#define CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SIZE	0x1UL

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#define CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SHIFT	0xDUL

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#define CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SIZE	0x1UL

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#define CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SHIFT	0xEUL

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#define CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SIZE	0x1UL

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#define CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SHIFT	0xFUL

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#define CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SIZE	0x1UL

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#define CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SHIFT	0x10UL

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#define CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SIZE	0x1UL

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#define CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SHIFT	0x11UL

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#define CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SIZE	0x1UL

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#define CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SHIFT	0x12UL

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#define CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SIZE	0x1UL

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#define CC_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SHIFT	0x13UL

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#define CC_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SIZE	0x1UL

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#define CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SHIFT	0x14UL

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#define CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SIZE	0x1UL

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#define CC_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SHIFT	0x17UL

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#define CC_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SIZE	0x1UL

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/* ICR */

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#define CC_HOST_ICR_REG_OFFSET	0xA08UL

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#define CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SHIFT	0x2UL

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#define CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SIZE	0x1UL

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#define CC_HOST_ICR_AXI_ERR_CLEAR_BIT_SHIFT	0x8UL

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#define CC_HOST_ICR_AXI_ERR_CLEAR_BIT_SIZE	0x1UL

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#define CC_HOST_ICR_GPR_INT_CLEAR_BIT_SHIFT	0xBUL

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#define CC_HOST_ICR_GPR_INT_CLEAR_BIT_SIZE	0x1UL

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#define CC_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SHIFT	0x13UL

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#define CC_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SIZE	0x1UL

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#define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SHIFT	0x17UL

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#define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SIZE	0x1UL

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#define CC_NVM_IS_IDLE_REG_OFFSET       0x0A10UL

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#define CC_NVM_IS_IDLE_VALUE_BIT_SHIFT  0x0UL

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#define CC_NVM_IS_IDLE_VALUE_BIT_SIZE   0x1UL

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#define CC_SECURITY_DISABLED_REG_OFFSET		0x0A1CUL

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#define CC_SECURITY_DISABLED_VALUE_BIT_SHIFT	0x0UL

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#define CC_SECURITY_DISABLED_VALUE_BIT_SIZE	0x1UL

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#define CC_HOST_SIGNATURE_712_REG_OFFSET	0xA24UL

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#define CC_HOST_SIGNATURE_630_REG_OFFSET	0xAC8UL

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#define CC_HOST_SIGNATURE_VALUE_BIT_SHIFT	0x0UL

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#define CC_HOST_SIGNATURE_VALUE_BIT_SIZE	0x20UL

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#define CC_HOST_BOOT_REG_OFFSET	0xA28UL

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#define CC_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SHIFT	0x0UL

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#define CC_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SHIFT	0x1UL

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#define CC_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SHIFT	0x2UL

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#define CC_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SHIFT	0x3UL

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#define CC_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SHIFT	0x5UL

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#define CC_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SHIFT	0x6UL

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#define CC_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SIZE	0x3UL

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#define CC_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SHIFT	0x9UL

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#define CC_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SHIFT	0xAUL

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#define CC_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SHIFT	0xBUL

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#define CC_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SHIFT	0xCUL

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#define CC_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SHIFT	0xDUL

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#define CC_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SHIFT	0xEUL

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#define CC_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SHIFT	0xFUL

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#define CC_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SHIFT	0x10UL

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#define CC_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SHIFT	0x11UL

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#define CC_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SHIFT	0x12UL

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#define CC_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SHIFT	0x13UL

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#define CC_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SHIFT	0x14UL

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#define CC_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SHIFT	0x15UL

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#define CC_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SHIFT	0x16UL

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#define CC_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SHIFT	0x17UL

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#define CC_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SHIFT	0x18UL

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#define CC_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SHIFT	0x19UL

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#define CC_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SHIFT	0x1AUL

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#define CC_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SHIFT	0x1BUL

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#define CC_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SHIFT	0x1CUL

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#define CC_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SHIFT	0x1DUL

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#define CC_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SHIFT	0x1EUL

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#define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SIZE	0x1UL

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#define CC_HOST_VERSION_712_REG_OFFSET	0xA40UL

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#define CC_HOST_VERSION_630_REG_OFFSET	0xAD8UL

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#define CC_HOST_VERSION_VALUE_BIT_SHIFT	0x0UL

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#define CC_HOST_VERSION_VALUE_BIT_SIZE	0x20UL

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#define CC_HOST_KFDE0_VALID_REG_OFFSET	0xA60UL

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#define CC_HOST_KFDE0_VALID_VALUE_BIT_SHIFT	0x0UL

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#define CC_HOST_KFDE0_VALID_VALUE_BIT_SIZE	0x1UL

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#define CC_HOST_KFDE1_VALID_REG_OFFSET	0xA64UL

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#define CC_HOST_KFDE1_VALID_VALUE_BIT_SHIFT	0x0UL

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#define CC_HOST_KFDE1_VALID_VALUE_BIT_SIZE	0x1UL

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#define CC_HOST_KFDE2_VALID_REG_OFFSET	0xA68UL

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#define CC_HOST_KFDE2_VALID_VALUE_BIT_SHIFT	0x0UL

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#define CC_HOST_KFDE2_VALID_VALUE_BIT_SIZE	0x1UL

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#define CC_HOST_KFDE3_VALID_REG_OFFSET	0xA6CUL

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#define CC_HOST_KFDE3_VALID_VALUE_BIT_SHIFT	0x0UL

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#define CC_HOST_KFDE3_VALID_VALUE_BIT_SIZE	0x1UL

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#define CC_HOST_GPR0_REG_OFFSET	0xA70UL

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#define CC_HOST_GPR0_VALUE_BIT_SHIFT	0x0UL

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#define CC_HOST_GPR0_VALUE_BIT_SIZE	0x20UL

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#define CC_GPR_HOST_REG_OFFSET	0xA74UL

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#define CC_GPR_HOST_VALUE_BIT_SHIFT	0x0UL

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#define CC_GPR_HOST_VALUE_BIT_SIZE	0x20UL

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#define CC_HOST_POWER_DOWN_EN_REG_OFFSET	0xA78UL

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#define CC_HOST_POWER_DOWN_EN_VALUE_BIT_SHIFT	0x0UL

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#define CC_HOST_POWER_DOWN_EN_VALUE_BIT_SIZE	0x1UL

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#define CC_HOST_REMOVE_INPUT_PINS_REG_OFFSET	0x0A7CUL

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#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_ENGINE_BIT_SHIFT	0x0UL

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#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_ENGINE_BIT_SIZE	0x1UL

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#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_MAC_ENGINE_BIT_SHIFT	0x1UL

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#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_MAC_ENGINE_BIT_SIZE	0x1UL

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#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_GHASH_ENGINE_BIT_SHIFT	0x2UL

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#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_GHASH_ENGINE_BIT_SIZE	0x1UL

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#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_DES_ENGINE_BIT_SHIFT	0x3UL

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#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_DES_ENGINE_BIT_SIZE	0x1UL

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#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_HASH_ENGINE_BIT_SHIFT	0x4UL

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#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_HASH_ENGINE_BIT_SIZE	0x1UL

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#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM3_ENGINE_BIT_SHIFT	0x5UL

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#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM3_ENGINE_BIT_SIZE	0x1UL

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#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM4_ENGINE_BIT_SHIFT	0x6UL

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#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM4_ENGINE_BIT_SIZE	0x1UL

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#define CC_HOST_REMOVE_INPUT_PINS_OTP_DISCONNECTED_BIT_SHIFT	0x7UL

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#define CC_HOST_REMOVE_INPUT_PINS_OTP_DISCONNECTED_BIT_SIZE	0x1UL

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// --------------------------------------

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// BLOCK: ID_REGISTERS

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// --------------------------------------

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#define CC_PERIPHERAL_ID_4_REG_OFFSET	0x0FD0UL

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#define CC_PERIPHERAL_ID_4_VALUE_BIT_SHIFT	0x0UL

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#define CC_PERIPHERAL_ID_4_VALUE_BIT_SIZE	0x4UL

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#define CC_PIDRESERVED0_REG_OFFSET	0x0FD4UL

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#define CC_PIDRESERVED1_REG_OFFSET	0x0FD8UL

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#define CC_PIDRESERVED2_REG_OFFSET	0x0FDCUL

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#define CC_PERIPHERAL_ID_0_REG_OFFSET	0x0FE0UL

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#define CC_PERIPHERAL_ID_0_VALUE_BIT_SHIFT	0x0UL

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#define CC_PERIPHERAL_ID_0_VALUE_BIT_SIZE	0x8UL

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#define CC_PERIPHERAL_ID_1_REG_OFFSET	0x0FE4UL

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#define CC_PERIPHERAL_ID_1_PART_1_BIT_SHIFT	0x0UL

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#define CC_PERIPHERAL_ID_1_PART_1_BIT_SIZE	0x4UL

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#define CC_PERIPHERAL_ID_1_DES_0_JEP106_BIT_SHIFT	0x4UL

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#define CC_PERIPHERAL_ID_1_DES_0_JEP106_BIT_SIZE	0x4UL

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#define CC_PERIPHERAL_ID_2_REG_OFFSET	0x0FE8UL

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#define CC_PERIPHERAL_ID_2_DES_1_JEP106_BIT_SHIFT	0x0UL

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#define CC_PERIPHERAL_ID_2_DES_1_JEP106_BIT_SIZE	0x3UL

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#define CC_PERIPHERAL_ID_2_JEDEC_BIT_SHIFT	0x3UL

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#define CC_PERIPHERAL_ID_2_JEDEC_BIT_SIZE	0x1UL

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#define CC_PERIPHERAL_ID_2_REVISION_BIT_SHIFT	0x4UL

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#define CC_PERIPHERAL_ID_2_REVISION_BIT_SIZE	0x4UL

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#define CC_PERIPHERAL_ID_3_REG_OFFSET	0x0FECUL

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#define CC_PERIPHERAL_ID_3_CMOD_BIT_SHIFT	0x0UL

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#define CC_PERIPHERAL_ID_3_CMOD_BIT_SIZE	0x4UL

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#define CC_PERIPHERAL_ID_3_REVAND_BIT_SHIFT	0x4UL

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#define CC_PERIPHERAL_ID_3_REVAND_BIT_SIZE	0x4UL

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#define CC_COMPONENT_ID_0_REG_OFFSET	0x0FF0UL

256
#define CC_COMPONENT_ID_0_VALUE_BIT_SHIFT	0x0UL

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#define CC_COMPONENT_ID_0_VALUE_BIT_SIZE	0x8UL

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#define CC_COMPONENT_ID_1_REG_OFFSET	0x0FF4UL

259
#define CC_COMPONENT_ID_1_PRMBL_1_BIT_SHIFT	0x0UL

260
#define CC_COMPONENT_ID_1_PRMBL_1_BIT_SIZE	0x4UL

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#define CC_COMPONENT_ID_1_CLASS_BIT_SHIFT	0x4UL

262
#define CC_COMPONENT_ID_1_CLASS_BIT_SIZE	0x4UL

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#define CC_COMPONENT_ID_2_REG_OFFSET	0x0FF8UL

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#define CC_COMPONENT_ID_2_VALUE_BIT_SHIFT	0x0UL

265
#define CC_COMPONENT_ID_2_VALUE_BIT_SIZE	0x8UL

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#define CC_COMPONENT_ID_3_REG_OFFSET	0x0FFCUL

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#define CC_COMPONENT_ID_3_VALUE_BIT_SHIFT	0x0UL

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#define CC_COMPONENT_ID_3_VALUE_BIT_SIZE	0x8UL

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// --------------------------------------

270
// BLOCK: HOST_SRAM

271
// --------------------------------------

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#define CC_SRAM_DATA_REG_OFFSET	0xF00UL

273
#define CC_SRAM_DATA_VALUE_BIT_SHIFT	0x0UL

274
#define CC_SRAM_DATA_VALUE_BIT_SIZE	0x20UL

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#define CC_SRAM_ADDR_REG_OFFSET	0xF04UL

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#define CC_SRAM_ADDR_VALUE_BIT_SHIFT	0x0UL

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#define CC_SRAM_ADDR_VALUE_BIT_SIZE	0xFUL

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#define CC_SRAM_DATA_READY_REG_OFFSET	0xF08UL

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#define CC_SRAM_DATA_READY_VALUE_BIT_SHIFT	0x0UL

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#define CC_SRAM_DATA_READY_VALUE_BIT_SIZE	0x1UL

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#endif //__CC_HOST_H__

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