Path: blob/master/drivers/crypto/marvell/octeontx2/cn10k_cpt.h
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/* SPDX-License-Identifier: GPL-2.0-only1* Copyright (C) 2021 Marvell.2*/3#ifndef __CN10K_CPT_H4#define __CN10K_CPT_H56#include "otx2_cpt_common.h"7#include "otx2_cptpf.h"8#include "otx2_cptvf.h"910#define CN10K_CPT_HW_CTX_SIZE 2561112union cn10k_cpt_hw_ctx {13u64 u;14struct {15u64 reserved_0_47:48;16u64 ctx_push_sz:7;17u64 reserved_55:1;18u64 ctx_hdr_sz:2;19u64 aop_valid:1;20u64 reserved_59:1;21u64 ctx_sz:4;22} w0;23};2425struct cn10k_cpt_errata_ctx {26union cn10k_cpt_hw_ctx *hw_ctx;27u64 cptr_dma;28};2930static inline u8 cn10k_cpt_get_compcode(union otx2_cpt_res_s *result)31{32return ((struct cn10k_cpt_res_s *)result)->compcode;33}3435static inline u8 cn10k_cpt_get_uc_compcode(union otx2_cpt_res_s *result)36{37return ((struct cn10k_cpt_res_s *)result)->uc_compcode;38}3940static inline u8 otx2_cpt_get_compcode(union otx2_cpt_res_s *result)41{42return ((struct cn9k_cpt_res_s *)result)->compcode;43}4445static inline u8 otx2_cpt_get_uc_compcode(union otx2_cpt_res_s *result)46{47return ((struct cn9k_cpt_res_s *)result)->uc_compcode;48}4950int cn10k_cptpf_lmtst_init(struct otx2_cptpf_dev *cptpf);51int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf);52void cn10k_cpt_lmtst_free(struct pci_dev *pdev, struct otx2_cptlfs_info *lfs);53void cn10k_cpt_ctx_flush(struct pci_dev *pdev, u64 cptr, bool inval);54int cn10k_cpt_hw_ctx_init(struct pci_dev *pdev,55struct cn10k_cpt_errata_ctx *er_ctx);56void cn10k_cpt_hw_ctx_clear(struct pci_dev *pdev,57struct cn10k_cpt_errata_ctx *er_ctx);58void cn10k_cpt_hw_ctx_set(union cn10k_cpt_hw_ctx *hctx, u16 ctx_sz);59void cptvf_hw_ops_get(struct otx2_cptvf_dev *cptvf);6061#endif /* __CN10K_CPTLF_H */626364