Path: blob/master/drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c
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// SPDX-License-Identifier: GPL-2.0-only1/* Copyright (C) 2020 Marvell. */23#include "otx2_cpt_common.h"4#include "otx2_cptlf.h"56int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pdev)7{8int ret;910otx2_mbox_msg_send(mbox, 0);11ret = otx2_mbox_wait_for_rsp(mbox, 0);12if (ret == -EIO) {13dev_err(&pdev->dev, "RVU MBOX timeout.\n");14return ret;15} else if (ret) {16dev_err(&pdev->dev, "RVU MBOX error: %d.\n", ret);17return -EFAULT;18}19return ret;20}21EXPORT_SYMBOL_NS_GPL(otx2_cpt_send_mbox_msg, "CRYPTO_DEV_OCTEONTX2_CPT");2223int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev)24{25struct mbox_msghdr *req;2627req = otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),28sizeof(struct ready_msg_rsp));29if (req == NULL) {30dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");31return -EFAULT;32}33req->id = MBOX_MSG_READY;34req->sig = OTX2_MBOX_REQ_SIG;35req->pcifunc = 0;3637return otx2_cpt_send_mbox_msg(mbox, pdev);38}39EXPORT_SYMBOL_NS_GPL(otx2_cpt_send_ready_msg, "CRYPTO_DEV_OCTEONTX2_CPT");4041int otx2_cpt_send_af_reg_requests(struct otx2_mbox *mbox, struct pci_dev *pdev)42{43return otx2_cpt_send_mbox_msg(mbox, pdev);44}45EXPORT_SYMBOL_NS_GPL(otx2_cpt_send_af_reg_requests, "CRYPTO_DEV_OCTEONTX2_CPT");4647static int otx2_cpt_add_read_af_reg(struct otx2_mbox *mbox,48struct pci_dev *pdev, u64 reg,49u64 *val, int blkaddr)50{51struct cpt_rd_wr_reg_msg *reg_msg;5253reg_msg = (struct cpt_rd_wr_reg_msg *)54otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*reg_msg),55sizeof(*reg_msg));56if (reg_msg == NULL) {57dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");58return -EFAULT;59}6061reg_msg->hdr.id = MBOX_MSG_CPT_RD_WR_REGISTER;62reg_msg->hdr.sig = OTX2_MBOX_REQ_SIG;63reg_msg->hdr.pcifunc = 0;6465reg_msg->is_write = 0;66reg_msg->reg_offset = reg;67reg_msg->ret_val = val;68reg_msg->blkaddr = blkaddr;6970return 0;71}7273int otx2_cpt_add_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,74u64 reg, u64 val, int blkaddr)75{76struct cpt_rd_wr_reg_msg *reg_msg;7778reg_msg = (struct cpt_rd_wr_reg_msg *)79otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*reg_msg),80sizeof(*reg_msg));81if (reg_msg == NULL) {82dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");83return -EFAULT;84}8586reg_msg->hdr.id = MBOX_MSG_CPT_RD_WR_REGISTER;87reg_msg->hdr.sig = OTX2_MBOX_REQ_SIG;88reg_msg->hdr.pcifunc = 0;8990reg_msg->is_write = 1;91reg_msg->reg_offset = reg;92reg_msg->val = val;93reg_msg->blkaddr = blkaddr;9495return 0;96}97EXPORT_SYMBOL_NS_GPL(otx2_cpt_add_write_af_reg, "CRYPTO_DEV_OCTEONTX2_CPT");9899int otx2_cpt_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,100u64 reg, u64 *val, int blkaddr)101{102int ret;103104ret = otx2_cpt_add_read_af_reg(mbox, pdev, reg, val, blkaddr);105if (ret)106return ret;107108return otx2_cpt_send_mbox_msg(mbox, pdev);109}110EXPORT_SYMBOL_NS_GPL(otx2_cpt_read_af_reg, "CRYPTO_DEV_OCTEONTX2_CPT");111112int otx2_cpt_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,113u64 reg, u64 val, int blkaddr)114{115int ret;116117ret = otx2_cpt_add_write_af_reg(mbox, pdev, reg, val, blkaddr);118if (ret)119return ret;120121return otx2_cpt_send_mbox_msg(mbox, pdev);122}123EXPORT_SYMBOL_NS_GPL(otx2_cpt_write_af_reg, "CRYPTO_DEV_OCTEONTX2_CPT");124125int otx2_cpt_attach_rscrs_msg(struct otx2_cptlfs_info *lfs)126{127struct otx2_mbox *mbox = lfs->mbox;128struct rsrc_attach *req;129int ret;130131req = (struct rsrc_attach *)132otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),133sizeof(struct msg_rsp));134if (req == NULL) {135dev_err(&lfs->pdev->dev, "RVU MBOX failed to get message.\n");136return -EFAULT;137}138139req->hdr.id = MBOX_MSG_ATTACH_RESOURCES;140req->hdr.sig = OTX2_MBOX_REQ_SIG;141req->hdr.pcifunc = 0;142req->cptlfs = lfs->lfs_num;143req->cpt_blkaddr = lfs->blkaddr;144req->modify = 1;145ret = otx2_cpt_send_mbox_msg(mbox, lfs->pdev);146if (ret)147return ret;148149if (!lfs->are_lfs_attached)150ret = -EINVAL;151152return ret;153}154155int otx2_cpt_detach_rsrcs_msg(struct otx2_cptlfs_info *lfs)156{157struct otx2_mbox *mbox = lfs->mbox;158struct rsrc_detach *req;159int ret;160161req = (struct rsrc_detach *)162otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),163sizeof(struct msg_rsp));164if (req == NULL) {165dev_err(&lfs->pdev->dev, "RVU MBOX failed to get message.\n");166return -EFAULT;167}168169req->hdr.id = MBOX_MSG_DETACH_RESOURCES;170req->hdr.sig = OTX2_MBOX_REQ_SIG;171req->hdr.pcifunc = 0;172req->cptlfs = 1;173ret = otx2_cpt_send_mbox_msg(mbox, lfs->pdev);174if (ret)175return ret;176177if (lfs->are_lfs_attached)178ret = -EINVAL;179180return ret;181}182EXPORT_SYMBOL_NS_GPL(otx2_cpt_detach_rsrcs_msg, "CRYPTO_DEV_OCTEONTX2_CPT");183184int otx2_cpt_msix_offset_msg(struct otx2_cptlfs_info *lfs)185{186struct otx2_mbox *mbox = lfs->mbox;187struct pci_dev *pdev = lfs->pdev;188struct mbox_msghdr *req;189int ret, i;190191req = otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),192sizeof(struct msix_offset_rsp));193if (req == NULL) {194dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");195return -EFAULT;196}197198req->id = MBOX_MSG_MSIX_OFFSET;199req->sig = OTX2_MBOX_REQ_SIG;200req->pcifunc = 0;201ret = otx2_cpt_send_mbox_msg(mbox, pdev);202if (ret)203return ret;204205for (i = 0; i < lfs->lfs_num; i++) {206if (lfs->lf[i].msix_offset == MSIX_VECTOR_INVALID) {207dev_err(&pdev->dev,208"Invalid msix offset %d for LF %d\n",209lfs->lf[i].msix_offset, i);210return -EINVAL;211}212}213return ret;214}215EXPORT_SYMBOL_NS_GPL(otx2_cpt_msix_offset_msg, "CRYPTO_DEV_OCTEONTX2_CPT");216217int otx2_cpt_sync_mbox_msg(struct otx2_mbox *mbox)218{219int err;220221if (!otx2_mbox_nonempty(mbox, 0))222return 0;223otx2_mbox_msg_send(mbox, 0);224err = otx2_mbox_wait_for_rsp(mbox, 0);225if (err)226return err;227228return otx2_mbox_check_rsp_msgs(mbox, 0);229}230EXPORT_SYMBOL_NS_GPL(otx2_cpt_sync_mbox_msg, "CRYPTO_DEV_OCTEONTX2_CPT");231232int otx2_cpt_lf_reset_msg(struct otx2_cptlfs_info *lfs, int slot)233{234struct otx2_mbox *mbox = lfs->mbox;235struct pci_dev *pdev = lfs->pdev;236struct cpt_lf_rst_req *req;237int ret;238239req = (struct cpt_lf_rst_req *)otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),240sizeof(struct msg_rsp));241if (!req) {242dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");243return -EFAULT;244}245246req->hdr.id = MBOX_MSG_CPT_LF_RESET;247req->hdr.sig = OTX2_MBOX_REQ_SIG;248req->hdr.pcifunc = 0;249req->slot = slot;250ret = otx2_cpt_send_mbox_msg(mbox, pdev);251if (ret)252return ret;253254return ret;255}256EXPORT_SYMBOL_NS_GPL(otx2_cpt_lf_reset_msg, "CRYPTO_DEV_OCTEONTX2_CPT");257258int otx2_cpt_lmtst_tbl_setup_msg(struct otx2_cptlfs_info *lfs)259{260struct otx2_mbox *mbox = lfs->mbox;261struct pci_dev *pdev = lfs->pdev;262struct lmtst_tbl_setup_req *req;263264req = (struct lmtst_tbl_setup_req *)265otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),266sizeof(struct msg_rsp));267if (!req) {268dev_err(&pdev->dev, "RVU MBOX failed to alloc message.\n");269return -EFAULT;270}271272req->hdr.id = MBOX_MSG_LMTST_TBL_SETUP;273req->hdr.sig = OTX2_MBOX_REQ_SIG;274req->hdr.pcifunc = 0;275276req->use_local_lmt_region = true;277req->lmt_iova = lfs->lmt_info.iova;278279return otx2_cpt_send_mbox_msg(mbox, pdev);280}281EXPORT_SYMBOL_NS_GPL(otx2_cpt_lmtst_tbl_setup_msg, "CRYPTO_DEV_OCTEONTX2_CPT");282283284