Path: blob/master/drivers/crypto/marvell/octeontx2/otx2_cptvf.h
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/* SPDX-License-Identifier: GPL-2.0-only1* Copyright (C) 2020 Marvell.2*/34#ifndef __OTX2_CPTVF_H5#define __OTX2_CPTVF_H67#include "mbox.h"8#include "otx2_cptlf.h"910struct otx2_cptvf_dev {11void __iomem *reg_base; /* Register start address */12void __iomem *pfvf_mbox_base; /* PF-VF mbox start address */13struct pci_dev *pdev; /* PCI device handle */14struct otx2_cptlfs_info lfs; /* CPT LFs attached to this VF */15u8 vf_id; /* Virtual function index */1617/* PF <=> VF mbox */18struct otx2_mbox pfvf_mbox;19struct work_struct pfvf_mbox_work;20struct workqueue_struct *pfvf_mbox_wq;21int blkaddr;22void *bbuf_base;23unsigned long cap_flag;24u64 eng_caps[OTX2_CPT_MAX_ENG_TYPES];25};2627irqreturn_t otx2_cptvf_pfvf_mbox_intr(int irq, void *arg);28void otx2_cptvf_pfvf_mbox_handler(struct work_struct *work);29int otx2_cptvf_send_eng_grp_num_msg(struct otx2_cptvf_dev *cptvf, int eng_type);30int otx2_cptvf_send_kvf_limits_msg(struct otx2_cptvf_dev *cptvf);31int otx2_cpt_mbox_bbuf_init(struct otx2_cptvf_dev *cptvf, struct pci_dev *pdev);32int otx2_cptvf_send_caps_msg(struct otx2_cptvf_dev *cptvf);3334#endif /* __OTX2_CPTVF_H */353637