Path: blob/master/drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.h
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/* SPDX-License-Identifier: GPL-2.0-only1* Copyright (C) 2020 Marvell.2*/34#ifndef __OTX2_CPT_ALGS_H5#define __OTX2_CPT_ALGS_H67#include <crypto/hash.h>8#include <crypto/skcipher.h>9#include <crypto/aead.h>10#include "otx2_cpt_common.h"11#include "cn10k_cpt.h"1213#define OTX2_CPT_MAX_ENC_KEY_SIZE 3214#define OTX2_CPT_MAX_HASH_KEY_SIZE 6415#define OTX2_CPT_MAX_KEY_SIZE (OTX2_CPT_MAX_ENC_KEY_SIZE + \16OTX2_CPT_MAX_HASH_KEY_SIZE)17enum otx2_cpt_request_type {18OTX2_CPT_ENC_DEC_REQ = 0x1,19OTX2_CPT_AEAD_ENC_DEC_REQ = 0x2,20OTX2_CPT_AEAD_ENC_DEC_NULL_REQ = 0x3,21OTX2_CPT_PASSTHROUGH_REQ = 0x422};2324enum otx2_cpt_major_opcodes {25OTX2_CPT_MAJOR_OP_MISC = 0x01,26OTX2_CPT_MAJOR_OP_FC = 0x33,27OTX2_CPT_MAJOR_OP_HMAC = 0x35,28};2930enum otx2_cpt_cipher_type {31OTX2_CPT_CIPHER_NULL = 0x0,32OTX2_CPT_DES3_CBC = 0x1,33OTX2_CPT_DES3_ECB = 0x2,34OTX2_CPT_AES_CBC = 0x3,35OTX2_CPT_AES_ECB = 0x4,36OTX2_CPT_AES_CFB = 0x5,37OTX2_CPT_AES_CTR = 0x6,38OTX2_CPT_AES_GCM = 0x7,39OTX2_CPT_AES_XTS = 0x840};4142enum otx2_cpt_mac_type {43OTX2_CPT_MAC_NULL = 0x0,44OTX2_CPT_MD5 = 0x1,45OTX2_CPT_SHA1 = 0x2,46OTX2_CPT_SHA224 = 0x3,47OTX2_CPT_SHA256 = 0x4,48OTX2_CPT_SHA384 = 0x5,49OTX2_CPT_SHA512 = 0x6,50OTX2_CPT_GMAC = 0x751};5253enum otx2_cpt_aes_key_len {54OTX2_CPT_AES_128_BIT = 0x1,55OTX2_CPT_AES_192_BIT = 0x2,56OTX2_CPT_AES_256_BIT = 0x357};5859union otx2_cpt_encr_ctrl {60u64 u;61struct {62#if defined(__BIG_ENDIAN_BITFIELD)63u64 enc_cipher:4;64u64 reserved_59:1;65u64 aes_key:2;66u64 iv_source:1;67u64 mac_type:4;68u64 reserved_49_51:3;69u64 auth_input_type:1;70u64 mac_len:8;71u64 reserved_32_39:8;72u64 encr_offset:16;73u64 iv_offset:8;74u64 auth_offset:8;75#else76u64 auth_offset:8;77u64 iv_offset:8;78u64 encr_offset:16;79u64 reserved_32_39:8;80u64 mac_len:8;81u64 auth_input_type:1;82u64 reserved_49_51:3;83u64 mac_type:4;84u64 iv_source:1;85u64 aes_key:2;86u64 reserved_59:1;87u64 enc_cipher:4;88#endif89} e;90};9192struct otx2_cpt_cipher {93const char *name;94u8 value;95};9697struct otx2_cpt_fc_enc_ctx {98union otx2_cpt_encr_ctrl enc_ctrl;99u8 encr_key[32];100u8 encr_iv[16];101};102103union otx2_cpt_fc_hmac_ctx {104struct {105u8 ipad[64];106u8 opad[64];107} e;108struct {109u8 hmac_calc[64]; /* HMAC calculated */110u8 hmac_recv[64]; /* HMAC received */111} s;112};113114struct otx2_cpt_fc_ctx {115struct otx2_cpt_fc_enc_ctx enc;116union otx2_cpt_fc_hmac_ctx hmac;117};118119struct otx2_cpt_enc_ctx {120u32 key_len;121u8 enc_key[OTX2_CPT_MAX_KEY_SIZE];122u8 cipher_type;123u8 key_type;124u8 enc_align_len;125struct crypto_skcipher *fbk_cipher;126struct pci_dev *pdev;127struct cn10k_cpt_errata_ctx er_ctx;128};129130union otx2_cpt_offset_ctrl {131u64 flags;132struct {133#if defined(__BIG_ENDIAN_BITFIELD)134u64 reserved:32;135u64 enc_data_offset:16;136u64 iv_offset:8;137u64 auth_offset:8;138#else139u64 auth_offset:8;140u64 iv_offset:8;141u64 enc_data_offset:16;142u64 reserved:32;143#endif144} e;145};146147struct otx2_cpt_req_ctx {148struct otx2_cpt_req_info cpt_req;149union otx2_cpt_offset_ctrl ctrl_word;150struct otx2_cpt_fc_ctx fctx;151union {152struct skcipher_request sk_fbk_req;153struct aead_request fbk_req;154};155};156157struct otx2_cpt_sdesc {158struct shash_desc shash;159};160161struct otx2_cpt_aead_ctx {162u8 key[OTX2_CPT_MAX_KEY_SIZE];163struct crypto_shash *hashalg;164struct otx2_cpt_sdesc *sdesc;165struct crypto_aead *fbk_cipher;166struct cn10k_cpt_errata_ctx er_ctx;167struct pci_dev *pdev;168u8 *ipad;169u8 *opad;170u32 enc_key_len;171u32 auth_key_len;172u8 cipher_type;173u8 mac_type;174u8 key_type;175u8 is_trunc_hmac;176u8 enc_align_len;177};178int otx2_cpt_crypto_init(struct pci_dev *pdev, struct module *mod,179int num_queues, int num_devices);180void otx2_cpt_crypto_exit(struct pci_dev *pdev, struct module *mod);181182#endif /* __OTX2_CPT_ALGS_H */183184185