/* SPDX-License-Identifier: GPL-2.0-only */1/*2* Copyright(c) 2023 Huawei3* CXL Specification rev 3.0 Setion 8.2.7 (CPMU Register Interface)4*/5#ifndef CXL_PMU_H6#define CXL_PMU_H7#include <linux/device.h>89enum cxl_pmu_type {10CXL_PMU_MEMDEV,11};1213#define CXL_PMU_REGMAP_SIZE 0xe00 /* Table 8-32 CXL 3.0 specification */14struct cxl_pmu {15struct device dev;16void __iomem *base;17int assoc_id;18int index;19enum cxl_pmu_type type;20};2122#define to_cxl_pmu(dev) container_of(dev, struct cxl_pmu, dev)23struct cxl_pmu_regs;24int devm_cxl_pmu_add(struct device *parent, struct cxl_pmu_regs *regs,25int assoc_id, int idx, enum cxl_pmu_type type);2627#endif282930