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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/drivers/dma/amd/ptdma/ptdma-debugfs.c
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// SPDX-License-Identifier: GPL-2.0-only

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/*

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 * AMD Passthrough DMA device driver

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 * -- Based on the CCP driver

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 *

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 * Copyright (C) 2016,2021 Advanced Micro Devices, Inc.

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 *

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 * Author: Sanjay R Mehta <[email protected]>

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 * Author: Gary R Hook <[email protected]>

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 */

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#include <linux/debugfs.h>

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#include <linux/seq_file.h>

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#include "ptdma.h"

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#include "../ae4dma/ae4dma.h"

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/* DebugFS helpers */

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#define	RI_VERSION_NUM	0x0000003F

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#define	RI_NUM_VQM	0x00078000

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#define	RI_NVQM_SHIFT	15

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static int pt_debugfs_info_show(struct seq_file *s, void *p)

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{

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	struct pt_device *pt = s->private;

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	struct ae4_device *ae4;

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	unsigned int regval;

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	seq_printf(s, "Device name: %s\n", dev_name(pt->dev));

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	if (pt->ver == AE4_DMA_VERSION) {

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		ae4 = container_of(pt, struct ae4_device, pt);

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		seq_printf(s, "   # Queues: %d\n", ae4->cmd_q_count);

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		seq_printf(s, "     # Cmds per queue: %d\n", CMD_Q_LEN);

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	} else {

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		seq_printf(s, "   # Queues: %d\n", 1);

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		seq_printf(s, "     # Cmds: %d\n", pt->cmd_count);

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	}

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	regval = ioread32(pt->io_regs + CMD_PT_VERSION);

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	seq_printf(s, "    Version: %d\n", regval & RI_VERSION_NUM);

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	seq_puts(s, "    Engines:");

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	seq_puts(s, "\n");

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	seq_printf(s, "     Queues: %d\n", (regval & RI_NUM_VQM) >> RI_NVQM_SHIFT);

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	return 0;

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}

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/*

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 * Return a formatted buffer containing the current

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 * statistics of queue for PTDMA

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 */

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static int pt_debugfs_stats_show(struct seq_file *s, void *p)

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{

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	struct pt_device *pt = s->private;

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	seq_printf(s, "Total Interrupts Handled: %ld\n", pt->total_interrupts);

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	return 0;

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}

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static int pt_debugfs_queue_show(struct seq_file *s, void *p)

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{

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	struct pt_cmd_queue *cmd_q = s->private;

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	struct pt_device *pt;

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	unsigned int regval;

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	if (!cmd_q)

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		return 0;

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	seq_printf(s, "               Pass-Thru: %ld\n", cmd_q->total_pt_ops);

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	pt = cmd_q->pt;

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	if (pt->ver == AE4_DMA_VERSION) {

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		regval = readl(cmd_q->reg_control + 0x4);

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		seq_printf(s, "     Enabled Interrupts:: status 0x%x\n", regval);

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	} else {

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		regval = ioread32(cmd_q->reg_control + 0x000C);

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		seq_puts(s, "      Enabled Interrupts:");

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		if (regval & INT_EMPTY_QUEUE)

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			seq_puts(s, " EMPTY");

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		if (regval & INT_QUEUE_STOPPED)

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			seq_puts(s, " STOPPED");

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		if (regval & INT_ERROR)

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			seq_puts(s, " ERROR");

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		if (regval & INT_COMPLETION)

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			seq_puts(s, " COMPLETION");

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		seq_puts(s, "\n");

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	}

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	return 0;

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}

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DEFINE_SHOW_ATTRIBUTE(pt_debugfs_info);

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DEFINE_SHOW_ATTRIBUTE(pt_debugfs_queue);

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DEFINE_SHOW_ATTRIBUTE(pt_debugfs_stats);

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void ptdma_debugfs_setup(struct pt_device *pt)

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{

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	struct dentry *debugfs_q_instance;

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	struct ae4_cmd_queue *ae4cmd_q;

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	struct pt_cmd_queue *cmd_q;

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	struct ae4_device *ae4;

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	char name[30];

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	int i;

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	if (!debugfs_initialized())

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		return;

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	debugfs_create_file("info", 0400, pt->dma_dev.dbg_dev_root, pt,

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			    &pt_debugfs_info_fops);

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	debugfs_create_file("stats", 0400, pt->dma_dev.dbg_dev_root, pt,

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			    &pt_debugfs_stats_fops);

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	if (pt->ver == AE4_DMA_VERSION) {

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		ae4 = container_of(pt, struct ae4_device, pt);

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		for (i = 0; i < ae4->cmd_q_count; i++) {

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			ae4cmd_q = &ae4->ae4cmd_q[i];

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			cmd_q = &ae4cmd_q->cmd_q;

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			memset(name, 0, sizeof(name));

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			snprintf(name, 29, "q%d", ae4cmd_q->id);

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			debugfs_q_instance =

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				debugfs_create_dir(name, pt->dma_dev.dbg_dev_root);

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			debugfs_create_file("stats", 0400, debugfs_q_instance, cmd_q,

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					    &pt_debugfs_queue_fops);

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		}

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	} else {

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		debugfs_q_instance =

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			debugfs_create_dir("q", pt->dma_dev.dbg_dev_root);

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		cmd_q = &pt->cmd_q;

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		debugfs_create_file("stats", 0400, debugfs_q_instance, cmd_q,

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				    &pt_debugfs_queue_fops);

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	}

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}

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EXPORT_SYMBOL_GPL(ptdma_debugfs_setup);

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