CoCalc -- hw.h

GitHub Repository: torvalds/linux
Path: blob/master/drivers/dma/ioat/hw.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
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 */
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#ifndef _IOAT_HW_H_
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#define _IOAT_HW_H_
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/* PCI Configuration Space Values */
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#define IOAT_MMIO_BAR		0
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/* CB device ID's */
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#define PCI_DEVICE_ID_INTEL_IOAT_IVB0	0x0e20
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#define PCI_DEVICE_ID_INTEL_IOAT_IVB1	0x0e21
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#define PCI_DEVICE_ID_INTEL_IOAT_IVB2	0x0e22
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#define PCI_DEVICE_ID_INTEL_IOAT_IVB3	0x0e23
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#define PCI_DEVICE_ID_INTEL_IOAT_IVB4	0x0e24
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#define PCI_DEVICE_ID_INTEL_IOAT_IVB5	0x0e25
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#define PCI_DEVICE_ID_INTEL_IOAT_IVB6	0x0e26
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#define PCI_DEVICE_ID_INTEL_IOAT_IVB7	0x0e27
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#define PCI_DEVICE_ID_INTEL_IOAT_IVB8	0x0e2e
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#define PCI_DEVICE_ID_INTEL_IOAT_IVB9	0x0e2f
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#define PCI_DEVICE_ID_INTEL_IOAT_HSW0	0x2f20
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#define PCI_DEVICE_ID_INTEL_IOAT_HSW1	0x2f21
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#define PCI_DEVICE_ID_INTEL_IOAT_HSW2	0x2f22
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#define PCI_DEVICE_ID_INTEL_IOAT_HSW3	0x2f23
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#define PCI_DEVICE_ID_INTEL_IOAT_HSW4	0x2f24
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#define PCI_DEVICE_ID_INTEL_IOAT_HSW5	0x2f25
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#define PCI_DEVICE_ID_INTEL_IOAT_HSW6	0x2f26
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#define PCI_DEVICE_ID_INTEL_IOAT_HSW7	0x2f27
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#define PCI_DEVICE_ID_INTEL_IOAT_HSW8	0x2f2e
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#define PCI_DEVICE_ID_INTEL_IOAT_HSW9	0x2f2f
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#define PCI_DEVICE_ID_INTEL_IOAT_BWD0	0x0C50
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#define PCI_DEVICE_ID_INTEL_IOAT_BWD1	0x0C51
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#define PCI_DEVICE_ID_INTEL_IOAT_BWD2	0x0C52
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#define PCI_DEVICE_ID_INTEL_IOAT_BWD3	0x0C53
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#define PCI_DEVICE_ID_INTEL_IOAT_BDXDE0	0x6f50
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#define PCI_DEVICE_ID_INTEL_IOAT_BDXDE1	0x6f51
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#define PCI_DEVICE_ID_INTEL_IOAT_BDXDE2	0x6f52
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#define PCI_DEVICE_ID_INTEL_IOAT_BDXDE3	0x6f53
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#define PCI_DEVICE_ID_INTEL_IOAT_BDX0	0x6f20
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#define PCI_DEVICE_ID_INTEL_IOAT_BDX1	0x6f21
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#define PCI_DEVICE_ID_INTEL_IOAT_BDX2	0x6f22
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#define PCI_DEVICE_ID_INTEL_IOAT_BDX3	0x6f23
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#define PCI_DEVICE_ID_INTEL_IOAT_BDX4	0x6f24
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#define PCI_DEVICE_ID_INTEL_IOAT_BDX5	0x6f25
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#define PCI_DEVICE_ID_INTEL_IOAT_BDX6	0x6f26
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#define PCI_DEVICE_ID_INTEL_IOAT_BDX7	0x6f27
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#define PCI_DEVICE_ID_INTEL_IOAT_BDX8	0x6f2e
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#define PCI_DEVICE_ID_INTEL_IOAT_BDX9	0x6f2f
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#define PCI_DEVICE_ID_INTEL_IOAT_SKX	0x2021
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#define PCI_DEVICE_ID_INTEL_IOAT_ICX	0x0b00
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#define IOAT_VER_1_2            0x12    /* Version 1.2 */
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#define IOAT_VER_2_0            0x20    /* Version 2.0 */
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#define IOAT_VER_3_0            0x30    /* Version 3.0 */
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#define IOAT_VER_3_2            0x32    /* Version 3.2 */
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#define IOAT_VER_3_3            0x33    /* Version 3.3 */
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#define IOAT_VER_3_4		0x34	/* Version 3.4 */
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int system_has_dca_enabled(struct pci_dev *pdev);
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#define IOAT_DESC_SZ	64
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struct ioat_dma_descriptor {
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	uint32_t	size;
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	union {
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		uint32_t ctl;
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		struct {
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			unsigned int int_en:1;
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			unsigned int src_snoop_dis:1;
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			unsigned int dest_snoop_dis:1;
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			unsigned int compl_write:1;
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			unsigned int fence:1;
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			unsigned int null:1;
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			unsigned int src_brk:1;
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			unsigned int dest_brk:1;
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			unsigned int bundle:1;
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			unsigned int dest_dca:1;
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			unsigned int hint:1;
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			unsigned int rsvd2:13;
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			#define IOAT_OP_COPY 0x00
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			unsigned int op:8;
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		} ctl_f;
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	};
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	uint64_t	src_addr;
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	uint64_t	dst_addr;
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	uint64_t	next;
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	uint64_t	rsv1;
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	uint64_t	rsv2;
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	/* store some driver data in an unused portion of the descriptor */
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	union {
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		uint64_t	user1;
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		uint64_t	tx_cnt;
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	};
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	uint64_t	user2;
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};
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struct ioat_xor_descriptor {
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	uint32_t	size;
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	union {
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		uint32_t ctl;
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		struct {
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			unsigned int int_en:1;
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			unsigned int src_snoop_dis:1;
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			unsigned int dest_snoop_dis:1;
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			unsigned int compl_write:1;
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			unsigned int fence:1;
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			unsigned int src_cnt:3;
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			unsigned int bundle:1;
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			unsigned int dest_dca:1;
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			unsigned int hint:1;
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			unsigned int rsvd:13;
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			#define IOAT_OP_XOR 0x87
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			#define IOAT_OP_XOR_VAL 0x88
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			unsigned int op:8;
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		} ctl_f;
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	};
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	uint64_t	src_addr;
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	uint64_t	dst_addr;
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	uint64_t	next;
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	uint64_t	src_addr2;
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	uint64_t	src_addr3;
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	uint64_t	src_addr4;
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	uint64_t	src_addr5;
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};
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struct ioat_xor_ext_descriptor {
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	uint64_t	src_addr6;
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	uint64_t	src_addr7;
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	uint64_t	src_addr8;
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	uint64_t	next;
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	uint64_t	rsvd[4];
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};
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struct ioat_pq_descriptor {
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	union {
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		uint32_t	size;
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		uint32_t	dwbes;
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		struct {
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			unsigned int rsvd:25;
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			unsigned int p_val_err:1;
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			unsigned int q_val_err:1;
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			unsigned int rsvd1:4;
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			unsigned int wbes:1;
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		} dwbes_f;
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	};
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	union {
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		uint32_t ctl;
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		struct {
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			unsigned int int_en:1;
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			unsigned int src_snoop_dis:1;
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			unsigned int dest_snoop_dis:1;
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			unsigned int compl_write:1;
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			unsigned int fence:1;
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			unsigned int src_cnt:3;
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			unsigned int bundle:1;
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			unsigned int dest_dca:1;
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			unsigned int hint:1;
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			unsigned int p_disable:1;
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			unsigned int q_disable:1;
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			unsigned int rsvd2:2;
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			unsigned int wb_en:1;
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			unsigned int prl_en:1;
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			unsigned int rsvd3:7;
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			#define IOAT_OP_PQ 0x89
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			#define IOAT_OP_PQ_VAL 0x8a
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			#define IOAT_OP_PQ_16S 0xa0
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			#define IOAT_OP_PQ_VAL_16S 0xa1
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			unsigned int op:8;
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		} ctl_f;
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	};
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	uint64_t	src_addr;
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	uint64_t	p_addr;
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	uint64_t	next;
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	uint64_t	src_addr2;
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	union {
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		uint64_t	src_addr3;
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		uint64_t	sed_addr;
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	};
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	uint8_t		coef[8];
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	uint64_t	q_addr;
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};
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struct ioat_pq_ext_descriptor {
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	uint64_t	src_addr4;
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	uint64_t	src_addr5;
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	uint64_t	src_addr6;
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	uint64_t	next;
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	uint64_t	src_addr7;
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	uint64_t	src_addr8;
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	uint64_t	rsvd[2];
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};
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struct ioat_pq_update_descriptor {
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	uint32_t	size;
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	union {
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		uint32_t ctl;
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		struct {
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			unsigned int int_en:1;
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			unsigned int src_snoop_dis:1;
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			unsigned int dest_snoop_dis:1;
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			unsigned int compl_write:1;
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			unsigned int fence:1;
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			unsigned int src_cnt:3;
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			unsigned int bundle:1;
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			unsigned int dest_dca:1;
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			unsigned int hint:1;
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			unsigned int p_disable:1;
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			unsigned int q_disable:1;
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			unsigned int rsvd:3;
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			unsigned int coef:8;
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			#define IOAT_OP_PQ_UP 0x8b
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			unsigned int op:8;
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		} ctl_f;
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	};
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	uint64_t	src_addr;
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	uint64_t	p_addr;
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	uint64_t	next;
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	uint64_t	src_addr2;
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	uint64_t	p_src;
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	uint64_t	q_src;
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	uint64_t	q_addr;
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};
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struct ioat_raw_descriptor {
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	uint64_t	field[8];
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};
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struct ioat_pq16a_descriptor {
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	uint8_t coef[8];
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	uint64_t src_addr3;
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	uint64_t src_addr4;
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	uint64_t src_addr5;
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	uint64_t src_addr6;
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	uint64_t src_addr7;
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	uint64_t src_addr8;
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	uint64_t src_addr9;
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};
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struct ioat_pq16b_descriptor {
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	uint64_t src_addr10;
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	uint64_t src_addr11;
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	uint64_t src_addr12;
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	uint64_t src_addr13;
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	uint64_t src_addr14;
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	uint64_t src_addr15;
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	uint64_t src_addr16;
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	uint64_t rsvd;
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};
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union ioat_sed_pq_descriptor {
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	struct ioat_pq16a_descriptor a;
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	struct ioat_pq16b_descriptor b;
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};
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#define SED_SIZE	64
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struct ioat_sed_raw_descriptor {
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	uint64_t	a[8];
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	uint64_t	b[8];
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	uint64_t	c[8];
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};
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#endif
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