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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/drivers/firmware/efi/cper_cxl.c
26428 views
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// SPDX-License-Identifier: GPL-2.0-only

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/*

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 * UEFI Common Platform Error Record (CPER) support for CXL Section.

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 *

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 * Copyright (C) 2022 Advanced Micro Devices, Inc.

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 *

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 * Author: Smita Koralahalli <[email protected]>

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 */

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#include <linux/cper.h>

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#include <cxl/event.h>

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static const char * const prot_err_agent_type_strs[] = {

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	"Restricted CXL Device",

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	"Restricted CXL Host Downstream Port",

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	"CXL Device",

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	"CXL Logical Device",

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	"CXL Fabric Manager managed Logical Device",

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	"CXL Root Port",

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	"CXL Downstream Switch Port",

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	"CXL Upstream Switch Port",

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};

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void cxl_cper_print_prot_err(const char *pfx,

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			     const struct cxl_cper_sec_prot_err *prot_err)

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{

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	if (prot_err->valid_bits & PROT_ERR_VALID_AGENT_TYPE)

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		pr_info("%s agent_type: %d, %s\n", pfx, prot_err->agent_type,

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			prot_err->agent_type < ARRAY_SIZE(prot_err_agent_type_strs)

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			? prot_err_agent_type_strs[prot_err->agent_type]

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			: "unknown");

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	if (prot_err->valid_bits & PROT_ERR_VALID_AGENT_ADDRESS) {

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		switch (prot_err->agent_type) {

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		/*

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		 * According to UEFI 2.10 Section N.2.13, the term CXL Device

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		 * is used to refer to Restricted CXL Device, CXL Device, CXL

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		 * Logical Device or a CXL Fabric Manager Managed Logical

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		 * Device.

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		 */

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		case RCD:

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		case DEVICE:

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		case LD:

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		case FMLD:

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		case RP:

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		case DSP:

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		case USP:

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			pr_info("%s agent_address: %04x:%02x:%02x.%x\n",

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				pfx, prot_err->agent_addr.segment,

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				prot_err->agent_addr.bus,

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				prot_err->agent_addr.device,

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				prot_err->agent_addr.function);

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			break;

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		case RCH_DP:

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			pr_info("%s rcrb_base_address: 0x%016llx\n", pfx,

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				prot_err->agent_addr.rcrb_base_addr);

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			break;

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		default:

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			break;

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		}

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	}

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	if (prot_err->valid_bits & PROT_ERR_VALID_DEVICE_ID) {

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		const __u8 *class_code;

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		switch (prot_err->agent_type) {

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		case RCD:

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		case DEVICE:

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		case LD:

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		case FMLD:

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		case RP:

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		case DSP:

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		case USP:

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			pr_info("%s slot: %d\n", pfx,

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				prot_err->device_id.slot >> CPER_PCIE_SLOT_SHIFT);

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			pr_info("%s vendor_id: 0x%04x, device_id: 0x%04x\n",

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				pfx, prot_err->device_id.vendor_id,

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				prot_err->device_id.device_id);

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			pr_info("%s sub_vendor_id: 0x%04x, sub_device_id: 0x%04x\n",

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				pfx, prot_err->device_id.subsystem_vendor_id,

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				prot_err->device_id.subsystem_id);

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			class_code = prot_err->device_id.class_code;

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			pr_info("%s class_code: %02x%02x\n", pfx,

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				class_code[1], class_code[0]);

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			break;

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		default:

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			break;

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		}

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	}

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	if (prot_err->valid_bits & PROT_ERR_VALID_SERIAL_NUMBER) {

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		switch (prot_err->agent_type) {

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		case RCD:

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		case DEVICE:

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		case LD:

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		case FMLD:

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			pr_info("%s lower_dw: 0x%08x, upper_dw: 0x%08x\n", pfx,

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				prot_err->dev_serial_num.lower_dw,

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				prot_err->dev_serial_num.upper_dw);

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			break;

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		default:

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			break;

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		}

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	}

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	if (prot_err->valid_bits & PROT_ERR_VALID_CAPABILITY) {

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		switch (prot_err->agent_type) {

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		case RCD:

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		case DEVICE:

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		case LD:

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		case FMLD:

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		case RP:

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		case DSP:

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		case USP:

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			print_hex_dump(pfx, "", DUMP_PREFIX_OFFSET, 16, 4,

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				       prot_err->capability,

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				       sizeof(prot_err->capability), 0);

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			break;

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		default:

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			break;

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		}

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	}

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	if (prot_err->valid_bits & PROT_ERR_VALID_DVSEC) {

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		pr_info("%s DVSEC length: 0x%04x\n", pfx, prot_err->dvsec_len);

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		pr_info("%s CXL DVSEC:\n", pfx);

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		print_hex_dump(pfx, "", DUMP_PREFIX_OFFSET, 16, 4, (prot_err + 1),

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			       prot_err->dvsec_len, 0);

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	}

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	if (prot_err->valid_bits & PROT_ERR_VALID_ERROR_LOG) {

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		size_t size = sizeof(*prot_err) + prot_err->dvsec_len;

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		struct cxl_ras_capability_regs *cxl_ras;

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		pr_info("%s Error log length: 0x%04x\n", pfx, prot_err->err_len);

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		pr_info("%s CXL Error Log:\n", pfx);

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		cxl_ras = (struct cxl_ras_capability_regs *)((long)prot_err + size);

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		pr_info("%s cxl_ras_uncor_status: 0x%08x", pfx,

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			cxl_ras->uncor_status);

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		pr_info("%s cxl_ras_uncor_mask: 0x%08x\n", pfx,

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			cxl_ras->uncor_mask);

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		pr_info("%s cxl_ras_uncor_severity: 0x%08x\n", pfx,

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			cxl_ras->uncor_severity);

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		pr_info("%s cxl_ras_cor_status: 0x%08x", pfx,

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			cxl_ras->cor_status);

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		pr_info("%s cxl_ras_cor_mask: 0x%08x\n", pfx,

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			cxl_ras->cor_mask);

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		pr_info("%s cap_control: 0x%08x\n", pfx,

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			cxl_ras->cap_control);

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		pr_info("%s Header Log Registers:\n", pfx);

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		print_hex_dump(pfx, "", DUMP_PREFIX_OFFSET, 16, 4, cxl_ras->header_log,

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			       sizeof(cxl_ras->header_log), 0);

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	}

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}

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