/* SPDX-License-Identifier: GPL-2.0 */1/*2* Header file for FPGA Accelerated Function Unit (AFU) Driver3*4* Copyright (C) 2017-2018 Intel Corporation, Inc.5*6* Authors:7* Wu Hao <[email protected]>8* Xiao Guangrong <[email protected]>9* Joseph Grecco <[email protected]>10* Enno Luebbers <[email protected]>11* Tim Whisonant <[email protected]>12* Ananda Ravuri <[email protected]>13* Henry Mitchel <[email protected]>14*/1516#ifndef __DFL_AFU_H17#define __DFL_AFU_H1819#include <linux/mm.h>2021#include "dfl.h"2223/**24* struct dfl_afu_mmio_region - afu mmio region data structure25*26* @index: region index.27* @flags: region flags (access permission).28* @size: region size.29* @offset: region offset from start of the device fd.30* @phys: region's physical address.31* @node: node to add to afu feature dev's region list.32*/33struct dfl_afu_mmio_region {34u32 index;35u32 flags;36u64 size;37u64 offset;38u64 phys;39struct list_head node;40};4142/**43* struct dfl_afu_dma_region - afu DMA region data structure44*45* @user_addr: region userspace virtual address.46* @length: region length.47* @iova: region IO virtual address.48* @pages: ptr to pages of this region.49* @node: rb tree node.50* @in_use: flag to indicate if this region is in_use.51*/52struct dfl_afu_dma_region {53u64 user_addr;54u64 length;55u64 iova;56struct page **pages;57struct rb_node node;58bool in_use;59};6061/**62* struct dfl_afu - afu device data structure63*64* @region_cur_offset: current region offset from start to the device fd.65* @num_regions: num of mmio regions.66* @regions: the mmio region linked list of this afu feature device.67* @dma_regions: root of dma regions rb tree.68* @num_umsgs: num of umsgs.69*/70struct dfl_afu {71u64 region_cur_offset;72int num_regions;73u8 num_umsgs;74struct list_head regions;75struct rb_root dma_regions;76};7778/* hold fdata->lock when call __afu_port_enable/disable */79int __afu_port_enable(struct dfl_feature_dev_data *fdata);80int __afu_port_disable(struct dfl_feature_dev_data *fdata);8182void afu_mmio_region_init(struct dfl_feature_dev_data *fdata);83int afu_mmio_region_add(struct dfl_feature_dev_data *fdata,84u32 region_index, u64 region_size, u64 phys, u32 flags);85void afu_mmio_region_destroy(struct dfl_feature_dev_data *fdata);86int afu_mmio_region_get_by_index(struct dfl_feature_dev_data *fdata,87u32 region_index,88struct dfl_afu_mmio_region *pregion);89int afu_mmio_region_get_by_offset(struct dfl_feature_dev_data *fdata,90u64 offset, u64 size,91struct dfl_afu_mmio_region *pregion);92void afu_dma_region_init(struct dfl_feature_dev_data *fdata);93void afu_dma_region_destroy(struct dfl_feature_dev_data *fdata);94int afu_dma_map_region(struct dfl_feature_dev_data *fdata,95u64 user_addr, u64 length, u64 *iova);96int afu_dma_unmap_region(struct dfl_feature_dev_data *fdata, u64 iova);97struct dfl_afu_dma_region *98afu_dma_region_find(struct dfl_feature_dev_data *fdata,99u64 iova, u64 size);100101extern const struct dfl_feature_ops port_err_ops;102extern const struct dfl_feature_id port_err_id_table[];103extern const struct attribute_group port_err_group;104105#endif /* __DFL_AFU_H */106107108