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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c
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/*

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 * Copyright 2020 Advanced Micro Devices, Inc.

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 *

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 * Permission is hereby granted, free of charge, to any person obtaining a

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 * copy of this software and associated documentation files (the "Software"),

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 * to deal in the Software without restriction, including without limitation

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 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

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 * and/or sell copies of the Software, and to permit persons to whom the

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 * Software is furnished to do so, subject to the following conditions:

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 *

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 * The above copyright notice and this permission notice shall be included in

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 * all copies or substantial portions of the Software.

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 *

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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

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 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

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 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

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 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

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 * OTHER DEALINGS IN THE SOFTWARE.

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 *

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 */

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#include "amdgpu.h"

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#include "soc15.h"

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#include "soc15_common.h"

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#include "aldebaran_ip_offset.h"

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int aldebaran_reg_base_init(struct amdgpu_device *adev)

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{

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	/* HW has more IP blocks,  only initialized the block needed by our driver  */

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	uint32_t i;

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	for (i = 0 ; i < MAX_INSTANCE ; ++i) {

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		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

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		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));

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		adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));

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		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));

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		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

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		adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));

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		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));

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		adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));

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		adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));

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		adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));

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		adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));

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		adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(SDMA2_BASE.instance[i]));

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		adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(SDMA3_BASE.instance[i]));

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		adev->reg_offset[SDMA4_HWIP][i] = (uint32_t *)(&(SDMA4_BASE.instance[i]));

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		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));

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		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));

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		adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i]));

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		adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));

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	}

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	return 0;

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}

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