Path: blob/master/drivers/gpu/drm/amd/amdkfd/cik_regs.h
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/*1* Copyright 2014 Advanced Micro Devices, Inc.2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice shall be included in11* all copies or substantial portions of the Software.12*13* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR14* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,15* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL16* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR17* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,18* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR19* OTHER DEALINGS IN THE SOFTWARE.20*/2122#ifndef CIK_REGS_H23#define CIK_REGS_H2425/* if PTR32, these are the bases for scratch and lds */26#define PRIVATE_BASE(x) ((x) << 0) /* scratch */27#define SHARED_BASE(x) ((x) << 16) /* LDS */28#define PTR32 (1 << 0)29#define ALIGNMENT_MODE(x) ((x) << 2)30#define SH_MEM_ALIGNMENT_MODE_UNALIGNED 331#define DEFAULT_MTYPE(x) ((x) << 4)32#define APE1_MTYPE(x) ((x) << 7)3334/* valid for both DEFAULT_MTYPE and APE1_MTYPE */35#define MTYPE_CACHED_NV 036#define MTYPE_CACHED 137#define MTYPE_NONCACHED 33839#define DEFAULT_CP_HQD_PERSISTENT_STATE (0x33U << 8)40#define PRELOAD_REQ (1 << 0)4142#define MQD_CONTROL_PRIV_STATE_EN (1U << 8)4344#define DEFAULT_MIN_IB_AVAIL_SIZE (3U << 20)4546#define IB_ATC_EN (1U << 23)4748#define QUANTUM_EN 1U49#define QUANTUM_SCALE_1MS (1U << 4)50#define QUANTUM_DURATION(x) ((x) << 8)5152#define RPTR_BLOCK_SIZE(x) ((x) << 8)53#define MIN_AVAIL_SIZE(x) ((x) << 20)54#define DEFAULT_RPTR_BLOCK_SIZE RPTR_BLOCK_SIZE(5)55#define DEFAULT_MIN_AVAIL_SIZE MIN_AVAIL_SIZE(3)5657#define PQ_ATC_EN (1 << 23)58#define NO_UPDATE_RPTR (1 << 27)5960#define DOORBELL_OFFSET(x) ((x) << 2)61#define DOORBELL_EN (1 << 30)6263#define PRIV_STATE (1 << 30)64#define KMD_QUEUE (1 << 31)6566#define AQL_ENABLE 16768#define GRBM_GFX_INDEX 0x308006970#endif717273