Path: blob/master/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
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/*1* Copyright 2016-2023 Advanced Micro Devices, Inc.2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice shall be included in11* all copies or substantial portions of the Software.12*13* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR14* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,15* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL16* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR17* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,18* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR19* OTHER DEALINGS IN THE SOFTWARE.20*21* Authors: AMD22*23*/2425#include "dm_services.h"26#include "dc.h"27#include "mod_freesync.h"28#include "core_types.h"2930#define MOD_FREESYNC_MAX_CONCURRENT_STREAMS 323132#define MIN_REFRESH_RANGE 1033/* Refresh rate ramp at a fixed rate of 65 Hz/second */34#define STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME ((1000 / 60) * 65)35/* Number of elements in the render times cache array */36#define RENDER_TIMES_MAX_COUNT 1037/* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower limit) */38#define BTR_MAX_MARGIN 250039/* Threshold to change BTR multiplier (to avoid frequent changes) */40#define BTR_DRIFT_MARGIN 200041/* Threshold to exit fixed refresh rate */42#define FIXED_REFRESH_EXIT_MARGIN_IN_HZ 143/* Number of consecutive frames to check before entering/exiting fixed refresh */44#define FIXED_REFRESH_ENTER_FRAME_COUNT 545#define FIXED_REFRESH_EXIT_FRAME_COUNT 1046/* Flip interval workaround constants */47#define VSYNCS_BETWEEN_FLIP_THRESHOLD 248#define FREESYNC_CONSEC_FLIP_AFTER_VSYNC 549#define FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US 50050#define MICRO_HZ_TO_HZ(x) (x / 1000000)5152struct core_freesync {53struct mod_freesync public;54struct dc *dc;55};5657#define MOD_FREESYNC_TO_CORE(mod_freesync)\58container_of(mod_freesync, struct core_freesync, public)5960struct mod_freesync *mod_freesync_create(struct dc *dc)61{62struct core_freesync *core_freesync =63kzalloc(sizeof(struct core_freesync), GFP_KERNEL);6465if (core_freesync == NULL)66goto fail_alloc_context;6768if (dc == NULL)69goto fail_construct;7071core_freesync->dc = dc;72return &core_freesync->public;7374fail_construct:75kfree(core_freesync);7677fail_alloc_context:78return NULL;79}8081void mod_freesync_destroy(struct mod_freesync *mod_freesync)82{83struct core_freesync *core_freesync = NULL;8485if (mod_freesync == NULL)86return;87core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);88kfree(core_freesync);89}9091#if 0 /* Unused currently */92static unsigned int calc_refresh_in_uhz_from_duration(93unsigned int duration_in_ns)94{95unsigned int refresh_in_uhz =96((unsigned int)(div64_u64((1000000000ULL * 1000000),97duration_in_ns)));98return refresh_in_uhz;99}100#endif101102static unsigned int calc_duration_in_us_from_refresh_in_uhz(103unsigned int refresh_in_uhz)104{105unsigned int duration_in_us =106((unsigned int)(div64_u64((1000000000ULL * 1000),107refresh_in_uhz)));108return duration_in_us;109}110111static unsigned int calc_duration_in_us_from_v_total(112const struct dc_stream_state *stream,113const struct mod_vrr_params *in_vrr,114unsigned int v_total)115{116unsigned int duration_in_us =117(unsigned int)(div64_u64(((unsigned long long)(v_total)118* 10000) * stream->timing.h_total,119stream->timing.pix_clk_100hz));120121return duration_in_us;122}123124static unsigned int calc_max_hardware_v_total(const struct dc_stream_state *stream)125{126unsigned int max_hw_v_total = stream->ctx->dc->caps.max_v_total;127128if (stream->ctx->dc->caps.vtotal_limited_by_fp2) {129max_hw_v_total -= stream->timing.v_front_porch + 1;130}131132return max_hw_v_total;133}134135unsigned int mod_freesync_calc_v_total_from_refresh(136const struct dc_stream_state *stream,137unsigned int refresh_in_uhz)138{139unsigned int v_total;140unsigned int frame_duration_in_ns;141142if (refresh_in_uhz == 0)143return stream->timing.v_total;144145frame_duration_in_ns =146((unsigned int)(div64_u64((1000000000ULL * 1000000),147refresh_in_uhz)));148149if (refresh_in_uhz <= stream->timing.min_refresh_in_uhz) {150/* When the target refresh rate is the minimum panel refresh rate,151* round down the vtotal value to avoid stretching vblank over152* panel's vtotal boundary.153*/154v_total = div64_u64(div64_u64(((unsigned long long)(155frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),156stream->timing.h_total), 1000000);157} else if (refresh_in_uhz >= stream->timing.max_refresh_in_uhz) {158/* When the target refresh rate is the maximum panel refresh rate159* round up the vtotal value to prevent off-by-one error causing160* v_total_min to be below the panel's lower bound161*/162v_total = div64_u64(div64_u64(((unsigned long long)(163frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),164stream->timing.h_total) + (1000000 - 1), 1000000);165} else {166v_total = div64_u64(div64_u64(((unsigned long long)(167frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),168stream->timing.h_total) + 500000, 1000000);169}170171/* v_total cannot be less than nominal */172if (v_total < stream->timing.v_total) {173ASSERT(v_total < stream->timing.v_total);174v_total = stream->timing.v_total;175}176177return v_total;178}179180static unsigned int calc_v_total_from_duration(181const struct dc_stream_state *stream,182const struct mod_vrr_params *vrr,183unsigned int duration_in_us)184{185unsigned int v_total = 0;186187if (duration_in_us < vrr->min_duration_in_us)188duration_in_us = vrr->min_duration_in_us;189190if (duration_in_us > vrr->max_duration_in_us)191duration_in_us = vrr->max_duration_in_us;192193if (dc_is_hdmi_signal(stream->signal)) { // change for HDMI to comply with spec194uint32_t h_total_up_scaled;195196h_total_up_scaled = stream->timing.h_total * 10000;197v_total = div_u64((unsigned long long)duration_in_us198* stream->timing.pix_clk_100hz + (h_total_up_scaled - 1),199h_total_up_scaled); //ceiling for MMax and MMin for MVRR200} else {201v_total = div64_u64(div64_u64(((unsigned long long)(202duration_in_us) * (stream->timing.pix_clk_100hz / 10)),203stream->timing.h_total), 1000);204}205206/* v_total cannot be less than nominal */207if (v_total < stream->timing.v_total) {208ASSERT(v_total < stream->timing.v_total);209v_total = stream->timing.v_total;210}211212return v_total;213}214215static void update_v_total_for_static_ramp(216struct core_freesync *core_freesync,217const struct dc_stream_state *stream,218struct mod_vrr_params *in_out_vrr)219{220unsigned int v_total = 0;221unsigned int current_duration_in_us =222calc_duration_in_us_from_v_total(223stream, in_out_vrr,224in_out_vrr->adjust.v_total_max);225unsigned int target_duration_in_us =226calc_duration_in_us_from_refresh_in_uhz(227in_out_vrr->fixed.target_refresh_in_uhz);228bool ramp_direction_is_up = (current_duration_in_us >229target_duration_in_us) ? true : false;230231/* Calculate ratio between new and current frame duration with 3 digit */232unsigned int frame_duration_ratio = div64_u64(1000000,233(1000 + div64_u64(((unsigned long long)(234STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME) *235current_duration_in_us),2361000000)));237238/* Calculate delta between new and current frame duration in us */239unsigned int frame_duration_delta = div64_u64(((unsigned long long)(240current_duration_in_us) *241(1000 - frame_duration_ratio)), 1000);242243/* Adjust frame duration delta based on ratio between current and244* standard frame duration (frame duration at 60 Hz refresh rate).245*/246unsigned int ramp_rate_interpolated = div64_u64(((unsigned long long)(247frame_duration_delta) * current_duration_in_us), 16666);248249/* Going to a higher refresh rate (lower frame duration) */250if (ramp_direction_is_up) {251/* Reduce frame duration */252current_duration_in_us -= ramp_rate_interpolated;253254/* Adjust for frame duration below min */255if (current_duration_in_us <= target_duration_in_us) {256in_out_vrr->fixed.ramping_active = false;257in_out_vrr->fixed.ramping_done = true;258current_duration_in_us =259calc_duration_in_us_from_refresh_in_uhz(260in_out_vrr->fixed.target_refresh_in_uhz);261}262/* Going to a lower refresh rate (larger frame duration) */263} else {264/* Increase frame duration */265current_duration_in_us += ramp_rate_interpolated;266267/* Adjust for frame duration above max */268if (current_duration_in_us >= target_duration_in_us) {269in_out_vrr->fixed.ramping_active = false;270in_out_vrr->fixed.ramping_done = true;271current_duration_in_us =272calc_duration_in_us_from_refresh_in_uhz(273in_out_vrr->fixed.target_refresh_in_uhz);274}275}276277v_total = div64_u64(div64_u64(((unsigned long long)(278current_duration_in_us) * (stream->timing.pix_clk_100hz / 10)),279stream->timing.h_total), 1000);280281/* v_total cannot be less than nominal */282if (v_total < stream->timing.v_total)283v_total = stream->timing.v_total;284285in_out_vrr->adjust.v_total_min = v_total;286in_out_vrr->adjust.v_total_max = v_total;287}288289static void apply_below_the_range(struct core_freesync *core_freesync,290const struct dc_stream_state *stream,291unsigned int last_render_time_in_us,292struct mod_vrr_params *in_out_vrr)293{294unsigned int inserted_frame_duration_in_us = 0;295unsigned int mid_point_frames_ceil = 0;296unsigned int mid_point_frames_floor = 0;297unsigned int frame_time_in_us = 0;298unsigned int delta_from_mid_point_in_us_1 = 0xFFFFFFFF;299unsigned int delta_from_mid_point_in_us_2 = 0xFFFFFFFF;300unsigned int frames_to_insert = 0;301unsigned int delta_from_mid_point_delta_in_us;302unsigned int max_render_time_in_us =303in_out_vrr->max_duration_in_us - in_out_vrr->btr.margin_in_us;304305/* Program BTR */306if ((last_render_time_in_us + in_out_vrr->btr.margin_in_us / 2) < max_render_time_in_us) {307/* Exit Below the Range */308if (in_out_vrr->btr.btr_active) {309in_out_vrr->btr.frame_counter = 0;310in_out_vrr->btr.btr_active = false;311}312} else if (last_render_time_in_us > (max_render_time_in_us + in_out_vrr->btr.margin_in_us / 2)) {313/* Enter Below the Range */314if (!in_out_vrr->btr.btr_active)315in_out_vrr->btr.btr_active = true;316}317318/* BTR set to "not active" so disengage */319if (!in_out_vrr->btr.btr_active) {320in_out_vrr->btr.inserted_duration_in_us = 0;321in_out_vrr->btr.frames_to_insert = 0;322in_out_vrr->btr.frame_counter = 0;323324/* Restore FreeSync */325in_out_vrr->adjust.v_total_min =326mod_freesync_calc_v_total_from_refresh(stream,327in_out_vrr->max_refresh_in_uhz);328in_out_vrr->adjust.v_total_max =329mod_freesync_calc_v_total_from_refresh(stream,330in_out_vrr->min_refresh_in_uhz);331/* BTR set to "active" so engage */332} else {333334/* Calculate number of midPoint frames that could fit within335* the render time interval - take ceil of this value336*/337mid_point_frames_ceil = (last_render_time_in_us +338in_out_vrr->btr.mid_point_in_us - 1) /339in_out_vrr->btr.mid_point_in_us;340341if (mid_point_frames_ceil > 0) {342frame_time_in_us = last_render_time_in_us /343mid_point_frames_ceil;344delta_from_mid_point_in_us_1 =345(in_out_vrr->btr.mid_point_in_us >346frame_time_in_us) ?347(in_out_vrr->btr.mid_point_in_us - frame_time_in_us) :348(frame_time_in_us - in_out_vrr->btr.mid_point_in_us);349}350351/* Calculate number of midPoint frames that could fit within352* the render time interval - take floor of this value353*/354mid_point_frames_floor = last_render_time_in_us /355in_out_vrr->btr.mid_point_in_us;356357if (mid_point_frames_floor > 0) {358359frame_time_in_us = last_render_time_in_us /360mid_point_frames_floor;361delta_from_mid_point_in_us_2 =362(in_out_vrr->btr.mid_point_in_us >363frame_time_in_us) ?364(in_out_vrr->btr.mid_point_in_us - frame_time_in_us) :365(frame_time_in_us - in_out_vrr->btr.mid_point_in_us);366}367368/* Choose number of frames to insert based on how close it369* can get to the mid point of the variable range.370* - Delta for CEIL: delta_from_mid_point_in_us_1371* - Delta for FLOOR: delta_from_mid_point_in_us_2372*/373if (mid_point_frames_ceil &&374(last_render_time_in_us / mid_point_frames_ceil) <375in_out_vrr->min_duration_in_us) {376/* Check for out of range.377* If using CEIL produces a value that is out of range,378* then we are forced to use FLOOR.379*/380frames_to_insert = mid_point_frames_floor;381} else if (mid_point_frames_floor < 2) {382/* Check if FLOOR would result in non-LFC. In this case383* choose to use CEIL384*/385frames_to_insert = mid_point_frames_ceil;386} else if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) {387/* If choosing CEIL results in a frame duration that is388* closer to the mid point of the range.389* Choose CEIL390*/391frames_to_insert = mid_point_frames_ceil;392} else {393/* If choosing FLOOR results in a frame duration that is394* closer to the mid point of the range.395* Choose FLOOR396*/397frames_to_insert = mid_point_frames_floor;398}399400/* Prefer current frame multiplier when BTR is enabled unless it drifts401* too far from the midpoint402*/403if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) {404delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_2 -405delta_from_mid_point_in_us_1;406} else {407delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_1 -408delta_from_mid_point_in_us_2;409}410if (in_out_vrr->btr.frames_to_insert != 0 &&411delta_from_mid_point_delta_in_us < BTR_DRIFT_MARGIN) {412if (((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) <413max_render_time_in_us) &&414((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) >415in_out_vrr->min_duration_in_us))416frames_to_insert = in_out_vrr->btr.frames_to_insert;417}418419/* Either we've calculated the number of frames to insert,420* or we need to insert min duration frames421*/422if (frames_to_insert &&423(last_render_time_in_us / frames_to_insert) <424in_out_vrr->min_duration_in_us){425frames_to_insert -= (frames_to_insert > 1) ?4261 : 0;427}428429if (frames_to_insert > 0)430inserted_frame_duration_in_us = last_render_time_in_us /431frames_to_insert;432433if (inserted_frame_duration_in_us < in_out_vrr->min_duration_in_us)434inserted_frame_duration_in_us = in_out_vrr->min_duration_in_us;435436/* Cache the calculated variables */437in_out_vrr->btr.inserted_duration_in_us =438inserted_frame_duration_in_us;439in_out_vrr->btr.frames_to_insert = frames_to_insert;440in_out_vrr->btr.frame_counter = frames_to_insert;441}442}443444static void apply_fixed_refresh(struct core_freesync *core_freesync,445const struct dc_stream_state *stream,446unsigned int last_render_time_in_us,447struct mod_vrr_params *in_out_vrr)448{449bool update = false;450unsigned int max_render_time_in_us = in_out_vrr->max_duration_in_us;451452/* Compute the exit refresh rate and exit frame duration */453unsigned int exit_refresh_rate_in_milli_hz = ((1000000000/max_render_time_in_us)454+ (1000*FIXED_REFRESH_EXIT_MARGIN_IN_HZ));455unsigned int exit_frame_duration_in_us = 1000000000/exit_refresh_rate_in_milli_hz;456457if (last_render_time_in_us < exit_frame_duration_in_us) {458/* Exit Fixed Refresh mode */459if (in_out_vrr->fixed.fixed_active) {460in_out_vrr->fixed.frame_counter++;461462if (in_out_vrr->fixed.frame_counter >463FIXED_REFRESH_EXIT_FRAME_COUNT) {464in_out_vrr->fixed.frame_counter = 0;465in_out_vrr->fixed.fixed_active = false;466in_out_vrr->fixed.target_refresh_in_uhz = 0;467update = true;468}469} else470in_out_vrr->fixed.frame_counter = 0;471} else if (last_render_time_in_us > max_render_time_in_us) {472/* Enter Fixed Refresh mode */473if (!in_out_vrr->fixed.fixed_active) {474in_out_vrr->fixed.frame_counter++;475476if (in_out_vrr->fixed.frame_counter >477FIXED_REFRESH_ENTER_FRAME_COUNT) {478in_out_vrr->fixed.frame_counter = 0;479in_out_vrr->fixed.fixed_active = true;480in_out_vrr->fixed.target_refresh_in_uhz =481in_out_vrr->max_refresh_in_uhz;482update = true;483}484} else485in_out_vrr->fixed.frame_counter = 0;486}487488if (update) {489if (in_out_vrr->fixed.fixed_active) {490in_out_vrr->adjust.v_total_min =491mod_freesync_calc_v_total_from_refresh(492stream, in_out_vrr->max_refresh_in_uhz);493in_out_vrr->adjust.v_total_max =494in_out_vrr->adjust.v_total_min;495} else {496in_out_vrr->adjust.v_total_min =497mod_freesync_calc_v_total_from_refresh(stream,498in_out_vrr->max_refresh_in_uhz);499in_out_vrr->adjust.v_total_max =500mod_freesync_calc_v_total_from_refresh(stream,501in_out_vrr->min_refresh_in_uhz);502}503}504}505506static void determine_flip_interval_workaround_req(struct mod_vrr_params *in_vrr,507unsigned int curr_time_stamp_in_us)508{509in_vrr->flip_interval.vsync_to_flip_in_us = curr_time_stamp_in_us -510in_vrr->flip_interval.v_update_timestamp_in_us;511512/* Determine conditions for stopping workaround */513if (in_vrr->flip_interval.flip_interval_workaround_active &&514in_vrr->flip_interval.vsyncs_between_flip < VSYNCS_BETWEEN_FLIP_THRESHOLD &&515in_vrr->flip_interval.vsync_to_flip_in_us > FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US) {516in_vrr->flip_interval.flip_interval_detect_counter = 0;517in_vrr->flip_interval.program_flip_interval_workaround = true;518in_vrr->flip_interval.flip_interval_workaround_active = false;519} else {520/* Determine conditions for starting workaround */521if (in_vrr->flip_interval.vsyncs_between_flip >= VSYNCS_BETWEEN_FLIP_THRESHOLD &&522in_vrr->flip_interval.vsync_to_flip_in_us < FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US) {523/* Increase flip interval counter we have 2 vsyncs between flips and524* vsync to flip interval is less than 500us525*/526in_vrr->flip_interval.flip_interval_detect_counter++;527if (in_vrr->flip_interval.flip_interval_detect_counter > FREESYNC_CONSEC_FLIP_AFTER_VSYNC) {528/* Start workaround if we detect 5 consecutive instances of the above case */529in_vrr->flip_interval.program_flip_interval_workaround = true;530in_vrr->flip_interval.flip_interval_workaround_active = true;531}532} else {533/* Reset the flip interval counter if we condition is no longer met */534in_vrr->flip_interval.flip_interval_detect_counter = 0;535}536}537538in_vrr->flip_interval.vsyncs_between_flip = 0;539}540541static bool vrr_settings_require_update(struct core_freesync *core_freesync,542struct mod_freesync_config *in_config,543unsigned int min_refresh_in_uhz,544unsigned int max_refresh_in_uhz,545struct mod_vrr_params *in_vrr)546{547if (in_vrr->state != in_config->state) {548return true;549} else if (in_vrr->state == VRR_STATE_ACTIVE_FIXED &&550in_vrr->fixed.target_refresh_in_uhz !=551in_config->fixed_refresh_in_uhz) {552return true;553} else if (in_vrr->min_refresh_in_uhz != min_refresh_in_uhz) {554return true;555} else if (in_vrr->max_refresh_in_uhz != max_refresh_in_uhz) {556return true;557}558559return false;560}561562static void build_vrr_infopacket_data_v1(const struct mod_vrr_params *vrr,563struct dc_info_packet *infopacket,564bool freesync_on_desktop)565{566/* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */567infopacket->sb[1] = 0x1A;568569/* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */570infopacket->sb[2] = 0x00;571572/* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */573infopacket->sb[3] = 0x00;574575/* PB4 = Reserved */576577/* PB5 = Reserved */578579/* PB6 = [Bits 7:3 = Reserved] */580581/* PB6 = [Bit 0 = FreeSync Supported] */582if (vrr->state != VRR_STATE_UNSUPPORTED)583infopacket->sb[6] |= 0x01;584585/* PB6 = [Bit 1 = FreeSync Enabled] */586if (vrr->state != VRR_STATE_DISABLED &&587vrr->state != VRR_STATE_UNSUPPORTED)588infopacket->sb[6] |= 0x02;589590if (freesync_on_desktop) {591/* PB6 = [Bit 2 = FreeSync Active] */592if (vrr->state != VRR_STATE_DISABLED &&593vrr->state != VRR_STATE_UNSUPPORTED)594infopacket->sb[6] |= 0x04;595} else {596if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||597vrr->state == VRR_STATE_ACTIVE_FIXED)598infopacket->sb[6] |= 0x04;599}600601// For v1 & 2 infoframes program nominal if non-fs mode, otherwise full range602/* PB7 = FreeSync Minimum refresh rate (Hz) */603if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||604vrr->state == VRR_STATE_ACTIVE_FIXED) {605infopacket->sb[7] = (unsigned char)((vrr->min_refresh_in_uhz + 500000) / 1000000);606} else {607infopacket->sb[7] = (unsigned char)((vrr->max_refresh_in_uhz + 500000) / 1000000);608}609610/* PB8 = FreeSync Maximum refresh rate (Hz)611* Note: We should never go above the field rate of the mode timing set.612*/613infopacket->sb[8] = (unsigned char)((vrr->max_refresh_in_uhz + 500000) / 1000000);614}615616static void build_vrr_infopacket_data_v3(const struct mod_vrr_params *vrr,617struct dc_info_packet *infopacket,618bool freesync_on_desktop)619{620unsigned int min_refresh;621unsigned int max_refresh;622unsigned int fixed_refresh;623unsigned int min_programmed;624625/* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */626infopacket->sb[1] = 0x1A;627628/* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */629infopacket->sb[2] = 0x00;630631/* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */632infopacket->sb[3] = 0x00;633634/* PB4 = Reserved */635636/* PB5 = Reserved */637638/* PB6 = [Bits 7:3 = Reserved] */639640/* PB6 = [Bit 0 = FreeSync Supported] */641if (vrr->state != VRR_STATE_UNSUPPORTED)642infopacket->sb[6] |= 0x01;643644/* PB6 = [Bit 1 = FreeSync Enabled] */645if (vrr->state != VRR_STATE_DISABLED &&646vrr->state != VRR_STATE_UNSUPPORTED)647infopacket->sb[6] |= 0x02;648649/* PB6 = [Bit 2 = FreeSync Active] */650if (freesync_on_desktop) {651if (vrr->state != VRR_STATE_DISABLED &&652vrr->state != VRR_STATE_UNSUPPORTED)653infopacket->sb[6] |= 0x04;654} else {655if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||656vrr->state == VRR_STATE_ACTIVE_FIXED)657infopacket->sb[6] |= 0x04;658}659660min_refresh = (vrr->min_refresh_in_uhz + 500000) / 1000000;661max_refresh = (vrr->max_refresh_in_uhz + 500000) / 1000000;662fixed_refresh = (vrr->fixed_refresh_in_uhz + 500000) / 1000000;663664min_programmed = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? fixed_refresh :665(vrr->state == VRR_STATE_ACTIVE_VARIABLE) ? min_refresh :666(vrr->state == VRR_STATE_INACTIVE) ? min_refresh :667max_refresh; // Non-fs case, program nominal range668669/* PB7 = FreeSync Minimum refresh rate (Hz) */670infopacket->sb[7] = min_programmed & 0xFF;671672/* PB8 = FreeSync Maximum refresh rate (Hz) */673infopacket->sb[8] = max_refresh & 0xFF;674675/* PB11 : MSB FreeSync Minimum refresh rate [Hz] - bits 9:8 */676infopacket->sb[11] = (min_programmed >> 8) & 0x03;677678/* PB12 : MSB FreeSync Maximum refresh rate [Hz] - bits 9:8 */679infopacket->sb[12] = (max_refresh >> 8) & 0x03;680681/* PB16 : Reserved bits 7:1, FixedRate bit 0 */682infopacket->sb[16] = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? 1 : 0;683}684685static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf,686struct dc_info_packet *infopacket)687{688if (app_tf != TRANSFER_FUNC_UNKNOWN) {689infopacket->valid = true;690691if (app_tf == TRANSFER_FUNC_PQ2084)692infopacket->sb[9] |= 0x20; // PB9 = [Bit 5 = PQ EOTF Active]693else {694infopacket->sb[6] |= 0x08; // PB6 = [Bit 3 = Native Color Active]695if (app_tf == TRANSFER_FUNC_GAMMA_22)696infopacket->sb[9] |= 0x04; // PB9 = [Bit 2 = Gamma 2.2 EOTF Active]697}698}699}700701static void build_vrr_infopacket_header_v1(enum signal_type signal,702struct dc_info_packet *infopacket,703unsigned int *payload_size)704{705if (dc_is_hdmi_signal(signal)) {706707/* HEADER */708709/* HB0 = Packet Type = 0x83 (Source Product710* Descriptor InfoFrame)711*/712infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;713714/* HB1 = Version = 0x01 */715infopacket->hb1 = 0x01;716717/* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */718infopacket->hb2 = 0x08;719720*payload_size = 0x08;721722} else if (dc_is_dp_signal(signal)) {723724/* HEADER */725726/* HB0 = Secondary-data Packet ID = 0 - Only non-zero727* when used to associate audio related info packets728*/729infopacket->hb0 = 0x00;730731/* HB1 = Packet Type = 0x83 (Source Product732* Descriptor InfoFrame)733*/734infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;735736/* HB2 = [Bits 7:0 = Least significant eight bits -737* For INFOFRAME, the value must be 1Bh]738*/739infopacket->hb2 = 0x1B;740741/* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]742* [Bits 1:0 = Most significant two bits = 0x00]743*/744infopacket->hb3 = 0x04;745746*payload_size = 0x1B;747}748}749750static void build_vrr_infopacket_header_v2(enum signal_type signal,751struct dc_info_packet *infopacket,752unsigned int *payload_size)753{754if (dc_is_hdmi_signal(signal)) {755756/* HEADER */757758/* HB0 = Packet Type = 0x83 (Source Product759* Descriptor InfoFrame)760*/761infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;762763/* HB1 = Version = 0x02 */764infopacket->hb1 = 0x02;765766/* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x09] */767infopacket->hb2 = 0x09;768769*payload_size = 0x09;770} else if (dc_is_dp_signal(signal)) {771772/* HEADER */773774/* HB0 = Secondary-data Packet ID = 0 - Only non-zero775* when used to associate audio related info packets776*/777infopacket->hb0 = 0x00;778779/* HB1 = Packet Type = 0x83 (Source Product780* Descriptor InfoFrame)781*/782infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;783784/* HB2 = [Bits 7:0 = Least significant eight bits -785* For INFOFRAME, the value must be 1Bh]786*/787infopacket->hb2 = 0x1B;788789/* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x2]790* [Bits 1:0 = Most significant two bits = 0x00]791*/792infopacket->hb3 = 0x08;793794*payload_size = 0x1B;795}796}797798static void build_vrr_infopacket_header_v3(enum signal_type signal,799struct dc_info_packet *infopacket,800unsigned int *payload_size)801{802unsigned char version;803804version = 3;805if (dc_is_hdmi_signal(signal)) {806807/* HEADER */808809/* HB0 = Packet Type = 0x83 (Source Product810* Descriptor InfoFrame)811*/812infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;813814/* HB1 = Version = 0x03 */815infopacket->hb1 = version;816817/* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length] */818infopacket->hb2 = 0x10;819820*payload_size = 0x10;821} else if (dc_is_dp_signal(signal)) {822823/* HEADER */824825/* HB0 = Secondary-data Packet ID = 0 - Only non-zero826* when used to associate audio related info packets827*/828infopacket->hb0 = 0x00;829830/* HB1 = Packet Type = 0x83 (Source Product831* Descriptor InfoFrame)832*/833infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;834835/* HB2 = [Bits 7:0 = Least significant eight bits -836* For INFOFRAME, the value must be 1Bh]837*/838infopacket->hb2 = 0x1B;839840/* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x2]841* [Bits 1:0 = Most significant two bits = 0x00]842*/843844infopacket->hb3 = (version & 0x3F) << 2;845846*payload_size = 0x1B;847}848}849850static void build_vrr_infopacket_checksum(unsigned int *payload_size,851struct dc_info_packet *infopacket)852{853/* Calculate checksum */854unsigned int idx = 0;855unsigned char checksum = 0;856857checksum += infopacket->hb0;858checksum += infopacket->hb1;859checksum += infopacket->hb2;860checksum += infopacket->hb3;861862for (idx = 1; idx <= *payload_size; idx++)863checksum += infopacket->sb[idx];864865/* PB0 = Checksum (one byte complement) */866infopacket->sb[0] = (unsigned char)(0x100 - checksum);867868infopacket->valid = true;869}870871static void build_vrr_infopacket_v1(enum signal_type signal,872const struct mod_vrr_params *vrr,873struct dc_info_packet *infopacket,874bool freesync_on_desktop)875{876/* SPD info packet for FreeSync */877unsigned int payload_size = 0;878879build_vrr_infopacket_header_v1(signal, infopacket, &payload_size);880build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop);881build_vrr_infopacket_checksum(&payload_size, infopacket);882883infopacket->valid = true;884}885886static void build_vrr_infopacket_v2(enum signal_type signal,887const struct mod_vrr_params *vrr,888enum color_transfer_func app_tf,889struct dc_info_packet *infopacket,890bool freesync_on_desktop)891{892unsigned int payload_size = 0;893894build_vrr_infopacket_header_v2(signal, infopacket, &payload_size);895build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop);896897build_vrr_infopacket_fs2_data(app_tf, infopacket);898899build_vrr_infopacket_checksum(&payload_size, infopacket);900901infopacket->valid = true;902}903904static void build_vrr_infopacket_v3(enum signal_type signal,905const struct mod_vrr_params *vrr,906enum color_transfer_func app_tf,907struct dc_info_packet *infopacket,908bool freesync_on_desktop)909{910unsigned int payload_size = 0;911912build_vrr_infopacket_header_v3(signal, infopacket, &payload_size);913build_vrr_infopacket_data_v3(vrr, infopacket, freesync_on_desktop);914915build_vrr_infopacket_fs2_data(app_tf, infopacket);916917build_vrr_infopacket_checksum(&payload_size, infopacket);918919infopacket->valid = true;920}921922static void build_vrr_infopacket_sdp_v1_3(enum vrr_packet_type packet_type,923struct dc_info_packet *infopacket)924{925uint8_t idx = 0, size = 0;926927size = ((packet_type == PACKET_TYPE_FS_V1) ? 0x08 :928(packet_type == PACKET_TYPE_FS_V3) ? 0x10 :9290x09);930931for (idx = infopacket->hb2; idx > 1; idx--) // Data Byte Count: 0x1B932infopacket->sb[idx] = infopacket->sb[idx-1];933934infopacket->sb[1] = size; // Length935infopacket->sb[0] = (infopacket->hb3 >> 2) & 0x3F;//Version936infopacket->hb3 = (0x13 << 2); // Header,SDP 1.3937infopacket->hb2 = 0x1D;938}939940void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,941const struct dc_stream_state *stream,942const struct mod_vrr_params *vrr,943enum vrr_packet_type packet_type,944enum color_transfer_func app_tf,945struct dc_info_packet *infopacket,946bool pack_sdp_v1_3)947{948/* SPD info packet for FreeSync949* VTEM info packet for HdmiVRR950* Check if Freesync is supported. Return if false. If true,951* set the corresponding bit in the info packet952*/953if (!vrr->send_info_frame)954return;955956switch (packet_type) {957case PACKET_TYPE_FS_V3:958build_vrr_infopacket_v3(stream->signal, vrr, app_tf, infopacket, stream->freesync_on_desktop);959break;960case PACKET_TYPE_FS_V2:961build_vrr_infopacket_v2(stream->signal, vrr, app_tf, infopacket, stream->freesync_on_desktop);962break;963case PACKET_TYPE_VRR:964case PACKET_TYPE_FS_V1:965default:966build_vrr_infopacket_v1(stream->signal, vrr, infopacket, stream->freesync_on_desktop);967}968969if (true == pack_sdp_v1_3 &&970true == dc_is_dp_signal(stream->signal) &&971packet_type != PACKET_TYPE_VRR &&972packet_type != PACKET_TYPE_VTEM)973build_vrr_infopacket_sdp_v1_3(packet_type, infopacket);974}975976void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,977const struct dc_stream_state *stream,978struct mod_freesync_config *in_config,979struct mod_vrr_params *in_out_vrr)980{981struct core_freesync *core_freesync = NULL;982unsigned long long nominal_field_rate_in_uhz = 0;983unsigned long long rounded_nominal_in_uhz = 0;984unsigned int refresh_range = 0;985unsigned long long min_refresh_in_uhz = 0;986unsigned long long max_refresh_in_uhz = 0;987unsigned long long min_hardware_refresh_in_uhz = 0;988989if (mod_freesync == NULL)990return;991992core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);993994/* Calculate nominal field rate for stream */995nominal_field_rate_in_uhz =996mod_freesync_calc_nominal_field_rate(stream);997998if (stream->ctx->dc->caps.max_v_total != 0 && stream->timing.h_total != 0) {999min_hardware_refresh_in_uhz = div64_u64((stream->timing.pix_clk_100hz * 100000000ULL),1000(stream->timing.h_total * (long long)calc_max_hardware_v_total(stream)));1001}1002/* Limit minimum refresh rate to what can be supported by hardware */1003min_refresh_in_uhz = min_hardware_refresh_in_uhz > in_config->min_refresh_in_uhz ?1004min_hardware_refresh_in_uhz : in_config->min_refresh_in_uhz;1005max_refresh_in_uhz = in_config->max_refresh_in_uhz;10061007/* Full range may be larger than current video timing, so cap at nominal */1008if (max_refresh_in_uhz > nominal_field_rate_in_uhz)1009max_refresh_in_uhz = nominal_field_rate_in_uhz;10101011/* Full range may be larger than current video timing, so cap at nominal */1012if (min_refresh_in_uhz > max_refresh_in_uhz)1013min_refresh_in_uhz = max_refresh_in_uhz;10141015/* If a monitor reports exactly max refresh of 2x of min, enforce it on nominal */1016rounded_nominal_in_uhz =1017div_u64(nominal_field_rate_in_uhz + 50000, 100000) * 100000;1018if (in_config->max_refresh_in_uhz == (2 * in_config->min_refresh_in_uhz) &&1019in_config->max_refresh_in_uhz == rounded_nominal_in_uhz)1020min_refresh_in_uhz = div_u64(nominal_field_rate_in_uhz, 2);10211022if (!vrr_settings_require_update(core_freesync,1023in_config, (unsigned int)min_refresh_in_uhz, (unsigned int)max_refresh_in_uhz,1024in_out_vrr))1025return;10261027in_out_vrr->state = in_config->state;1028in_out_vrr->send_info_frame = in_config->vsif_supported;10291030if (in_config->state == VRR_STATE_UNSUPPORTED) {1031in_out_vrr->state = VRR_STATE_UNSUPPORTED;1032in_out_vrr->supported = false;1033in_out_vrr->adjust.v_total_min = stream->timing.v_total;1034in_out_vrr->adjust.v_total_max = stream->timing.v_total;10351036return;10371038} else {1039in_out_vrr->min_refresh_in_uhz = (unsigned int)min_refresh_in_uhz;1040in_out_vrr->max_duration_in_us =1041calc_duration_in_us_from_refresh_in_uhz(1042(unsigned int)min_refresh_in_uhz);10431044in_out_vrr->max_refresh_in_uhz = (unsigned int)max_refresh_in_uhz;1045in_out_vrr->min_duration_in_us =1046calc_duration_in_us_from_refresh_in_uhz(1047(unsigned int)max_refresh_in_uhz);10481049if (in_config->state == VRR_STATE_ACTIVE_FIXED)1050in_out_vrr->fixed_refresh_in_uhz = in_config->fixed_refresh_in_uhz;1051else1052in_out_vrr->fixed_refresh_in_uhz = 0;10531054refresh_range = div_u64(in_out_vrr->max_refresh_in_uhz + 500000, 1000000) -1055div_u64(in_out_vrr->min_refresh_in_uhz + 500000, 1000000);10561057in_out_vrr->supported = true;1058}10591060in_out_vrr->fixed.ramping_active = in_config->ramping;10611062in_out_vrr->btr.btr_enabled = in_config->btr;10631064if (in_out_vrr->max_refresh_in_uhz < (2 * in_out_vrr->min_refresh_in_uhz))1065in_out_vrr->btr.btr_enabled = false;1066else {1067in_out_vrr->btr.margin_in_us = in_out_vrr->max_duration_in_us -10682 * in_out_vrr->min_duration_in_us;1069if (in_out_vrr->btr.margin_in_us > BTR_MAX_MARGIN)1070in_out_vrr->btr.margin_in_us = BTR_MAX_MARGIN;1071}10721073in_out_vrr->btr.btr_active = false;1074in_out_vrr->btr.inserted_duration_in_us = 0;1075in_out_vrr->btr.frames_to_insert = 0;1076in_out_vrr->btr.frame_counter = 0;1077in_out_vrr->fixed.fixed_active = false;1078in_out_vrr->fixed.target_refresh_in_uhz = 0;10791080in_out_vrr->btr.mid_point_in_us =1081(in_out_vrr->min_duration_in_us +1082in_out_vrr->max_duration_in_us) / 2;10831084if (in_out_vrr->state == VRR_STATE_UNSUPPORTED) {1085in_out_vrr->adjust.v_total_min = stream->timing.v_total;1086in_out_vrr->adjust.v_total_max = stream->timing.v_total;1087} else if (in_out_vrr->state == VRR_STATE_DISABLED) {1088in_out_vrr->adjust.v_total_min = stream->timing.v_total;1089in_out_vrr->adjust.v_total_max = stream->timing.v_total;1090} else if (in_out_vrr->state == VRR_STATE_INACTIVE) {1091in_out_vrr->adjust.v_total_min = stream->timing.v_total;1092in_out_vrr->adjust.v_total_max = stream->timing.v_total;1093} else if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&1094refresh_range >= MIN_REFRESH_RANGE) {10951096in_out_vrr->adjust.v_total_min =1097mod_freesync_calc_v_total_from_refresh(stream,1098in_out_vrr->max_refresh_in_uhz);1099in_out_vrr->adjust.v_total_max =1100mod_freesync_calc_v_total_from_refresh(stream,1101in_out_vrr->min_refresh_in_uhz);1102} else if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED) {1103in_out_vrr->fixed.target_refresh_in_uhz =1104in_out_vrr->fixed_refresh_in_uhz;1105if (in_out_vrr->fixed.ramping_active &&1106in_out_vrr->fixed.fixed_active) {1107/* Do not update vtotals if ramping is already active1108* in order to continue ramp from current refresh.1109*/1110in_out_vrr->fixed.fixed_active = true;1111} else {1112in_out_vrr->fixed.fixed_active = true;1113in_out_vrr->adjust.v_total_min =1114mod_freesync_calc_v_total_from_refresh(stream,1115in_out_vrr->fixed.target_refresh_in_uhz);1116in_out_vrr->adjust.v_total_max =1117in_out_vrr->adjust.v_total_min;1118}1119} else {1120in_out_vrr->state = VRR_STATE_INACTIVE;1121in_out_vrr->adjust.v_total_min = stream->timing.v_total;1122in_out_vrr->adjust.v_total_max = stream->timing.v_total;1123}11241125in_out_vrr->adjust.allow_otg_v_count_halt = (in_config->state == VRR_STATE_ACTIVE_FIXED) ? true : false;1126}11271128void mod_freesync_handle_preflip(struct mod_freesync *mod_freesync,1129const struct dc_plane_state *plane,1130const struct dc_stream_state *stream,1131unsigned int curr_time_stamp_in_us,1132struct mod_vrr_params *in_out_vrr)1133{1134struct core_freesync *core_freesync = NULL;1135unsigned int last_render_time_in_us = 0;11361137if (mod_freesync == NULL)1138return;11391140core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);11411142if (in_out_vrr->supported &&1143in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE) {11441145last_render_time_in_us = curr_time_stamp_in_us -1146plane->time.prev_update_time_in_us;11471148if (in_out_vrr->btr.btr_enabled) {1149apply_below_the_range(core_freesync,1150stream,1151last_render_time_in_us,1152in_out_vrr);1153} else {1154apply_fixed_refresh(core_freesync,1155stream,1156last_render_time_in_us,1157in_out_vrr);1158}11591160determine_flip_interval_workaround_req(in_out_vrr,1161curr_time_stamp_in_us);11621163}1164}11651166void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,1167const struct dc_stream_state *stream,1168struct mod_vrr_params *in_out_vrr)1169{1170struct core_freesync *core_freesync = NULL;1171unsigned int cur_timestamp_in_us;1172unsigned long long cur_tick;11731174if ((mod_freesync == NULL) || (stream == NULL) || (in_out_vrr == NULL))1175return;11761177core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);11781179if (in_out_vrr->supported == false)1180return;11811182cur_tick = dm_get_timestamp(core_freesync->dc->ctx);1183cur_timestamp_in_us = (unsigned int)1184div_u64(dm_get_elapse_time_in_ns(core_freesync->dc->ctx, cur_tick, 0), 1000);11851186in_out_vrr->flip_interval.vsyncs_between_flip++;1187in_out_vrr->flip_interval.v_update_timestamp_in_us = cur_timestamp_in_us;11881189if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&1190(in_out_vrr->flip_interval.flip_interval_workaround_active ||1191(!in_out_vrr->flip_interval.flip_interval_workaround_active &&1192in_out_vrr->flip_interval.program_flip_interval_workaround))) {1193// set freesync vmin vmax to nominal for workaround1194in_out_vrr->adjust.v_total_min =1195mod_freesync_calc_v_total_from_refresh(1196stream, in_out_vrr->max_refresh_in_uhz);1197in_out_vrr->adjust.v_total_max =1198in_out_vrr->adjust.v_total_min;1199in_out_vrr->flip_interval.program_flip_interval_workaround = false;1200in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup = true;1201return;1202}12031204if (in_out_vrr->state != VRR_STATE_ACTIVE_VARIABLE &&1205in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup) {1206in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup = false;1207in_out_vrr->flip_interval.flip_interval_detect_counter = 0;1208in_out_vrr->flip_interval.vsyncs_between_flip = 0;1209in_out_vrr->flip_interval.vsync_to_flip_in_us = 0;1210}12111212/* Below the Range Logic */12131214/* Only execute if in fullscreen mode */1215if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&1216in_out_vrr->btr.btr_active) {1217/* TODO: pass in flag for Pre-DCE12 ASIC1218* in order for frame variable duration to take affect,1219* it needs to be done one VSYNC early, which is at1220* frameCounter == 1.1221* For DCE12 and newer updates to V_TOTAL_MIN/MAX1222* will take affect on current frame1223*/1224if (in_out_vrr->btr.frames_to_insert ==1225in_out_vrr->btr.frame_counter) {1226in_out_vrr->adjust.v_total_min =1227calc_v_total_from_duration(stream,1228in_out_vrr,1229in_out_vrr->btr.inserted_duration_in_us);1230in_out_vrr->adjust.v_total_max =1231in_out_vrr->adjust.v_total_min;1232}12331234if (in_out_vrr->btr.frame_counter > 0)1235in_out_vrr->btr.frame_counter--;12361237/* Restore FreeSync */1238if (in_out_vrr->btr.frame_counter == 0) {1239in_out_vrr->adjust.v_total_min =1240mod_freesync_calc_v_total_from_refresh(stream,1241in_out_vrr->max_refresh_in_uhz);1242in_out_vrr->adjust.v_total_max =1243mod_freesync_calc_v_total_from_refresh(stream,1244in_out_vrr->min_refresh_in_uhz);1245}1246}12471248/* If in fullscreen freesync mode or in video, do not program1249* static screen ramp values1250*/1251if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE)1252in_out_vrr->fixed.ramping_active = false;12531254/* Gradual Static Screen Ramping Logic1255* Execute if ramp is active and user enabled freesync static screen1256*/1257if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED &&1258in_out_vrr->fixed.ramping_active) {1259update_v_total_for_static_ramp(1260core_freesync, stream, in_out_vrr);1261}1262}12631264unsigned long long mod_freesync_calc_nominal_field_rate(1265const struct dc_stream_state *stream)1266{1267unsigned long long nominal_field_rate_in_uhz = 0;1268unsigned int total = stream->timing.h_total * stream->timing.v_total;12691270/* Calculate nominal field rate for stream, rounded up to nearest integer */1271nominal_field_rate_in_uhz = stream->timing.pix_clk_100hz;1272nominal_field_rate_in_uhz *= 100000000ULL;12731274nominal_field_rate_in_uhz = div_u64(nominal_field_rate_in_uhz, total);12751276return nominal_field_rate_in_uhz;1277}12781279bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr)1280{1281return (pVrr->state != VRR_STATE_UNSUPPORTED) && (pVrr->state != VRR_STATE_DISABLED);1282}128312841285