Path: blob/master/drivers/gpu/drm/amd/include/aldebaran_ip_offset.h
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/*1* Copyright (C) 2020 Advanced Micro Devices, Inc.2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice shall be included11* in all copies or substantial portions of the Software.12*13* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS14* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,15* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL16* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN17* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN18* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.19*/20#ifndef _aldebaran_ip_offset_HEADER21#define _aldebaran_ip_offset_HEADER2223#define MAX_INSTANCE 724#define MAX_SEGMENT 62526struct IP_BASE_INSTANCE {27unsigned int segment[MAX_SEGMENT];28};2930struct IP_BASE {31struct IP_BASE_INSTANCE instance[MAX_INSTANCE];32} __maybe_unused;3334static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0x02408C00, 0, 0, 0, 0 } },35{ { 0, 0, 0, 0, 0, 0 } },36{ { 0, 0, 0, 0, 0, 0 } },37{ { 0, 0, 0, 0, 0, 0 } },38{ { 0, 0, 0, 0, 0, 0 } },39{ { 0, 0, 0, 0, 0, 0 } },40{ { 0, 0, 0, 0, 0, 0 } } } };41static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },42{ { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },43{ { 0x00017000, 0x02402000, 0, 0, 0, 0 } },44{ { 0x00017200, 0x02402400, 0, 0, 0, 0 } },45{ { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },46{ { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },47{ { 0x00017E00, 0x0240BC00, 0, 0, 0, 0 } } } };48static const struct IP_BASE DBGU_IO0_BASE = { { { { 0x000001E0, 0x0240B400, 0, 0, 0, 0 } },49{ { 0x00000260, 0x02413C00, 0, 0, 0, 0 } },50{ { 0x00000280, 0x02416000, 0, 0, 0, 0 } },51{ { 0, 0, 0, 0, 0, 0 } },52{ { 0, 0, 0, 0, 0, 0 } },53{ { 0, 0, 0, 0, 0, 0 } },54{ { 0, 0, 0, 0, 0, 0 } } } };55static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0x07C00000, 0, 0, 0 } },56{ { 0, 0, 0, 0, 0, 0 } },57{ { 0, 0, 0, 0, 0, 0 } },58{ { 0, 0, 0, 0, 0, 0 } },59{ { 0, 0, 0, 0, 0, 0 } },60{ { 0, 0, 0, 0, 0, 0 } },61{ { 0, 0, 0, 0, 0, 0 } } } };62static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } },63{ { 0, 0, 0, 0, 0, 0 } },64{ { 0, 0, 0, 0, 0, 0 } },65{ { 0, 0, 0, 0, 0, 0 } },66{ { 0, 0, 0, 0, 0, 0 } },67{ { 0, 0, 0, 0, 0, 0 } },68{ { 0, 0, 0, 0, 0, 0 } } } };69static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0x02402C00, 0, 0, 0 } },70{ { 0, 0, 0, 0, 0, 0 } },71{ { 0, 0, 0, 0, 0, 0 } },72{ { 0, 0, 0, 0, 0, 0 } },73{ { 0, 0, 0, 0, 0, 0 } },74{ { 0, 0, 0, 0, 0, 0 } },75{ { 0, 0, 0, 0, 0, 0 } } } };76static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } },77{ { 0, 0, 0, 0, 0, 0 } },78{ { 0, 0, 0, 0, 0, 0 } },79{ { 0, 0, 0, 0, 0, 0 } },80{ { 0, 0, 0, 0, 0, 0 } },81{ { 0, 0, 0, 0, 0, 0 } },82{ { 0, 0, 0, 0, 0, 0 } } } };83static const struct IP_BASE IOAGR0_BASE = { { { { 0x02419000, 0x056C0000, 0, 0, 0, 0 } },84{ { 0, 0, 0, 0, 0, 0 } },85{ { 0, 0, 0, 0, 0, 0 } },86{ { 0, 0, 0, 0, 0, 0 } },87{ { 0, 0, 0, 0, 0, 0 } },88{ { 0, 0, 0, 0, 0, 0 } },89{ { 0, 0, 0, 0, 0, 0 } } } };90static const struct IP_BASE IOAPIC0_BASE = { { { { 0x00A00000, 0x0241F000, 0x050C0000, 0, 0, 0 } },91{ { 0, 0, 0, 0, 0, 0 } },92{ { 0, 0, 0, 0, 0, 0 } },93{ { 0, 0, 0, 0, 0, 0 } },94{ { 0, 0, 0, 0, 0, 0 } },95{ { 0, 0, 0, 0, 0, 0 } },96{ { 0, 0, 0, 0, 0, 0 } } } };97static const struct IP_BASE IOHC0_BASE = { { { { 0x00010000, 0x02406000, 0x04EC0000, 0, 0, 0 } },98{ { 0, 0, 0, 0, 0, 0 } },99{ { 0, 0, 0, 0, 0, 0 } },100{ { 0, 0, 0, 0, 0, 0 } },101{ { 0, 0, 0, 0, 0, 0 } },102{ { 0, 0, 0, 0, 0, 0 } },103{ { 0, 0, 0, 0, 0, 0 } } } };104static const struct IP_BASE L1IMUIOAGR0_BASE = { { { { 0x0240CC00, 0x05200000, 0, 0, 0, 0 } },105{ { 0, 0, 0, 0, 0, 0 } },106{ { 0, 0, 0, 0, 0, 0 } },107{ { 0, 0, 0, 0, 0, 0 } },108{ { 0, 0, 0, 0, 0, 0 } },109{ { 0, 0, 0, 0, 0, 0 } },110{ { 0, 0, 0, 0, 0, 0 } } } };111static const struct IP_BASE L1IMUPCIE0_BASE = { { { { 0x0240C800, 0x051C0000, 0, 0, 0, 0 } },112{ { 0, 0, 0, 0, 0, 0 } },113{ { 0, 0, 0, 0, 0, 0 } },114{ { 0, 0, 0, 0, 0, 0 } },115{ { 0, 0, 0, 0, 0, 0 } },116{ { 0, 0, 0, 0, 0, 0 } },117{ { 0, 0, 0, 0, 0, 0 } } } };118static const struct IP_BASE L2IMU0_BASE = { { { { 0x00007DC0, 0x00900000, 0x02407000, 0x04FC0000, 0x055C0000, 0 } },119{ { 0, 0, 0, 0, 0, 0 } },120{ { 0, 0, 0, 0, 0, 0 } },121{ { 0, 0, 0, 0, 0, 0 } },122{ { 0, 0, 0, 0, 0, 0 } },123{ { 0, 0, 0, 0, 0, 0 } },124{ { 0, 0, 0, 0, 0, 0 } } } };125static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } },126{ { 0, 0, 0, 0, 0, 0 } },127{ { 0, 0, 0, 0, 0, 0 } },128{ { 0, 0, 0, 0, 0, 0 } },129{ { 0, 0, 0, 0, 0, 0 } },130{ { 0, 0, 0, 0, 0, 0 } },131{ { 0, 0, 0, 0, 0, 0 } } } };132static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },133{ { 0, 0, 0, 0, 0, 0 } },134{ { 0, 0, 0, 0, 0, 0 } },135{ { 0, 0, 0, 0, 0, 0 } },136{ { 0, 0, 0, 0, 0, 0 } },137{ { 0, 0, 0, 0, 0, 0 } },138{ { 0, 0, 0, 0, 0, 0 } } } };139static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },140{ { 0, 0, 0, 0, 0, 0 } },141{ { 0, 0, 0, 0, 0, 0 } },142{ { 0, 0, 0, 0, 0, 0 } },143{ { 0, 0, 0, 0, 0, 0 } },144{ { 0, 0, 0, 0, 0, 0 } },145{ { 0, 0, 0, 0, 0, 0 } } } };146static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },147{ { 0, 0, 0, 0, 0, 0 } },148{ { 0, 0, 0, 0, 0, 0 } },149{ { 0, 0, 0, 0, 0, 0 } },150{ { 0, 0, 0, 0, 0, 0 } },151{ { 0, 0, 0, 0, 0, 0 } },152{ { 0, 0, 0, 0, 0, 0 } } } };153static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } },154{ { 0, 0, 0, 0, 0, 0 } },155{ { 0, 0, 0, 0, 0, 0 } },156{ { 0, 0, 0, 0, 0, 0 } },157{ { 0, 0, 0, 0, 0, 0 } },158{ { 0, 0, 0, 0, 0, 0 } },159{ { 0, 0, 0, 0, 0, 0 } } } };160static const struct IP_BASE PCIE0_BASE = { { { { 0x02411800, 0x04440000, 0, 0, 0, 0 } },161{ { 0, 0, 0, 0, 0, 0 } },162{ { 0, 0, 0, 0, 0, 0 } },163{ { 0, 0, 0, 0, 0, 0 } },164{ { 0, 0, 0, 0, 0, 0 } },165{ { 0, 0, 0, 0, 0, 0 } },166{ { 0, 0, 0, 0, 0, 0 } } } };167static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x00012540, 0x0040A800, 0, 0, 0 } },168{ { 0, 0, 0, 0, 0, 0 } },169{ { 0, 0, 0, 0, 0, 0 } },170{ { 0, 0, 0, 0, 0, 0 } },171{ { 0, 0, 0, 0, 0, 0 } },172{ { 0, 0, 0, 0, 0, 0 } },173{ { 0, 0, 0, 0, 0, 0 } } } };174static const struct IP_BASE SDMA1_BASE = { { { { 0x00001860, 0x00012560, 0x0040AC00, 0, 0, 0 } },175{ { 0, 0, 0, 0, 0, 0 } },176{ { 0, 0, 0, 0, 0, 0 } },177{ { 0, 0, 0, 0, 0, 0 } },178{ { 0, 0, 0, 0, 0, 0 } },179{ { 0, 0, 0, 0, 0, 0 } },180{ { 0, 0, 0, 0, 0, 0 } } } };181static const struct IP_BASE SDMA2_BASE = { { { { 0x00013760, 0x0001E000, 0x0042EC00, 0, 0, 0 } },182{ { 0, 0, 0, 0, 0, 0 } },183{ { 0, 0, 0, 0, 0, 0 } },184{ { 0, 0, 0, 0, 0, 0 } },185{ { 0, 0, 0, 0, 0, 0 } },186{ { 0, 0, 0, 0, 0, 0 } },187{ { 0, 0, 0, 0, 0, 0 } } } };188static const struct IP_BASE SDMA3_BASE = { { { { 0x00013780, 0x0001E400, 0x0042F000, 0, 0, 0 } },189{ { 0, 0, 0, 0, 0, 0 } },190{ { 0, 0, 0, 0, 0, 0 } },191{ { 0, 0, 0, 0, 0, 0 } },192{ { 0, 0, 0, 0, 0, 0 } },193{ { 0, 0, 0, 0, 0, 0 } },194{ { 0, 0, 0, 0, 0, 0 } } } };195static const struct IP_BASE SDMA4_BASE = { { { { 0x000137A0, 0x0001E800, 0x0042F400, 0, 0, 0 } },196{ { 0, 0, 0, 0, 0, 0 } },197{ { 0, 0, 0, 0, 0, 0 } },198{ { 0, 0, 0, 0, 0, 0 } },199{ { 0, 0, 0, 0, 0, 0 } },200{ { 0, 0, 0, 0, 0, 0 } },201{ { 0, 0, 0, 0, 0, 0 } } } };202static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x02401000, 0x03440000, 0, 0 } },203{ { 0, 0, 0, 0, 0, 0 } },204{ { 0, 0, 0, 0, 0, 0 } },205{ { 0, 0, 0, 0, 0, 0 } },206{ { 0, 0, 0, 0, 0, 0 } },207{ { 0, 0, 0, 0, 0, 0 } },208{ { 0, 0, 0, 0, 0, 0 } } } };209static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } },210{ { 0, 0, 0, 0, 0, 0 } },211{ { 0, 0, 0, 0, 0, 0 } },212{ { 0, 0, 0, 0, 0, 0 } },213{ { 0, 0, 0, 0, 0, 0 } },214{ { 0, 0, 0, 0, 0, 0 } },215{ { 0, 0, 0, 0, 0, 0 } } } };216static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x00054000, 0x02425800, 0, 0, 0 } },217{ { 0x00094000, 0x000D4000, 0x02425C00, 0, 0, 0 } },218{ { 0x00114000, 0x00154000, 0x02426000, 0, 0, 0 } },219{ { 0x00194000, 0x001D4000, 0x02426400, 0, 0, 0 } },220{ { 0, 0, 0, 0, 0, 0 } },221{ { 0, 0, 0, 0, 0, 0 } },222{ { 0, 0, 0, 0, 0, 0 } } } };223static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } },224{ { 0x00007A00, 0x00009000, 0x02445000, 0, 0, 0 } },225{ { 0, 0, 0, 0, 0, 0 } },226{ { 0, 0, 0, 0, 0, 0 } },227{ { 0, 0, 0, 0, 0, 0 } },228{ { 0, 0, 0, 0, 0, 0 } },229{ { 0, 0, 0, 0, 0, 0 } } } };230static const struct IP_BASE WAFL0_BASE = { { { { 0x02438000, 0x04880000, 0, 0, 0, 0 } },231{ { 0, 0, 0, 0, 0, 0 } },232{ { 0, 0, 0, 0, 0, 0 } },233{ { 0, 0, 0, 0, 0, 0 } },234{ { 0, 0, 0, 0, 0, 0 } },235{ { 0, 0, 0, 0, 0, 0 } },236{ { 0, 0, 0, 0, 0, 0 } } } };237static const struct IP_BASE WAFL1_BASE = { { { { 0, 0x01300000, 0x02410800, 0, 0, 0 } },238{ { 0, 0, 0, 0, 0, 0 } },239{ { 0, 0, 0, 0, 0, 0 } },240{ { 0, 0, 0, 0, 0, 0 } },241{ { 0, 0, 0, 0, 0, 0 } },242{ { 0, 0, 0, 0, 0, 0 } },243{ { 0, 0, 0, 0, 0, 0 } } } };244static const struct IP_BASE XGMI0_BASE = { { { { 0x02438C00, 0x04680000, 0x04940000, 0, 0, 0 } },245{ { 0, 0, 0, 0, 0, 0 } },246{ { 0, 0, 0, 0, 0, 0 } },247{ { 0, 0, 0, 0, 0, 0 } },248{ { 0, 0, 0, 0, 0, 0 } },249{ { 0, 0, 0, 0, 0, 0 } },250{ { 0, 0, 0, 0, 0, 0 } } } };251static const struct IP_BASE XGMI1_BASE = { { { { 0x02439000, 0x046C0000, 0x04980000, 0, 0, 0 } },252{ { 0, 0, 0, 0, 0, 0 } },253{ { 0, 0, 0, 0, 0, 0 } },254{ { 0, 0, 0, 0, 0, 0 } },255{ { 0, 0, 0, 0, 0, 0 } },256{ { 0, 0, 0, 0, 0, 0 } },257{ { 0, 0, 0, 0, 0, 0 } } } };258static const struct IP_BASE XGMI2_BASE = { { { { 0x04700000, 0x049C0000, 0, 0, 0, 0 } },259{ { 0x04740000, 0x04A00000, 0, 0, 0, 0 } },260{ { 0x04780000, 0x04A40000, 0, 0, 0, 0 } },261{ { 0x047C0000, 0x04A80000, 0, 0, 0, 0 } },262{ { 0x04800000, 0x04AC0000, 0, 0, 0, 0 } },263{ { 0x04840000, 0x04B00000, 0, 0, 0, 0 } },264{ { 0, 0, 0, 0, 0, 0 } } } };265266267#define ATHUB_BASE__INST0_SEG0 0x00000C20268#define ATHUB_BASE__INST0_SEG1 0x02408C00269#define ATHUB_BASE__INST0_SEG2 0270#define ATHUB_BASE__INST0_SEG3 0271#define ATHUB_BASE__INST0_SEG4 0272#define ATHUB_BASE__INST0_SEG5 0273274#define ATHUB_BASE__INST1_SEG0 0275#define ATHUB_BASE__INST1_SEG1 0276#define ATHUB_BASE__INST1_SEG2 0277#define ATHUB_BASE__INST1_SEG3 0278#define ATHUB_BASE__INST1_SEG4 0279#define ATHUB_BASE__INST1_SEG5 0280281#define ATHUB_BASE__INST2_SEG0 0282#define ATHUB_BASE__INST2_SEG1 0283#define ATHUB_BASE__INST2_SEG2 0284#define ATHUB_BASE__INST2_SEG3 0285#define ATHUB_BASE__INST2_SEG4 0286#define ATHUB_BASE__INST2_SEG5 0287288#define ATHUB_BASE__INST3_SEG0 0289#define ATHUB_BASE__INST3_SEG1 0290#define ATHUB_BASE__INST3_SEG2 0291#define ATHUB_BASE__INST3_SEG3 0292#define ATHUB_BASE__INST3_SEG4 0293#define ATHUB_BASE__INST3_SEG5 0294295#define ATHUB_BASE__INST4_SEG0 0296#define ATHUB_BASE__INST4_SEG1 0297#define ATHUB_BASE__INST4_SEG2 0298#define ATHUB_BASE__INST4_SEG3 0299#define ATHUB_BASE__INST4_SEG4 0300#define ATHUB_BASE__INST4_SEG5 0301302#define ATHUB_BASE__INST5_SEG0 0303#define ATHUB_BASE__INST5_SEG1 0304#define ATHUB_BASE__INST5_SEG2 0305#define ATHUB_BASE__INST5_SEG3 0306#define ATHUB_BASE__INST5_SEG4 0307#define ATHUB_BASE__INST5_SEG5 0308309#define ATHUB_BASE__INST6_SEG0 0310#define ATHUB_BASE__INST6_SEG1 0311#define ATHUB_BASE__INST6_SEG2 0312#define ATHUB_BASE__INST6_SEG3 0313#define ATHUB_BASE__INST6_SEG4 0314#define ATHUB_BASE__INST6_SEG5 0315316#define CLK_BASE__INST0_SEG0 0x00016C00317#define CLK_BASE__INST0_SEG1 0x02401800318#define CLK_BASE__INST0_SEG2 0319#define CLK_BASE__INST0_SEG3 0320#define CLK_BASE__INST0_SEG4 0321#define CLK_BASE__INST0_SEG5 0322323#define CLK_BASE__INST1_SEG0 0x00016E00324#define CLK_BASE__INST1_SEG1 0x02401C00325#define CLK_BASE__INST1_SEG2 0326#define CLK_BASE__INST1_SEG3 0327#define CLK_BASE__INST1_SEG4 0328#define CLK_BASE__INST1_SEG5 0329330#define CLK_BASE__INST2_SEG0 0x00017000331#define CLK_BASE__INST2_SEG1 0x02402000332#define CLK_BASE__INST2_SEG2 0333#define CLK_BASE__INST2_SEG3 0334#define CLK_BASE__INST2_SEG4 0335#define CLK_BASE__INST2_SEG5 0336337#define CLK_BASE__INST3_SEG0 0x00017200338#define CLK_BASE__INST3_SEG1 0x02402400339#define CLK_BASE__INST3_SEG2 0340#define CLK_BASE__INST3_SEG3 0341#define CLK_BASE__INST3_SEG4 0342#define CLK_BASE__INST3_SEG5 0343344#define CLK_BASE__INST4_SEG0 0x0001B000345#define CLK_BASE__INST4_SEG1 0x0242D800346#define CLK_BASE__INST4_SEG2 0347#define CLK_BASE__INST4_SEG3 0348#define CLK_BASE__INST4_SEG4 0349#define CLK_BASE__INST4_SEG5 0350351#define CLK_BASE__INST5_SEG0 0x0001B200352#define CLK_BASE__INST5_SEG1 0x0242DC00353#define CLK_BASE__INST5_SEG2 0354#define CLK_BASE__INST5_SEG3 0355#define CLK_BASE__INST5_SEG4 0356#define CLK_BASE__INST5_SEG5 0357358#define CLK_BASE__INST6_SEG0 0x00017E00359#define CLK_BASE__INST6_SEG1 0x0240BC00360#define CLK_BASE__INST6_SEG2 0361#define CLK_BASE__INST6_SEG3 0362#define CLK_BASE__INST6_SEG4 0363#define CLK_BASE__INST6_SEG5 0364365#define DBGU_IO0_BASE__INST0_SEG0 0x000001E0366#define DBGU_IO0_BASE__INST0_SEG1 0x0240B400367#define DBGU_IO0_BASE__INST0_SEG2 0368#define DBGU_IO0_BASE__INST0_SEG3 0369#define DBGU_IO0_BASE__INST0_SEG4 0370#define DBGU_IO0_BASE__INST0_SEG5 0371372#define DBGU_IO0_BASE__INST1_SEG0 0x00000260373#define DBGU_IO0_BASE__INST1_SEG1 0x02413C00374#define DBGU_IO0_BASE__INST1_SEG2 0375#define DBGU_IO0_BASE__INST1_SEG3 0376#define DBGU_IO0_BASE__INST1_SEG4 0377#define DBGU_IO0_BASE__INST1_SEG5 0378379#define DBGU_IO0_BASE__INST2_SEG0 0x00000280380#define DBGU_IO0_BASE__INST2_SEG1 0x02416000381#define DBGU_IO0_BASE__INST2_SEG2 0382#define DBGU_IO0_BASE__INST2_SEG3 0383#define DBGU_IO0_BASE__INST2_SEG4 0384#define DBGU_IO0_BASE__INST2_SEG5 0385386#define DBGU_IO0_BASE__INST3_SEG0 0387#define DBGU_IO0_BASE__INST3_SEG1 0388#define DBGU_IO0_BASE__INST3_SEG2 0389#define DBGU_IO0_BASE__INST3_SEG3 0390#define DBGU_IO0_BASE__INST3_SEG4 0391#define DBGU_IO0_BASE__INST3_SEG5 0392393#define DBGU_IO0_BASE__INST4_SEG0 0394#define DBGU_IO0_BASE__INST4_SEG1 0395#define DBGU_IO0_BASE__INST4_SEG2 0396#define DBGU_IO0_BASE__INST4_SEG3 0397#define DBGU_IO0_BASE__INST4_SEG4 0398#define DBGU_IO0_BASE__INST4_SEG5 0399400#define DBGU_IO0_BASE__INST5_SEG0 0401#define DBGU_IO0_BASE__INST5_SEG1 0402#define DBGU_IO0_BASE__INST5_SEG2 0403#define DBGU_IO0_BASE__INST5_SEG3 0404#define DBGU_IO0_BASE__INST5_SEG4 0405#define DBGU_IO0_BASE__INST5_SEG5 0406407#define DBGU_IO0_BASE__INST6_SEG0 0408#define DBGU_IO0_BASE__INST6_SEG1 0409#define DBGU_IO0_BASE__INST6_SEG2 0410#define DBGU_IO0_BASE__INST6_SEG3 0411#define DBGU_IO0_BASE__INST6_SEG4 0412#define DBGU_IO0_BASE__INST6_SEG5 0413414#define DF_BASE__INST0_SEG0 0x00007000415#define DF_BASE__INST0_SEG1 0x0240B800416#define DF_BASE__INST0_SEG2 0x07C00000417#define DF_BASE__INST0_SEG3 0418#define DF_BASE__INST0_SEG4 0419#define DF_BASE__INST0_SEG5 0420421#define DF_BASE__INST1_SEG0 0422#define DF_BASE__INST1_SEG1 0423#define DF_BASE__INST1_SEG2 0424#define DF_BASE__INST1_SEG3 0425#define DF_BASE__INST1_SEG4 0426#define DF_BASE__INST1_SEG5 0427428#define DF_BASE__INST2_SEG0 0429#define DF_BASE__INST2_SEG1 0430#define DF_BASE__INST2_SEG2 0431#define DF_BASE__INST2_SEG3 0432#define DF_BASE__INST2_SEG4 0433#define DF_BASE__INST2_SEG5 0434435#define DF_BASE__INST3_SEG0 0436#define DF_BASE__INST3_SEG1 0437#define DF_BASE__INST3_SEG2 0438#define DF_BASE__INST3_SEG3 0439#define DF_BASE__INST3_SEG4 0440#define DF_BASE__INST3_SEG5 0441442#define DF_BASE__INST4_SEG0 0443#define DF_BASE__INST4_SEG1 0444#define DF_BASE__INST4_SEG2 0445#define DF_BASE__INST4_SEG3 0446#define DF_BASE__INST4_SEG4 0447#define DF_BASE__INST4_SEG5 0448449#define DF_BASE__INST5_SEG0 0450#define DF_BASE__INST5_SEG1 0451#define DF_BASE__INST5_SEG2 0452#define DF_BASE__INST5_SEG3 0453#define DF_BASE__INST5_SEG4 0454#define DF_BASE__INST5_SEG5 0455456#define DF_BASE__INST6_SEG0 0457#define DF_BASE__INST6_SEG1 0458#define DF_BASE__INST6_SEG2 0459#define DF_BASE__INST6_SEG3 0460#define DF_BASE__INST6_SEG4 0461#define DF_BASE__INST6_SEG5 0462463#define FUSE_BASE__INST0_SEG0 0x00017400464#define FUSE_BASE__INST0_SEG1 0x02401400465#define FUSE_BASE__INST0_SEG2 0466#define FUSE_BASE__INST0_SEG3 0467#define FUSE_BASE__INST0_SEG4 0468#define FUSE_BASE__INST0_SEG5 0469470#define FUSE_BASE__INST1_SEG0 0471#define FUSE_BASE__INST1_SEG1 0472#define FUSE_BASE__INST1_SEG2 0473#define FUSE_BASE__INST1_SEG3 0474#define FUSE_BASE__INST1_SEG4 0475#define FUSE_BASE__INST1_SEG5 0476477#define FUSE_BASE__INST2_SEG0 0478#define FUSE_BASE__INST2_SEG1 0479#define FUSE_BASE__INST2_SEG2 0480#define FUSE_BASE__INST2_SEG3 0481#define FUSE_BASE__INST2_SEG4 0482#define FUSE_BASE__INST2_SEG5 0483484#define FUSE_BASE__INST3_SEG0 0485#define FUSE_BASE__INST3_SEG1 0486#define FUSE_BASE__INST3_SEG2 0487#define FUSE_BASE__INST3_SEG3 0488#define FUSE_BASE__INST3_SEG4 0489#define FUSE_BASE__INST3_SEG5 0490491#define FUSE_BASE__INST4_SEG0 0492#define FUSE_BASE__INST4_SEG1 0493#define FUSE_BASE__INST4_SEG2 0494#define FUSE_BASE__INST4_SEG3 0495#define FUSE_BASE__INST4_SEG4 0496#define FUSE_BASE__INST4_SEG5 0497498#define FUSE_BASE__INST5_SEG0 0499#define FUSE_BASE__INST5_SEG1 0500#define FUSE_BASE__INST5_SEG2 0501#define FUSE_BASE__INST5_SEG3 0502#define FUSE_BASE__INST5_SEG4 0503#define FUSE_BASE__INST5_SEG5 0504505#define FUSE_BASE__INST6_SEG0 0506#define FUSE_BASE__INST6_SEG1 0507#define FUSE_BASE__INST6_SEG2 0508#define FUSE_BASE__INST6_SEG3 0509#define FUSE_BASE__INST6_SEG4 0510#define FUSE_BASE__INST6_SEG5 0511512#define GC_BASE__INST0_SEG0 0x00002000513#define GC_BASE__INST0_SEG1 0x0000A000514#define GC_BASE__INST0_SEG2 0x02402C00515#define GC_BASE__INST0_SEG3 0516#define GC_BASE__INST0_SEG4 0517#define GC_BASE__INST0_SEG5 0518519#define GC_BASE__INST1_SEG0 0520#define GC_BASE__INST1_SEG1 0521#define GC_BASE__INST1_SEG2 0522#define GC_BASE__INST1_SEG3 0523#define GC_BASE__INST1_SEG4 0524#define GC_BASE__INST1_SEG5 0525526#define GC_BASE__INST2_SEG0 0527#define GC_BASE__INST2_SEG1 0528#define GC_BASE__INST2_SEG2 0529#define GC_BASE__INST2_SEG3 0530#define GC_BASE__INST2_SEG4 0531#define GC_BASE__INST2_SEG5 0532533#define GC_BASE__INST3_SEG0 0534#define GC_BASE__INST3_SEG1 0535#define GC_BASE__INST3_SEG2 0536#define GC_BASE__INST3_SEG3 0537#define GC_BASE__INST3_SEG4 0538#define GC_BASE__INST3_SEG5 0539540#define GC_BASE__INST4_SEG0 0541#define GC_BASE__INST4_SEG1 0542#define GC_BASE__INST4_SEG2 0543#define GC_BASE__INST4_SEG3 0544#define GC_BASE__INST4_SEG4 0545#define GC_BASE__INST4_SEG5 0546547#define GC_BASE__INST5_SEG0 0548#define GC_BASE__INST5_SEG1 0549#define GC_BASE__INST5_SEG2 0550#define GC_BASE__INST5_SEG3 0551#define GC_BASE__INST5_SEG4 0552#define GC_BASE__INST5_SEG5 0553554#define GC_BASE__INST6_SEG0 0555#define GC_BASE__INST6_SEG1 0556#define GC_BASE__INST6_SEG2 0557#define GC_BASE__INST6_SEG3 0558#define GC_BASE__INST6_SEG4 0559#define GC_BASE__INST6_SEG5 0560561#define HDP_BASE__INST0_SEG0 0x00000F20562#define HDP_BASE__INST0_SEG1 0x0240A400563#define HDP_BASE__INST0_SEG2 0564#define HDP_BASE__INST0_SEG3 0565#define HDP_BASE__INST0_SEG4 0566#define HDP_BASE__INST0_SEG5 0567568#define HDP_BASE__INST1_SEG0 0569#define HDP_BASE__INST1_SEG1 0570#define HDP_BASE__INST1_SEG2 0571#define HDP_BASE__INST1_SEG3 0572#define HDP_BASE__INST1_SEG4 0573#define HDP_BASE__INST1_SEG5 0574575#define HDP_BASE__INST2_SEG0 0576#define HDP_BASE__INST2_SEG1 0577#define HDP_BASE__INST2_SEG2 0578#define HDP_BASE__INST2_SEG3 0579#define HDP_BASE__INST2_SEG4 0580#define HDP_BASE__INST2_SEG5 0581582#define HDP_BASE__INST3_SEG0 0583#define HDP_BASE__INST3_SEG1 0584#define HDP_BASE__INST3_SEG2 0585#define HDP_BASE__INST3_SEG3 0586#define HDP_BASE__INST3_SEG4 0587#define HDP_BASE__INST3_SEG5 0588589#define HDP_BASE__INST4_SEG0 0590#define HDP_BASE__INST4_SEG1 0591#define HDP_BASE__INST4_SEG2 0592#define HDP_BASE__INST4_SEG3 0593#define HDP_BASE__INST4_SEG4 0594#define HDP_BASE__INST4_SEG5 0595596#define HDP_BASE__INST5_SEG0 0597#define HDP_BASE__INST5_SEG1 0598#define HDP_BASE__INST5_SEG2 0599#define HDP_BASE__INST5_SEG3 0600#define HDP_BASE__INST5_SEG4 0601#define HDP_BASE__INST5_SEG5 0602603#define HDP_BASE__INST6_SEG0 0604#define HDP_BASE__INST6_SEG1 0605#define HDP_BASE__INST6_SEG2 0606#define HDP_BASE__INST6_SEG3 0607#define HDP_BASE__INST6_SEG4 0608#define HDP_BASE__INST6_SEG5 0609610#define IOAGR0_BASE__INST0_SEG0 0x02419000611#define IOAGR0_BASE__INST0_SEG1 0x056C0000612#define IOAGR0_BASE__INST0_SEG2 0613#define IOAGR0_BASE__INST0_SEG3 0614#define IOAGR0_BASE__INST0_SEG4 0615#define IOAGR0_BASE__INST0_SEG5 0616617#define IOAGR0_BASE__INST1_SEG0 0618#define IOAGR0_BASE__INST1_SEG1 0619#define IOAGR0_BASE__INST1_SEG2 0620#define IOAGR0_BASE__INST1_SEG3 0621#define IOAGR0_BASE__INST1_SEG4 0622#define IOAGR0_BASE__INST1_SEG5 0623624#define IOAGR0_BASE__INST2_SEG0 0625#define IOAGR0_BASE__INST2_SEG1 0626#define IOAGR0_BASE__INST2_SEG2 0627#define IOAGR0_BASE__INST2_SEG3 0628#define IOAGR0_BASE__INST2_SEG4 0629#define IOAGR0_BASE__INST2_SEG5 0630631#define IOAGR0_BASE__INST3_SEG0 0632#define IOAGR0_BASE__INST3_SEG1 0633#define IOAGR0_BASE__INST3_SEG2 0634#define IOAGR0_BASE__INST3_SEG3 0635#define IOAGR0_BASE__INST3_SEG4 0636#define IOAGR0_BASE__INST3_SEG5 0637638#define IOAGR0_BASE__INST4_SEG0 0639#define IOAGR0_BASE__INST4_SEG1 0640#define IOAGR0_BASE__INST4_SEG2 0641#define IOAGR0_BASE__INST4_SEG3 0642#define IOAGR0_BASE__INST4_SEG4 0643#define IOAGR0_BASE__INST4_SEG5 0644645#define IOAGR0_BASE__INST5_SEG0 0646#define IOAGR0_BASE__INST5_SEG1 0647#define IOAGR0_BASE__INST5_SEG2 0648#define IOAGR0_BASE__INST5_SEG3 0649#define IOAGR0_BASE__INST5_SEG4 0650#define IOAGR0_BASE__INST5_SEG5 0651652#define IOAGR0_BASE__INST6_SEG0 0653#define IOAGR0_BASE__INST6_SEG1 0654#define IOAGR0_BASE__INST6_SEG2 0655#define IOAGR0_BASE__INST6_SEG3 0656#define IOAGR0_BASE__INST6_SEG4 0657#define IOAGR0_BASE__INST6_SEG5 0658659#define IOAPIC0_BASE__INST0_SEG0 0x00A00000660#define IOAPIC0_BASE__INST0_SEG1 0x0241F000661#define IOAPIC0_BASE__INST0_SEG2 0x050C0000662#define IOAPIC0_BASE__INST0_SEG3 0663#define IOAPIC0_BASE__INST0_SEG4 0664#define IOAPIC0_BASE__INST0_SEG5 0665666#define IOAPIC0_BASE__INST1_SEG0 0667#define IOAPIC0_BASE__INST1_SEG1 0668#define IOAPIC0_BASE__INST1_SEG2 0669#define IOAPIC0_BASE__INST1_SEG3 0670#define IOAPIC0_BASE__INST1_SEG4 0671#define IOAPIC0_BASE__INST1_SEG5 0672673#define IOAPIC0_BASE__INST2_SEG0 0674#define IOAPIC0_BASE__INST2_SEG1 0675#define IOAPIC0_BASE__INST2_SEG2 0676#define IOAPIC0_BASE__INST2_SEG3 0677#define IOAPIC0_BASE__INST2_SEG4 0678#define IOAPIC0_BASE__INST2_SEG5 0679680#define IOAPIC0_BASE__INST3_SEG0 0681#define IOAPIC0_BASE__INST3_SEG1 0682#define IOAPIC0_BASE__INST3_SEG2 0683#define IOAPIC0_BASE__INST3_SEG3 0684#define IOAPIC0_BASE__INST3_SEG4 0685#define IOAPIC0_BASE__INST3_SEG5 0686687#define IOAPIC0_BASE__INST4_SEG0 0688#define IOAPIC0_BASE__INST4_SEG1 0689#define IOAPIC0_BASE__INST4_SEG2 0690#define IOAPIC0_BASE__INST4_SEG3 0691#define IOAPIC0_BASE__INST4_SEG4 0692#define IOAPIC0_BASE__INST4_SEG5 0693694#define IOAPIC0_BASE__INST5_SEG0 0695#define IOAPIC0_BASE__INST5_SEG1 0696#define IOAPIC0_BASE__INST5_SEG2 0697#define IOAPIC0_BASE__INST5_SEG3 0698#define IOAPIC0_BASE__INST5_SEG4 0699#define IOAPIC0_BASE__INST5_SEG5 0700701#define IOAPIC0_BASE__INST6_SEG0 0702#define IOAPIC0_BASE__INST6_SEG1 0703#define IOAPIC0_BASE__INST6_SEG2 0704#define IOAPIC0_BASE__INST6_SEG3 0705#define IOAPIC0_BASE__INST6_SEG4 0706#define IOAPIC0_BASE__INST6_SEG5 0707708#define IOHC0_BASE__INST0_SEG0 0x00010000709#define IOHC0_BASE__INST0_SEG1 0x02406000710#define IOHC0_BASE__INST0_SEG2 0x04EC0000711#define IOHC0_BASE__INST0_SEG3 0712#define IOHC0_BASE__INST0_SEG4 0713#define IOHC0_BASE__INST0_SEG5 0714715#define IOHC0_BASE__INST1_SEG0 0716#define IOHC0_BASE__INST1_SEG1 0717#define IOHC0_BASE__INST1_SEG2 0718#define IOHC0_BASE__INST1_SEG3 0719#define IOHC0_BASE__INST1_SEG4 0720#define IOHC0_BASE__INST1_SEG5 0721722#define IOHC0_BASE__INST2_SEG0 0723#define IOHC0_BASE__INST2_SEG1 0724#define IOHC0_BASE__INST2_SEG2 0725#define IOHC0_BASE__INST2_SEG3 0726#define IOHC0_BASE__INST2_SEG4 0727#define IOHC0_BASE__INST2_SEG5 0728729#define IOHC0_BASE__INST3_SEG0 0730#define IOHC0_BASE__INST3_SEG1 0731#define IOHC0_BASE__INST3_SEG2 0732#define IOHC0_BASE__INST3_SEG3 0733#define IOHC0_BASE__INST3_SEG4 0734#define IOHC0_BASE__INST3_SEG5 0735736#define IOHC0_BASE__INST4_SEG0 0737#define IOHC0_BASE__INST4_SEG1 0738#define IOHC0_BASE__INST4_SEG2 0739#define IOHC0_BASE__INST4_SEG3 0740#define IOHC0_BASE__INST4_SEG4 0741#define IOHC0_BASE__INST4_SEG5 0742743#define IOHC0_BASE__INST5_SEG0 0744#define IOHC0_BASE__INST5_SEG1 0745#define IOHC0_BASE__INST5_SEG2 0746#define IOHC0_BASE__INST5_SEG3 0747#define IOHC0_BASE__INST5_SEG4 0748#define IOHC0_BASE__INST5_SEG5 0749750#define IOHC0_BASE__INST6_SEG0 0751#define IOHC0_BASE__INST6_SEG1 0752#define IOHC0_BASE__INST6_SEG2 0753#define IOHC0_BASE__INST6_SEG3 0754#define IOHC0_BASE__INST6_SEG4 0755#define IOHC0_BASE__INST6_SEG5 0756757#define L1IMUIOAGR0_BASE__INST0_SEG0 0x0240CC00758#define L1IMUIOAGR0_BASE__INST0_SEG1 0x05200000759#define L1IMUIOAGR0_BASE__INST0_SEG2 0760#define L1IMUIOAGR0_BASE__INST0_SEG3 0761#define L1IMUIOAGR0_BASE__INST0_SEG4 0762#define L1IMUIOAGR0_BASE__INST0_SEG5 0763764#define L1IMUIOAGR0_BASE__INST1_SEG0 0765#define L1IMUIOAGR0_BASE__INST1_SEG1 0766#define L1IMUIOAGR0_BASE__INST1_SEG2 0767#define L1IMUIOAGR0_BASE__INST1_SEG3 0768#define L1IMUIOAGR0_BASE__INST1_SEG4 0769#define L1IMUIOAGR0_BASE__INST1_SEG5 0770771#define L1IMUIOAGR0_BASE__INST2_SEG0 0772#define L1IMUIOAGR0_BASE__INST2_SEG1 0773#define L1IMUIOAGR0_BASE__INST2_SEG2 0774#define L1IMUIOAGR0_BASE__INST2_SEG3 0775#define L1IMUIOAGR0_BASE__INST2_SEG4 0776#define L1IMUIOAGR0_BASE__INST2_SEG5 0777778#define L1IMUIOAGR0_BASE__INST3_SEG0 0779#define L1IMUIOAGR0_BASE__INST3_SEG1 0780#define L1IMUIOAGR0_BASE__INST3_SEG2 0781#define L1IMUIOAGR0_BASE__INST3_SEG3 0782#define L1IMUIOAGR0_BASE__INST3_SEG4 0783#define L1IMUIOAGR0_BASE__INST3_SEG5 0784785#define L1IMUIOAGR0_BASE__INST4_SEG0 0786#define L1IMUIOAGR0_BASE__INST4_SEG1 0787#define L1IMUIOAGR0_BASE__INST4_SEG2 0788#define L1IMUIOAGR0_BASE__INST4_SEG3 0789#define L1IMUIOAGR0_BASE__INST4_SEG4 0790#define L1IMUIOAGR0_BASE__INST4_SEG5 0791792#define L1IMUIOAGR0_BASE__INST5_SEG0 0793#define L1IMUIOAGR0_BASE__INST5_SEG1 0794#define L1IMUIOAGR0_BASE__INST5_SEG2 0795#define L1IMUIOAGR0_BASE__INST5_SEG3 0796#define L1IMUIOAGR0_BASE__INST5_SEG4 0797#define L1IMUIOAGR0_BASE__INST5_SEG5 0798799#define L1IMUIOAGR0_BASE__INST6_SEG0 0800#define L1IMUIOAGR0_BASE__INST6_SEG1 0801#define L1IMUIOAGR0_BASE__INST6_SEG2 0802#define L1IMUIOAGR0_BASE__INST6_SEG3 0803#define L1IMUIOAGR0_BASE__INST6_SEG4 0804#define L1IMUIOAGR0_BASE__INST6_SEG5 0805806#define L1IMUPCIE0_BASE__INST0_SEG0 0x0240C800807#define L1IMUPCIE0_BASE__INST0_SEG1 0x051C0000808#define L1IMUPCIE0_BASE__INST0_SEG2 0809#define L1IMUPCIE0_BASE__INST0_SEG3 0810#define L1IMUPCIE0_BASE__INST0_SEG4 0811#define L1IMUPCIE0_BASE__INST0_SEG5 0812813#define L1IMUPCIE0_BASE__INST1_SEG0 0814#define L1IMUPCIE0_BASE__INST1_SEG1 0815#define L1IMUPCIE0_BASE__INST1_SEG2 0816#define L1IMUPCIE0_BASE__INST1_SEG3 0817#define L1IMUPCIE0_BASE__INST1_SEG4 0818#define L1IMUPCIE0_BASE__INST1_SEG5 0819820#define L1IMUPCIE0_BASE__INST2_SEG0 0821#define L1IMUPCIE0_BASE__INST2_SEG1 0822#define L1IMUPCIE0_BASE__INST2_SEG2 0823#define L1IMUPCIE0_BASE__INST2_SEG3 0824#define L1IMUPCIE0_BASE__INST2_SEG4 0825#define L1IMUPCIE0_BASE__INST2_SEG5 0826827#define L1IMUPCIE0_BASE__INST3_SEG0 0828#define L1IMUPCIE0_BASE__INST3_SEG1 0829#define L1IMUPCIE0_BASE__INST3_SEG2 0830#define L1IMUPCIE0_BASE__INST3_SEG3 0831#define L1IMUPCIE0_BASE__INST3_SEG4 0832#define L1IMUPCIE0_BASE__INST3_SEG5 0833834#define L1IMUPCIE0_BASE__INST4_SEG0 0835#define L1IMUPCIE0_BASE__INST4_SEG1 0836#define L1IMUPCIE0_BASE__INST4_SEG2 0837#define L1IMUPCIE0_BASE__INST4_SEG3 0838#define L1IMUPCIE0_BASE__INST4_SEG4 0839#define L1IMUPCIE0_BASE__INST4_SEG5 0840841#define L1IMUPCIE0_BASE__INST5_SEG0 0842#define L1IMUPCIE0_BASE__INST5_SEG1 0843#define L1IMUPCIE0_BASE__INST5_SEG2 0844#define L1IMUPCIE0_BASE__INST5_SEG3 0845#define L1IMUPCIE0_BASE__INST5_SEG4 0846#define L1IMUPCIE0_BASE__INST5_SEG5 0847848#define L1IMUPCIE0_BASE__INST6_SEG0 0849#define L1IMUPCIE0_BASE__INST6_SEG1 0850#define L1IMUPCIE0_BASE__INST6_SEG2 0851#define L1IMUPCIE0_BASE__INST6_SEG3 0852#define L1IMUPCIE0_BASE__INST6_SEG4 0853#define L1IMUPCIE0_BASE__INST6_SEG5 0854855#define L2IMU0_BASE__INST0_SEG0 0x00007DC0856#define L2IMU0_BASE__INST0_SEG1 0x00900000857#define L2IMU0_BASE__INST0_SEG2 0x02407000858#define L2IMU0_BASE__INST0_SEG3 0x04FC0000859#define L2IMU0_BASE__INST0_SEG4 0x055C0000860#define L2IMU0_BASE__INST0_SEG5 0861862#define L2IMU0_BASE__INST1_SEG0 0863#define L2IMU0_BASE__INST1_SEG1 0864#define L2IMU0_BASE__INST1_SEG2 0865#define L2IMU0_BASE__INST1_SEG3 0866#define L2IMU0_BASE__INST1_SEG4 0867#define L2IMU0_BASE__INST1_SEG5 0868869#define L2IMU0_BASE__INST2_SEG0 0870#define L2IMU0_BASE__INST2_SEG1 0871#define L2IMU0_BASE__INST2_SEG2 0872#define L2IMU0_BASE__INST2_SEG3 0873#define L2IMU0_BASE__INST2_SEG4 0874#define L2IMU0_BASE__INST2_SEG5 0875876#define L2IMU0_BASE__INST3_SEG0 0877#define L2IMU0_BASE__INST3_SEG1 0878#define L2IMU0_BASE__INST3_SEG2 0879#define L2IMU0_BASE__INST3_SEG3 0880#define L2IMU0_BASE__INST3_SEG4 0881#define L2IMU0_BASE__INST3_SEG5 0882883#define L2IMU0_BASE__INST4_SEG0 0884#define L2IMU0_BASE__INST4_SEG1 0885#define L2IMU0_BASE__INST4_SEG2 0886#define L2IMU0_BASE__INST4_SEG3 0887#define L2IMU0_BASE__INST4_SEG4 0888#define L2IMU0_BASE__INST4_SEG5 0889890#define L2IMU0_BASE__INST5_SEG0 0891#define L2IMU0_BASE__INST5_SEG1 0892#define L2IMU0_BASE__INST5_SEG2 0893#define L2IMU0_BASE__INST5_SEG3 0894#define L2IMU0_BASE__INST5_SEG4 0895#define L2IMU0_BASE__INST5_SEG5 0896897#define L2IMU0_BASE__INST6_SEG0 0898#define L2IMU0_BASE__INST6_SEG1 0899#define L2IMU0_BASE__INST6_SEG2 0900#define L2IMU0_BASE__INST6_SEG3 0901#define L2IMU0_BASE__INST6_SEG4 0902#define L2IMU0_BASE__INST6_SEG5 0903904#define MMHUB_BASE__INST0_SEG0 0x0001A000905#define MMHUB_BASE__INST0_SEG1 0x02408800906#define MMHUB_BASE__INST0_SEG2 0907#define MMHUB_BASE__INST0_SEG3 0908#define MMHUB_BASE__INST0_SEG4 0909#define MMHUB_BASE__INST0_SEG5 0910911#define MMHUB_BASE__INST1_SEG0 0912#define MMHUB_BASE__INST1_SEG1 0913#define MMHUB_BASE__INST1_SEG2 0914#define MMHUB_BASE__INST1_SEG3 0915#define MMHUB_BASE__INST1_SEG4 0916#define MMHUB_BASE__INST1_SEG5 0917918#define MMHUB_BASE__INST2_SEG0 0919#define MMHUB_BASE__INST2_SEG1 0920#define MMHUB_BASE__INST2_SEG2 0921#define MMHUB_BASE__INST2_SEG3 0922#define MMHUB_BASE__INST2_SEG4 0923#define MMHUB_BASE__INST2_SEG5 0924925#define MMHUB_BASE__INST3_SEG0 0926#define MMHUB_BASE__INST3_SEG1 0927#define MMHUB_BASE__INST3_SEG2 0928#define MMHUB_BASE__INST3_SEG3 0929#define MMHUB_BASE__INST3_SEG4 0930#define MMHUB_BASE__INST3_SEG5 0931932#define MMHUB_BASE__INST4_SEG0 0933#define MMHUB_BASE__INST4_SEG1 0934#define MMHUB_BASE__INST4_SEG2 0935#define MMHUB_BASE__INST4_SEG3 0936#define MMHUB_BASE__INST4_SEG4 0937#define MMHUB_BASE__INST4_SEG5 0938939#define MMHUB_BASE__INST5_SEG0 0940#define MMHUB_BASE__INST5_SEG1 0941#define MMHUB_BASE__INST5_SEG2 0942#define MMHUB_BASE__INST5_SEG3 0943#define MMHUB_BASE__INST5_SEG4 0944#define MMHUB_BASE__INST5_SEG5 0945946#define MMHUB_BASE__INST6_SEG0 0947#define MMHUB_BASE__INST6_SEG1 0948#define MMHUB_BASE__INST6_SEG2 0949#define MMHUB_BASE__INST6_SEG3 0950#define MMHUB_BASE__INST6_SEG4 0951#define MMHUB_BASE__INST6_SEG5 0952953#define MP0_BASE__INST0_SEG0 0x00016000954#define MP0_BASE__INST0_SEG1 0x00DC0000955#define MP0_BASE__INST0_SEG2 0x00E00000956#define MP0_BASE__INST0_SEG3 0x00E40000957#define MP0_BASE__INST0_SEG4 0x0243FC00958#define MP0_BASE__INST0_SEG5 0959960#define MP0_BASE__INST1_SEG0 0961#define MP0_BASE__INST1_SEG1 0962#define MP0_BASE__INST1_SEG2 0963#define MP0_BASE__INST1_SEG3 0964#define MP0_BASE__INST1_SEG4 0965#define MP0_BASE__INST1_SEG5 0966967#define MP0_BASE__INST2_SEG0 0968#define MP0_BASE__INST2_SEG1 0969#define MP0_BASE__INST2_SEG2 0970#define MP0_BASE__INST2_SEG3 0971#define MP0_BASE__INST2_SEG4 0972#define MP0_BASE__INST2_SEG5 0973974#define MP0_BASE__INST3_SEG0 0975#define MP0_BASE__INST3_SEG1 0976#define MP0_BASE__INST3_SEG2 0977#define MP0_BASE__INST3_SEG3 0978#define MP0_BASE__INST3_SEG4 0979#define MP0_BASE__INST3_SEG5 0980981#define MP0_BASE__INST4_SEG0 0982#define MP0_BASE__INST4_SEG1 0983#define MP0_BASE__INST4_SEG2 0984#define MP0_BASE__INST4_SEG3 0985#define MP0_BASE__INST4_SEG4 0986#define MP0_BASE__INST4_SEG5 0987988#define MP0_BASE__INST5_SEG0 0989#define MP0_BASE__INST5_SEG1 0990#define MP0_BASE__INST5_SEG2 0991#define MP0_BASE__INST5_SEG3 0992#define MP0_BASE__INST5_SEG4 0993#define MP0_BASE__INST5_SEG5 0994995#define MP0_BASE__INST6_SEG0 0996#define MP0_BASE__INST6_SEG1 0997#define MP0_BASE__INST6_SEG2 0998#define MP0_BASE__INST6_SEG3 0999#define MP0_BASE__INST6_SEG4 01000#define MP0_BASE__INST6_SEG5 010011002#define MP1_BASE__INST0_SEG0 0x000160001003#define MP1_BASE__INST0_SEG1 0x00DC00001004#define MP1_BASE__INST0_SEG2 0x00E000001005#define MP1_BASE__INST0_SEG3 0x00E400001006#define MP1_BASE__INST0_SEG4 0x0243FC001007#define MP1_BASE__INST0_SEG5 010081009#define MP1_BASE__INST1_SEG0 01010#define MP1_BASE__INST1_SEG1 01011#define MP1_BASE__INST1_SEG2 01012#define MP1_BASE__INST1_SEG3 01013#define MP1_BASE__INST1_SEG4 01014#define MP1_BASE__INST1_SEG5 010151016#define MP1_BASE__INST2_SEG0 01017#define MP1_BASE__INST2_SEG1 01018#define MP1_BASE__INST2_SEG2 01019#define MP1_BASE__INST2_SEG3 01020#define MP1_BASE__INST2_SEG4 01021#define MP1_BASE__INST2_SEG5 010221023#define MP1_BASE__INST3_SEG0 01024#define MP1_BASE__INST3_SEG1 01025#define MP1_BASE__INST3_SEG2 01026#define MP1_BASE__INST3_SEG3 01027#define MP1_BASE__INST3_SEG4 01028#define MP1_BASE__INST3_SEG5 010291030#define MP1_BASE__INST4_SEG0 01031#define MP1_BASE__INST4_SEG1 01032#define MP1_BASE__INST4_SEG2 01033#define MP1_BASE__INST4_SEG3 01034#define MP1_BASE__INST4_SEG4 01035#define MP1_BASE__INST4_SEG5 010361037#define MP1_BASE__INST5_SEG0 01038#define MP1_BASE__INST5_SEG1 01039#define MP1_BASE__INST5_SEG2 01040#define MP1_BASE__INST5_SEG3 01041#define MP1_BASE__INST5_SEG4 01042#define MP1_BASE__INST5_SEG5 010431044#define MP1_BASE__INST6_SEG0 01045#define MP1_BASE__INST6_SEG1 01046#define MP1_BASE__INST6_SEG2 01047#define MP1_BASE__INST6_SEG3 01048#define MP1_BASE__INST6_SEG4 01049#define MP1_BASE__INST6_SEG5 010501051#define NBIO_BASE__INST0_SEG0 0x000000001052#define NBIO_BASE__INST0_SEG1 0x000000141053#define NBIO_BASE__INST0_SEG2 0x00000D201054#define NBIO_BASE__INST0_SEG3 0x000104001055#define NBIO_BASE__INST0_SEG4 0x0241B0001056#define NBIO_BASE__INST0_SEG5 0x0404000010571058#define NBIO_BASE__INST1_SEG0 01059#define NBIO_BASE__INST1_SEG1 01060#define NBIO_BASE__INST1_SEG2 01061#define NBIO_BASE__INST1_SEG3 01062#define NBIO_BASE__INST1_SEG4 01063#define NBIO_BASE__INST1_SEG5 010641065#define NBIO_BASE__INST2_SEG0 01066#define NBIO_BASE__INST2_SEG1 01067#define NBIO_BASE__INST2_SEG2 01068#define NBIO_BASE__INST2_SEG3 01069#define NBIO_BASE__INST2_SEG4 01070#define NBIO_BASE__INST2_SEG5 010711072#define NBIO_BASE__INST3_SEG0 01073#define NBIO_BASE__INST3_SEG1 01074#define NBIO_BASE__INST3_SEG2 01075#define NBIO_BASE__INST3_SEG3 01076#define NBIO_BASE__INST3_SEG4 01077#define NBIO_BASE__INST3_SEG5 010781079#define NBIO_BASE__INST4_SEG0 01080#define NBIO_BASE__INST4_SEG1 01081#define NBIO_BASE__INST4_SEG2 01082#define NBIO_BASE__INST4_SEG3 01083#define NBIO_BASE__INST4_SEG4 01084#define NBIO_BASE__INST4_SEG5 010851086#define NBIO_BASE__INST5_SEG0 01087#define NBIO_BASE__INST5_SEG1 01088#define NBIO_BASE__INST5_SEG2 01089#define NBIO_BASE__INST5_SEG3 01090#define NBIO_BASE__INST5_SEG4 01091#define NBIO_BASE__INST5_SEG5 010921093#define NBIO_BASE__INST6_SEG0 01094#define NBIO_BASE__INST6_SEG1 01095#define NBIO_BASE__INST6_SEG2 01096#define NBIO_BASE__INST6_SEG3 01097#define NBIO_BASE__INST6_SEG4 01098#define NBIO_BASE__INST6_SEG5 010991100#define OSSSYS_BASE__INST0_SEG0 0x000010A01101#define OSSSYS_BASE__INST0_SEG1 0x0240A0001102#define OSSSYS_BASE__INST0_SEG2 01103#define OSSSYS_BASE__INST0_SEG3 01104#define OSSSYS_BASE__INST0_SEG4 01105#define OSSSYS_BASE__INST0_SEG5 011061107#define OSSSYS_BASE__INST1_SEG0 01108#define OSSSYS_BASE__INST1_SEG1 01109#define OSSSYS_BASE__INST1_SEG2 01110#define OSSSYS_BASE__INST1_SEG3 01111#define OSSSYS_BASE__INST1_SEG4 01112#define OSSSYS_BASE__INST1_SEG5 011131114#define OSSSYS_BASE__INST2_SEG0 01115#define OSSSYS_BASE__INST2_SEG1 01116#define OSSSYS_BASE__INST2_SEG2 01117#define OSSSYS_BASE__INST2_SEG3 01118#define OSSSYS_BASE__INST2_SEG4 01119#define OSSSYS_BASE__INST2_SEG5 011201121#define OSSSYS_BASE__INST3_SEG0 01122#define OSSSYS_BASE__INST3_SEG1 01123#define OSSSYS_BASE__INST3_SEG2 01124#define OSSSYS_BASE__INST3_SEG3 01125#define OSSSYS_BASE__INST3_SEG4 01126#define OSSSYS_BASE__INST3_SEG5 011271128#define OSSSYS_BASE__INST4_SEG0 01129#define OSSSYS_BASE__INST4_SEG1 01130#define OSSSYS_BASE__INST4_SEG2 01131#define OSSSYS_BASE__INST4_SEG3 01132#define OSSSYS_BASE__INST4_SEG4 01133#define OSSSYS_BASE__INST4_SEG5 011341135#define OSSSYS_BASE__INST5_SEG0 01136#define OSSSYS_BASE__INST5_SEG1 01137#define OSSSYS_BASE__INST5_SEG2 01138#define OSSSYS_BASE__INST5_SEG3 01139#define OSSSYS_BASE__INST5_SEG4 01140#define OSSSYS_BASE__INST5_SEG5 011411142#define OSSSYS_BASE__INST6_SEG0 01143#define OSSSYS_BASE__INST6_SEG1 01144#define OSSSYS_BASE__INST6_SEG2 01145#define OSSSYS_BASE__INST6_SEG3 01146#define OSSSYS_BASE__INST6_SEG4 01147#define OSSSYS_BASE__INST6_SEG5 011481149#define PCIE0_BASE__INST0_SEG0 0x024118001150#define PCIE0_BASE__INST0_SEG1 0x044400001151#define PCIE0_BASE__INST0_SEG2 01152#define PCIE0_BASE__INST0_SEG3 01153#define PCIE0_BASE__INST0_SEG4 01154#define PCIE0_BASE__INST0_SEG5 011551156#define PCIE0_BASE__INST1_SEG0 01157#define PCIE0_BASE__INST1_SEG1 01158#define PCIE0_BASE__INST1_SEG2 01159#define PCIE0_BASE__INST1_SEG3 01160#define PCIE0_BASE__INST1_SEG4 01161#define PCIE0_BASE__INST1_SEG5 011621163#define PCIE0_BASE__INST2_SEG0 01164#define PCIE0_BASE__INST2_SEG1 01165#define PCIE0_BASE__INST2_SEG2 01166#define PCIE0_BASE__INST2_SEG3 01167#define PCIE0_BASE__INST2_SEG4 01168#define PCIE0_BASE__INST2_SEG5 011691170#define PCIE0_BASE__INST3_SEG0 01171#define PCIE0_BASE__INST3_SEG1 01172#define PCIE0_BASE__INST3_SEG2 01173#define PCIE0_BASE__INST3_SEG3 01174#define PCIE0_BASE__INST3_SEG4 01175#define PCIE0_BASE__INST3_SEG5 011761177#define PCIE0_BASE__INST4_SEG0 01178#define PCIE0_BASE__INST4_SEG1 01179#define PCIE0_BASE__INST4_SEG2 01180#define PCIE0_BASE__INST4_SEG3 01181#define PCIE0_BASE__INST4_SEG4 01182#define PCIE0_BASE__INST4_SEG5 011831184#define PCIE0_BASE__INST5_SEG0 01185#define PCIE0_BASE__INST5_SEG1 01186#define PCIE0_BASE__INST5_SEG2 01187#define PCIE0_BASE__INST5_SEG3 01188#define PCIE0_BASE__INST5_SEG4 01189#define PCIE0_BASE__INST5_SEG5 011901191#define PCIE0_BASE__INST6_SEG0 01192#define PCIE0_BASE__INST6_SEG1 01193#define PCIE0_BASE__INST6_SEG2 01194#define PCIE0_BASE__INST6_SEG3 01195#define PCIE0_BASE__INST6_SEG4 01196#define PCIE0_BASE__INST6_SEG5 011971198#define SDMA0_BASE__INST0_SEG0 0x000012601199#define SDMA0_BASE__INST0_SEG1 0x024454001200#define SDMA0_BASE__INST0_SEG2 01201#define SDMA0_BASE__INST0_SEG3 01202#define SDMA0_BASE__INST0_SEG4 01203#define SDMA0_BASE__INST0_SEG5 012041205#define SDMA0_BASE__INST1_SEG0 01206#define SDMA0_BASE__INST1_SEG1 01207#define SDMA0_BASE__INST1_SEG2 01208#define SDMA0_BASE__INST1_SEG3 01209#define SDMA0_BASE__INST1_SEG4 01210#define SDMA0_BASE__INST1_SEG5 012111212#define SDMA0_BASE__INST2_SEG0 01213#define SDMA0_BASE__INST2_SEG1 01214#define SDMA0_BASE__INST2_SEG2 01215#define SDMA0_BASE__INST2_SEG3 01216#define SDMA0_BASE__INST2_SEG4 01217#define SDMA0_BASE__INST2_SEG5 012181219#define SDMA0_BASE__INST3_SEG0 01220#define SDMA0_BASE__INST3_SEG1 01221#define SDMA0_BASE__INST3_SEG2 01222#define SDMA0_BASE__INST3_SEG3 01223#define SDMA0_BASE__INST3_SEG4 01224#define SDMA0_BASE__INST3_SEG5 012251226#define SDMA0_BASE__INST4_SEG0 01227#define SDMA0_BASE__INST4_SEG1 01228#define SDMA0_BASE__INST4_SEG2 01229#define SDMA0_BASE__INST4_SEG3 01230#define SDMA0_BASE__INST4_SEG4 01231#define SDMA0_BASE__INST4_SEG5 012321233#define SDMA0_BASE__INST5_SEG0 01234#define SDMA0_BASE__INST5_SEG1 01235#define SDMA0_BASE__INST5_SEG2 01236#define SDMA0_BASE__INST5_SEG3 01237#define SDMA0_BASE__INST5_SEG4 01238#define SDMA0_BASE__INST5_SEG5 012391240#define SDMA0_BASE__INST6_SEG0 01241#define SDMA0_BASE__INST6_SEG1 01242#define SDMA0_BASE__INST6_SEG2 01243#define SDMA0_BASE__INST6_SEG3 01244#define SDMA0_BASE__INST6_SEG4 01245#define SDMA0_BASE__INST6_SEG5 012461247#define SDMA1_BASE__INST0_SEG0 0x000018601248#define SDMA1_BASE__INST0_SEG1 0x024458001249#define SDMA1_BASE__INST0_SEG2 01250#define SDMA1_BASE__INST0_SEG3 01251#define SDMA1_BASE__INST0_SEG4 01252#define SDMA1_BASE__INST0_SEG5 012531254#define SDMA1_BASE__INST1_SEG0 0x0001E0001255#define SDMA1_BASE__INST1_SEG1 0x024464001256#define SDMA1_BASE__INST1_SEG2 01257#define SDMA1_BASE__INST1_SEG3 01258#define SDMA1_BASE__INST1_SEG4 01259#define SDMA1_BASE__INST1_SEG5 012601261#define SDMA1_BASE__INST2_SEG0 0x0001E4001262#define SDMA1_BASE__INST2_SEG1 0x024468001263#define SDMA1_BASE__INST2_SEG2 01264#define SDMA1_BASE__INST2_SEG3 01265#define SDMA1_BASE__INST2_SEG4 01266#define SDMA1_BASE__INST2_SEG5 012671268#define SDMA1_BASE__INST3_SEG0 0x0001E8001269#define SDMA1_BASE__INST3_SEG1 0x02446C001270#define SDMA1_BASE__INST3_SEG2 01271#define SDMA1_BASE__INST3_SEG3 01272#define SDMA1_BASE__INST3_SEG4 01273#define SDMA1_BASE__INST3_SEG5 012741275#define SDMA1_BASE__INST4_SEG0 01276#define SDMA1_BASE__INST4_SEG1 01277#define SDMA1_BASE__INST4_SEG2 01278#define SDMA1_BASE__INST4_SEG3 01279#define SDMA1_BASE__INST4_SEG4 01280#define SDMA1_BASE__INST4_SEG5 012811282#define SDMA1_BASE__INST5_SEG0 01283#define SDMA1_BASE__INST5_SEG1 01284#define SDMA1_BASE__INST5_SEG2 01285#define SDMA1_BASE__INST5_SEG3 01286#define SDMA1_BASE__INST5_SEG4 01287#define SDMA1_BASE__INST5_SEG5 012881289#define SDMA1_BASE__INST6_SEG0 01290#define SDMA1_BASE__INST6_SEG1 01291#define SDMA1_BASE__INST6_SEG2 01292#define SDMA1_BASE__INST6_SEG3 01293#define SDMA1_BASE__INST6_SEG4 01294#define SDMA1_BASE__INST6_SEG5 012951296#define SMUIO_BASE__INST0_SEG0 0x000168001297#define SMUIO_BASE__INST0_SEG1 0x00016A001298#define SMUIO_BASE__INST0_SEG2 0x024010001299#define SMUIO_BASE__INST0_SEG3 0x034400001300#define SMUIO_BASE__INST0_SEG4 01301#define SMUIO_BASE__INST0_SEG5 013021303#define SMUIO_BASE__INST1_SEG0 01304#define SMUIO_BASE__INST1_SEG1 01305#define SMUIO_BASE__INST1_SEG2 01306#define SMUIO_BASE__INST1_SEG3 01307#define SMUIO_BASE__INST1_SEG4 01308#define SMUIO_BASE__INST1_SEG5 013091310#define SMUIO_BASE__INST2_SEG0 01311#define SMUIO_BASE__INST2_SEG1 01312#define SMUIO_BASE__INST2_SEG2 01313#define SMUIO_BASE__INST2_SEG3 01314#define SMUIO_BASE__INST2_SEG4 01315#define SMUIO_BASE__INST2_SEG5 013161317#define SMUIO_BASE__INST3_SEG0 01318#define SMUIO_BASE__INST3_SEG1 01319#define SMUIO_BASE__INST3_SEG2 01320#define SMUIO_BASE__INST3_SEG3 01321#define SMUIO_BASE__INST3_SEG4 01322#define SMUIO_BASE__INST3_SEG5 013231324#define SMUIO_BASE__INST4_SEG0 01325#define SMUIO_BASE__INST4_SEG1 01326#define SMUIO_BASE__INST4_SEG2 01327#define SMUIO_BASE__INST4_SEG3 01328#define SMUIO_BASE__INST4_SEG4 01329#define SMUIO_BASE__INST4_SEG5 013301331#define SMUIO_BASE__INST5_SEG0 01332#define SMUIO_BASE__INST5_SEG1 01333#define SMUIO_BASE__INST5_SEG2 01334#define SMUIO_BASE__INST5_SEG3 01335#define SMUIO_BASE__INST5_SEG4 01336#define SMUIO_BASE__INST5_SEG5 013371338#define SMUIO_BASE__INST6_SEG0 01339#define SMUIO_BASE__INST6_SEG1 01340#define SMUIO_BASE__INST6_SEG2 01341#define SMUIO_BASE__INST6_SEG3 01342#define SMUIO_BASE__INST6_SEG4 01343#define SMUIO_BASE__INST6_SEG5 013441345#define THM_BASE__INST0_SEG0 0x000166001346#define THM_BASE__INST0_SEG1 0x02400C001347#define THM_BASE__INST0_SEG2 01348#define THM_BASE__INST0_SEG3 01349#define THM_BASE__INST0_SEG4 01350#define THM_BASE__INST0_SEG5 013511352#define THM_BASE__INST1_SEG0 01353#define THM_BASE__INST1_SEG1 01354#define THM_BASE__INST1_SEG2 01355#define THM_BASE__INST1_SEG3 01356#define THM_BASE__INST1_SEG4 01357#define THM_BASE__INST1_SEG5 013581359#define THM_BASE__INST2_SEG0 01360#define THM_BASE__INST2_SEG1 01361#define THM_BASE__INST2_SEG2 01362#define THM_BASE__INST2_SEG3 01363#define THM_BASE__INST2_SEG4 01364#define THM_BASE__INST2_SEG5 013651366#define THM_BASE__INST3_SEG0 01367#define THM_BASE__INST3_SEG1 01368#define THM_BASE__INST3_SEG2 01369#define THM_BASE__INST3_SEG3 01370#define THM_BASE__INST3_SEG4 01371#define THM_BASE__INST3_SEG5 013721373#define THM_BASE__INST4_SEG0 01374#define THM_BASE__INST4_SEG1 01375#define THM_BASE__INST4_SEG2 01376#define THM_BASE__INST4_SEG3 01377#define THM_BASE__INST4_SEG4 01378#define THM_BASE__INST4_SEG5 013791380#define THM_BASE__INST5_SEG0 01381#define THM_BASE__INST5_SEG1 01382#define THM_BASE__INST5_SEG2 01383#define THM_BASE__INST5_SEG3 01384#define THM_BASE__INST5_SEG4 01385#define THM_BASE__INST5_SEG5 013861387#define THM_BASE__INST6_SEG0 01388#define THM_BASE__INST6_SEG1 01389#define THM_BASE__INST6_SEG2 01390#define THM_BASE__INST6_SEG3 01391#define THM_BASE__INST6_SEG4 01392#define THM_BASE__INST6_SEG5 013931394#define UMC_BASE__INST0_SEG0 0x000140001395#define UMC_BASE__INST0_SEG1 0x000540001396#define UMC_BASE__INST0_SEG2 0x024258001397#define UMC_BASE__INST0_SEG3 01398#define UMC_BASE__INST0_SEG4 01399#define UMC_BASE__INST0_SEG5 014001401#define UMC_BASE__INST1_SEG0 0x000940001402#define UMC_BASE__INST1_SEG1 0x000D40001403#define UMC_BASE__INST1_SEG2 0x02425C001404#define UMC_BASE__INST1_SEG3 01405#define UMC_BASE__INST1_SEG4 01406#define UMC_BASE__INST1_SEG5 014071408#define UMC_BASE__INST2_SEG0 0x001140001409#define UMC_BASE__INST2_SEG1 0x001540001410#define UMC_BASE__INST2_SEG2 0x024260001411#define UMC_BASE__INST2_SEG3 01412#define UMC_BASE__INST2_SEG4 01413#define UMC_BASE__INST2_SEG5 014141415#define UMC_BASE__INST3_SEG0 0x001940001416#define UMC_BASE__INST3_SEG1 0x001D40001417#define UMC_BASE__INST3_SEG2 0x024264001418#define UMC_BASE__INST3_SEG3 01419#define UMC_BASE__INST3_SEG4 01420#define UMC_BASE__INST3_SEG5 014211422#define UMC_BASE__INST4_SEG0 01423#define UMC_BASE__INST4_SEG1 01424#define UMC_BASE__INST4_SEG2 01425#define UMC_BASE__INST4_SEG3 01426#define UMC_BASE__INST4_SEG4 01427#define UMC_BASE__INST4_SEG5 014281429#define UMC_BASE__INST5_SEG0 01430#define UMC_BASE__INST5_SEG1 01431#define UMC_BASE__INST5_SEG2 01432#define UMC_BASE__INST5_SEG3 01433#define UMC_BASE__INST5_SEG4 01434#define UMC_BASE__INST5_SEG5 014351436#define UMC_BASE__INST6_SEG0 01437#define UMC_BASE__INST6_SEG1 01438#define UMC_BASE__INST6_SEG2 01439#define UMC_BASE__INST6_SEG3 01440#define UMC_BASE__INST6_SEG4 01441#define UMC_BASE__INST6_SEG5 014421443#define VCN_BASE__INST0_SEG0 0x000078001444#define VCN_BASE__INST0_SEG1 0x00007E001445#define VCN_BASE__INST0_SEG2 0x024030001446#define VCN_BASE__INST0_SEG3 01447#define VCN_BASE__INST0_SEG4 01448#define VCN_BASE__INST0_SEG5 014491450#define VCN_BASE__INST1_SEG0 0x00007A001451#define VCN_BASE__INST1_SEG1 0x000090001452#define VCN_BASE__INST1_SEG2 0x024450001453#define VCN_BASE__INST1_SEG3 01454#define VCN_BASE__INST1_SEG4 01455#define VCN_BASE__INST1_SEG5 014561457#define VCN_BASE__INST2_SEG0 01458#define VCN_BASE__INST2_SEG1 01459#define VCN_BASE__INST2_SEG2 01460#define VCN_BASE__INST2_SEG3 01461#define VCN_BASE__INST2_SEG4 01462#define VCN_BASE__INST2_SEG5 014631464#define VCN_BASE__INST3_SEG0 01465#define VCN_BASE__INST3_SEG1 01466#define VCN_BASE__INST3_SEG2 01467#define VCN_BASE__INST3_SEG3 01468#define VCN_BASE__INST3_SEG4 01469#define VCN_BASE__INST3_SEG5 014701471#define VCN_BASE__INST4_SEG0 01472#define VCN_BASE__INST4_SEG1 01473#define VCN_BASE__INST4_SEG2 01474#define VCN_BASE__INST4_SEG3 01475#define VCN_BASE__INST4_SEG4 01476#define VCN_BASE__INST4_SEG5 014771478#define VCN_BASE__INST5_SEG0 01479#define VCN_BASE__INST5_SEG1 01480#define VCN_BASE__INST5_SEG2 01481#define VCN_BASE__INST5_SEG3 01482#define VCN_BASE__INST5_SEG4 01483#define VCN_BASE__INST5_SEG5 014841485#define VCN_BASE__INST6_SEG0 01486#define VCN_BASE__INST6_SEG1 01487#define VCN_BASE__INST6_SEG2 01488#define VCN_BASE__INST6_SEG3 01489#define VCN_BASE__INST6_SEG4 01490#define VCN_BASE__INST6_SEG5 014911492#define WAFL0_BASE__INST0_SEG0 0x024380001493#define WAFL0_BASE__INST0_SEG1 0x048800001494#define WAFL0_BASE__INST0_SEG2 01495#define WAFL0_BASE__INST0_SEG3 01496#define WAFL0_BASE__INST0_SEG4 01497#define WAFL0_BASE__INST0_SEG5 014981499#define WAFL0_BASE__INST1_SEG0 01500#define WAFL0_BASE__INST1_SEG1 01501#define WAFL0_BASE__INST1_SEG2 01502#define WAFL0_BASE__INST1_SEG3 01503#define WAFL0_BASE__INST1_SEG4 01504#define WAFL0_BASE__INST1_SEG5 015051506#define WAFL0_BASE__INST2_SEG0 01507#define WAFL0_BASE__INST2_SEG1 01508#define WAFL0_BASE__INST2_SEG2 01509#define WAFL0_BASE__INST2_SEG3 01510#define WAFL0_BASE__INST2_SEG4 01511#define WAFL0_BASE__INST2_SEG5 015121513#define WAFL0_BASE__INST3_SEG0 01514#define WAFL0_BASE__INST3_SEG1 01515#define WAFL0_BASE__INST3_SEG2 01516#define WAFL0_BASE__INST3_SEG3 01517#define WAFL0_BASE__INST3_SEG4 01518#define WAFL0_BASE__INST3_SEG5 015191520#define WAFL0_BASE__INST4_SEG0 01521#define WAFL0_BASE__INST4_SEG1 01522#define WAFL0_BASE__INST4_SEG2 01523#define WAFL0_BASE__INST4_SEG3 01524#define WAFL0_BASE__INST4_SEG4 01525#define WAFL0_BASE__INST4_SEG5 015261527#define WAFL0_BASE__INST5_SEG0 01528#define WAFL0_BASE__INST5_SEG1 01529#define WAFL0_BASE__INST5_SEG2 01530#define WAFL0_BASE__INST5_SEG3 01531#define WAFL0_BASE__INST5_SEG4 01532#define WAFL0_BASE__INST5_SEG5 015331534#define WAFL0_BASE__INST6_SEG0 01535#define WAFL0_BASE__INST6_SEG1 01536#define WAFL0_BASE__INST6_SEG2 01537#define WAFL0_BASE__INST6_SEG3 01538#define WAFL0_BASE__INST6_SEG4 01539#define WAFL0_BASE__INST6_SEG5 015401541#define WAFL1_BASE__INST0_SEG0 01542#define WAFL1_BASE__INST0_SEG1 0x013000001543#define WAFL1_BASE__INST0_SEG2 0x024108001544#define WAFL1_BASE__INST0_SEG3 01545#define WAFL1_BASE__INST0_SEG4 01546#define WAFL1_BASE__INST0_SEG5 015471548#define WAFL1_BASE__INST1_SEG0 01549#define WAFL1_BASE__INST1_SEG1 01550#define WAFL1_BASE__INST1_SEG2 01551#define WAFL1_BASE__INST1_SEG3 01552#define WAFL1_BASE__INST1_SEG4 01553#define WAFL1_BASE__INST1_SEG5 015541555#define WAFL1_BASE__INST2_SEG0 01556#define WAFL1_BASE__INST2_SEG1 01557#define WAFL1_BASE__INST2_SEG2 01558#define WAFL1_BASE__INST2_SEG3 01559#define WAFL1_BASE__INST2_SEG4 01560#define WAFL1_BASE__INST2_SEG5 015611562#define WAFL1_BASE__INST3_SEG0 01563#define WAFL1_BASE__INST3_SEG1 01564#define WAFL1_BASE__INST3_SEG2 01565#define WAFL1_BASE__INST3_SEG3 01566#define WAFL1_BASE__INST3_SEG4 01567#define WAFL1_BASE__INST3_SEG5 015681569#define WAFL1_BASE__INST4_SEG0 01570#define WAFL1_BASE__INST4_SEG1 01571#define WAFL1_BASE__INST4_SEG2 01572#define WAFL1_BASE__INST4_SEG3 01573#define WAFL1_BASE__INST4_SEG4 01574#define WAFL1_BASE__INST4_SEG5 015751576#define WAFL1_BASE__INST5_SEG0 01577#define WAFL1_BASE__INST5_SEG1 01578#define WAFL1_BASE__INST5_SEG2 01579#define WAFL1_BASE__INST5_SEG3 01580#define WAFL1_BASE__INST5_SEG4 01581#define WAFL1_BASE__INST5_SEG5 015821583#define WAFL1_BASE__INST6_SEG0 01584#define WAFL1_BASE__INST6_SEG1 01585#define WAFL1_BASE__INST6_SEG2 01586#define WAFL1_BASE__INST6_SEG3 01587#define WAFL1_BASE__INST6_SEG4 01588#define WAFL1_BASE__INST6_SEG5 015891590#define XGMI0_BASE__INST0_SEG0 0x02438C001591#define XGMI0_BASE__INST0_SEG1 0x046800001592#define XGMI0_BASE__INST0_SEG2 0x049400001593#define XGMI0_BASE__INST0_SEG3 01594#define XGMI0_BASE__INST0_SEG4 01595#define XGMI0_BASE__INST0_SEG5 015961597#define XGMI0_BASE__INST1_SEG0 01598#define XGMI0_BASE__INST1_SEG1 01599#define XGMI0_BASE__INST1_SEG2 01600#define XGMI0_BASE__INST1_SEG3 01601#define XGMI0_BASE__INST1_SEG4 01602#define XGMI0_BASE__INST1_SEG5 016031604#define XGMI0_BASE__INST2_SEG0 01605#define XGMI0_BASE__INST2_SEG1 01606#define XGMI0_BASE__INST2_SEG2 01607#define XGMI0_BASE__INST2_SEG3 01608#define XGMI0_BASE__INST2_SEG4 01609#define XGMI0_BASE__INST2_SEG5 016101611#define XGMI0_BASE__INST3_SEG0 01612#define XGMI0_BASE__INST3_SEG1 01613#define XGMI0_BASE__INST3_SEG2 01614#define XGMI0_BASE__INST3_SEG3 01615#define XGMI0_BASE__INST3_SEG4 01616#define XGMI0_BASE__INST3_SEG5 016171618#define XGMI0_BASE__INST4_SEG0 01619#define XGMI0_BASE__INST4_SEG1 01620#define XGMI0_BASE__INST4_SEG2 01621#define XGMI0_BASE__INST4_SEG3 01622#define XGMI0_BASE__INST4_SEG4 01623#define XGMI0_BASE__INST4_SEG5 016241625#define XGMI0_BASE__INST5_SEG0 01626#define XGMI0_BASE__INST5_SEG1 01627#define XGMI0_BASE__INST5_SEG2 01628#define XGMI0_BASE__INST5_SEG3 01629#define XGMI0_BASE__INST5_SEG4 01630#define XGMI0_BASE__INST5_SEG5 016311632#define XGMI0_BASE__INST6_SEG0 01633#define XGMI0_BASE__INST6_SEG1 01634#define XGMI0_BASE__INST6_SEG2 01635#define XGMI0_BASE__INST6_SEG3 01636#define XGMI0_BASE__INST6_SEG4 01637#define XGMI0_BASE__INST6_SEG5 016381639#define XGMI1_BASE__INST0_SEG0 0x024390001640#define XGMI1_BASE__INST0_SEG1 0x046C00001641#define XGMI1_BASE__INST0_SEG2 0x049800001642#define XGMI1_BASE__INST0_SEG3 01643#define XGMI1_BASE__INST0_SEG4 01644#define XGMI1_BASE__INST0_SEG5 016451646#define XGMI1_BASE__INST1_SEG0 01647#define XGMI1_BASE__INST1_SEG1 01648#define XGMI1_BASE__INST1_SEG2 01649#define XGMI1_BASE__INST1_SEG3 01650#define XGMI1_BASE__INST1_SEG4 01651#define XGMI1_BASE__INST1_SEG5 016521653#define XGMI1_BASE__INST2_SEG0 01654#define XGMI1_BASE__INST2_SEG1 01655#define XGMI1_BASE__INST2_SEG2 01656#define XGMI1_BASE__INST2_SEG3 01657#define XGMI1_BASE__INST2_SEG4 01658#define XGMI1_BASE__INST2_SEG5 016591660#define XGMI1_BASE__INST3_SEG0 01661#define XGMI1_BASE__INST3_SEG1 01662#define XGMI1_BASE__INST3_SEG2 01663#define XGMI1_BASE__INST3_SEG3 01664#define XGMI1_BASE__INST3_SEG4 01665#define XGMI1_BASE__INST3_SEG5 016661667#define XGMI1_BASE__INST4_SEG0 01668#define XGMI1_BASE__INST4_SEG1 01669#define XGMI1_BASE__INST4_SEG2 01670#define XGMI1_BASE__INST4_SEG3 01671#define XGMI1_BASE__INST4_SEG4 01672#define XGMI1_BASE__INST4_SEG5 016731674#define XGMI1_BASE__INST5_SEG0 01675#define XGMI1_BASE__INST5_SEG1 01676#define XGMI1_BASE__INST5_SEG2 01677#define XGMI1_BASE__INST5_SEG3 01678#define XGMI1_BASE__INST5_SEG4 01679#define XGMI1_BASE__INST5_SEG5 016801681#define XGMI1_BASE__INST6_SEG0 01682#define XGMI1_BASE__INST6_SEG1 01683#define XGMI1_BASE__INST6_SEG2 01684#define XGMI1_BASE__INST6_SEG3 01685#define XGMI1_BASE__INST6_SEG4 01686#define XGMI1_BASE__INST6_SEG5 016871688#define XGMI2_BASE__INST0_SEG0 0x047000001689#define XGMI2_BASE__INST0_SEG1 0x049C00001690#define XGMI2_BASE__INST0_SEG2 01691#define XGMI2_BASE__INST0_SEG3 01692#define XGMI2_BASE__INST0_SEG4 01693#define XGMI2_BASE__INST0_SEG5 016941695#define XGMI2_BASE__INST1_SEG0 0x047400001696#define XGMI2_BASE__INST1_SEG1 0x04A000001697#define XGMI2_BASE__INST1_SEG2 01698#define XGMI2_BASE__INST1_SEG3 01699#define XGMI2_BASE__INST1_SEG4 01700#define XGMI2_BASE__INST1_SEG5 017011702#define XGMI2_BASE__INST2_SEG0 0x047800001703#define XGMI2_BASE__INST2_SEG1 0x04A400001704#define XGMI2_BASE__INST2_SEG2 01705#define XGMI2_BASE__INST2_SEG3 01706#define XGMI2_BASE__INST2_SEG4 01707#define XGMI2_BASE__INST2_SEG5 017081709#define XGMI2_BASE__INST3_SEG0 0x047C00001710#define XGMI2_BASE__INST3_SEG1 0x04A800001711#define XGMI2_BASE__INST3_SEG2 01712#define XGMI2_BASE__INST3_SEG3 01713#define XGMI2_BASE__INST3_SEG4 01714#define XGMI2_BASE__INST3_SEG5 017151716#define XGMI2_BASE__INST4_SEG0 0x048000001717#define XGMI2_BASE__INST4_SEG1 0x04AC00001718#define XGMI2_BASE__INST4_SEG2 01719#define XGMI2_BASE__INST4_SEG3 01720#define XGMI2_BASE__INST4_SEG4 01721#define XGMI2_BASE__INST4_SEG5 017221723#define XGMI2_BASE__INST5_SEG0 0x048400001724#define XGMI2_BASE__INST5_SEG1 0x04B000001725#define XGMI2_BASE__INST5_SEG2 01726#define XGMI2_BASE__INST5_SEG3 01727#define XGMI2_BASE__INST5_SEG4 01728#define XGMI2_BASE__INST5_SEG5 017291730#define XGMI2_BASE__INST6_SEG0 01731#define XGMI2_BASE__INST6_SEG1 01732#define XGMI2_BASE__INST6_SEG2 01733#define XGMI2_BASE__INST6_SEG3 01734#define XGMI2_BASE__INST6_SEG4 01735#define XGMI2_BASE__INST6_SEG5 017361737#endif173817391740