Path: blob/master/drivers/gpu/drm/amd/include/arct_ip_offset.h
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/*1* Copyright (C) 2018 Advanced Micro Devices, Inc.2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice shall be included11* in all copies or substantial portions of the Software.12*13* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS14* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,15* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL16* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN17* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN18* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.19*/20#ifndef _arct_ip_offset_HEADER21#define _arct_ip_offset_HEADER2223#define MAX_INSTANCE 824#define MAX_SEGMENT 6252627struct IP_BASE_INSTANCE {28unsigned int segment[MAX_SEGMENT];29} __maybe_unused;3031struct IP_BASE {32struct IP_BASE_INSTANCE instance[MAX_INSTANCE];33} __maybe_unused;343536static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x00012460, 0x00408C00, 0, 0, 0 } },37{ { 0, 0, 0, 0, 0, 0 } },38{ { 0, 0, 0, 0, 0, 0 } },39{ { 0, 0, 0, 0, 0, 0 } },40{ { 0, 0, 0, 0, 0, 0 } },41{ { 0, 0, 0, 0, 0, 0 } },42{ { 0, 0, 0, 0, 0, 0 } },43{ { 0, 0, 0, 0, 0, 0 } } } };44static const struct IP_BASE CLK_BASE ={ { { { 0x000120C0, 0x00016C00, 0x00401800, 0, 0, 0 } },45{ { 0x000120E0, 0x00016E00, 0x00401C00, 0, 0, 0 } },46{ { 0x00012100, 0x00017000, 0x00402000, 0, 0, 0 } },47{ { 0x00012120, 0x00017200, 0x00402400, 0, 0, 0 } },48{ { 0x000136C0, 0x0001B000, 0x0042D800, 0, 0, 0 } },49{ { 0x00013720, 0x0001B200, 0x0042E400, 0, 0, 0 } },50{ { 0x000125E0, 0x00017E00, 0x0040BC00, 0, 0, 0 } },51{ { 0, 0, 0, 0, 0, 0 } } } };52static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x000125C0, 0x0040B800, 0, 0, 0 } },53{ { 0, 0, 0, 0, 0, 0 } },54{ { 0, 0, 0, 0, 0, 0 } },55{ { 0, 0, 0, 0, 0, 0 } },56{ { 0, 0, 0, 0, 0, 0 } },57{ { 0, 0, 0, 0, 0, 0 } },58{ { 0, 0, 0, 0, 0, 0 } },59{ { 0, 0, 0, 0, 0, 0 } } } };60static const struct IP_BASE FUSE_BASE ={ { { { 0x000120A0, 0x00017400, 0x00401400, 0, 0, 0 } },61{ { 0, 0, 0, 0, 0, 0 } },62{ { 0, 0, 0, 0, 0, 0 } },63{ { 0, 0, 0, 0, 0, 0 } },64{ { 0, 0, 0, 0, 0, 0 } },65{ { 0, 0, 0, 0, 0, 0 } },66{ { 0, 0, 0, 0, 0, 0 } },67{ { 0, 0, 0, 0, 0, 0 } } } };68static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0x00012160, 0x00402C00, 0, 0 } },69{ { 0, 0, 0, 0, 0, 0 } },70{ { 0, 0, 0, 0, 0, 0 } },71{ { 0, 0, 0, 0, 0, 0 } },72{ { 0, 0, 0, 0, 0, 0 } },73{ { 0, 0, 0, 0, 0, 0 } },74{ { 0, 0, 0, 0, 0, 0 } },75{ { 0, 0, 0, 0, 0, 0 } } } };76static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x00012520, 0x0040A400, 0, 0, 0 } },77{ { 0, 0, 0, 0, 0, 0 } },78{ { 0, 0, 0, 0, 0, 0 } },79{ { 0, 0, 0, 0, 0, 0 } },80{ { 0, 0, 0, 0, 0, 0 } },81{ { 0, 0, 0, 0, 0, 0 } },82{ { 0, 0, 0, 0, 0, 0 } },83{ { 0, 0, 0, 0, 0, 0 } } } };84static const struct IP_BASE MMHUB_BASE ={ { { { 0x00012440, 0x0001A000, 0x00408800, 0, 0, 0 } },85{ { 0, 0, 0, 0, 0, 0 } },86{ { 0, 0, 0, 0, 0, 0 } },87{ { 0, 0, 0, 0, 0, 0 } },88{ { 0, 0, 0, 0, 0, 0 } },89{ { 0, 0, 0, 0, 0, 0 } },90{ { 0, 0, 0, 0, 0, 0 } },91{ { 0, 0, 0, 0, 0, 0 } } } };92static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },93{ { 0, 0, 0, 0, 0, 0 } },94{ { 0, 0, 0, 0, 0, 0 } },95{ { 0, 0, 0, 0, 0, 0 } },96{ { 0, 0, 0, 0, 0, 0 } },97{ { 0, 0, 0, 0, 0, 0 } },98{ { 0, 0, 0, 0, 0, 0 } },99{ { 0, 0, 0, 0, 0, 0 } } } };100static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },101{ { 0, 0, 0, 0, 0, 0 } },102{ { 0, 0, 0, 0, 0, 0 } },103{ { 0, 0, 0, 0, 0, 0 } },104{ { 0, 0, 0, 0, 0, 0 } },105{ { 0, 0, 0, 0, 0, 0 } },106{ { 0, 0, 0, 0, 0, 0 } },107{ { 0, 0, 0, 0, 0, 0 } } } };108static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x00012D80, 0x0041B000 } },109{ { 0, 0, 0, 0, 0, 0 } },110{ { 0, 0, 0, 0, 0, 0 } },111{ { 0, 0, 0, 0, 0, 0 } },112{ { 0, 0, 0, 0, 0, 0 } },113{ { 0, 0, 0, 0, 0, 0 } },114{ { 0, 0, 0, 0, 0, 0 } },115{ { 0, 0, 0, 0, 0, 0 } } } };116static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x00012500, 0x0040A000, 0, 0, 0 } },117{ { 0, 0, 0, 0, 0, 0 } },118{ { 0, 0, 0, 0, 0, 0 } },119{ { 0, 0, 0, 0, 0, 0 } },120{ { 0, 0, 0, 0, 0, 0 } },121{ { 0, 0, 0, 0, 0, 0 } },122{ { 0, 0, 0, 0, 0, 0 } },123{ { 0, 0, 0, 0, 0, 0 } } } };124static const struct IP_BASE PCIE0_BASE ={ { { { 0x000128C0, 0x00411800, 0x04440000, 0, 0, 0 } },125{ { 0, 0, 0, 0, 0, 0 } },126{ { 0, 0, 0, 0, 0, 0 } },127{ { 0, 0, 0, 0, 0, 0 } },128{ { 0, 0, 0, 0, 0, 0 } },129{ { 0, 0, 0, 0, 0, 0 } },130{ { 0, 0, 0, 0, 0, 0 } },131{ { 0, 0, 0, 0, 0, 0 } } } };132static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x00012540, 0x0040A800, 0, 0, 0 } },133{ { 0, 0, 0, 0, 0, 0 } },134{ { 0, 0, 0, 0, 0, 0 } },135{ { 0, 0, 0, 0, 0, 0 } },136{ { 0, 0, 0, 0, 0, 0 } },137{ { 0, 0, 0, 0, 0, 0 } },138{ { 0, 0, 0, 0, 0, 0 } },139{ { 0, 0, 0, 0, 0, 0 } } } };140static const struct IP_BASE SDMA1_BASE ={ { { { 0x00001860, 0x00012560, 0x0040AC00, 0, 0, 0 } },141{ { 0, 0, 0, 0, 0, 0 } },142{ { 0, 0, 0, 0, 0, 0 } },143{ { 0, 0, 0, 0, 0, 0 } },144{ { 0, 0, 0, 0, 0, 0 } },145{ { 0, 0, 0, 0, 0, 0 } },146{ { 0, 0, 0, 0, 0, 0 } },147{ { 0, 0, 0, 0, 0, 0 } } } };148static const struct IP_BASE SDMA2_BASE ={ { { { 0x00013760, 0x0001E000, 0x0042EC00, 0, 0, 0 } },149{ { 0, 0, 0, 0, 0, 0 } },150{ { 0, 0, 0, 0, 0, 0 } },151{ { 0, 0, 0, 0, 0, 0 } },152{ { 0, 0, 0, 0, 0, 0 } },153{ { 0, 0, 0, 0, 0, 0 } },154{ { 0, 0, 0, 0, 0, 0 } },155{ { 0, 0, 0, 0, 0, 0 } } } };156static const struct IP_BASE SDMA3_BASE ={ { { { 0x00013780, 0x0001E400, 0x0042F000, 0, 0, 0 } },157{ { 0, 0, 0, 0, 0, 0 } },158{ { 0, 0, 0, 0, 0, 0 } },159{ { 0, 0, 0, 0, 0, 0 } },160{ { 0, 0, 0, 0, 0, 0 } },161{ { 0, 0, 0, 0, 0, 0 } },162{ { 0, 0, 0, 0, 0, 0 } },163{ { 0, 0, 0, 0, 0, 0 } } } };164static const struct IP_BASE SDMA4_BASE ={ { { { 0x000137A0, 0x0001E800, 0x0042F400, 0, 0, 0 } },165{ { 0, 0, 0, 0, 0, 0 } },166{ { 0, 0, 0, 0, 0, 0 } },167{ { 0, 0, 0, 0, 0, 0 } },168{ { 0, 0, 0, 0, 0, 0 } },169{ { 0, 0, 0, 0, 0, 0 } },170{ { 0, 0, 0, 0, 0, 0 } },171{ { 0, 0, 0, 0, 0, 0 } } } };172static const struct IP_BASE SDMA5_BASE ={ { { { 0x000137C0, 0x0001EC00, 0x0042F800, 0, 0, 0 } },173{ { 0, 0, 0, 0, 0, 0 } },174{ { 0, 0, 0, 0, 0, 0 } },175{ { 0, 0, 0, 0, 0, 0 } },176{ { 0, 0, 0, 0, 0, 0 } },177{ { 0, 0, 0, 0, 0, 0 } },178{ { 0, 0, 0, 0, 0, 0 } },179{ { 0, 0, 0, 0, 0, 0 } } } };180static const struct IP_BASE SDMA6_BASE ={ { { { 0x000137E0, 0x0001F000, 0x0042FC00, 0, 0, 0 } },181{ { 0, 0, 0, 0, 0, 0 } },182{ { 0, 0, 0, 0, 0, 0 } },183{ { 0, 0, 0, 0, 0, 0 } },184{ { 0, 0, 0, 0, 0, 0 } },185{ { 0, 0, 0, 0, 0, 0 } },186{ { 0, 0, 0, 0, 0, 0 } },187{ { 0, 0, 0, 0, 0, 0 } } } };188static const struct IP_BASE SDMA7_BASE ={ { { { 0x00013800, 0x0001F400, 0x00430000, 0, 0, 0 } },189{ { 0, 0, 0, 0, 0, 0 } },190{ { 0, 0, 0, 0, 0, 0 } },191{ { 0, 0, 0, 0, 0, 0 } },192{ { 0, 0, 0, 0, 0, 0 } },193{ { 0, 0, 0, 0, 0, 0 } },194{ { 0, 0, 0, 0, 0, 0 } },195{ { 0, 0, 0, 0, 0, 0 } } } };196static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } },197{ { 0, 0, 0, 0, 0, 0 } },198{ { 0, 0, 0, 0, 0, 0 } },199{ { 0, 0, 0, 0, 0, 0 } },200{ { 0, 0, 0, 0, 0, 0 } },201{ { 0, 0, 0, 0, 0, 0 } } } };202static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } },203{ { 0, 0, 0, 0, 0, 0 } },204{ { 0, 0, 0, 0, 0, 0 } },205{ { 0, 0, 0, 0, 0, 0 } },206{ { 0, 0, 0, 0, 0, 0 } },207{ { 0, 0, 0, 0, 0, 0 } } } };208static const struct IP_BASE UMC_BASE ={ { { { 0x000132C0, 0x00014000, 0x00425800, 0, 0, 0 } },209{ { 0x000132E0, 0x00054000, 0x00425C00, 0, 0, 0 } },210{ { 0x00013300, 0x00094000, 0x00426000, 0, 0, 0 } },211{ { 0x00013320, 0x000D4000, 0x00426400, 0, 0, 0 } },212{ { 0x00013340, 0x00114000, 0x00426800, 0, 0, 0 } },213{ { 0x00013360, 0x00154000, 0x00426C00, 0, 0, 0 } },214{ { 0x00013380, 0x00194000, 0x00427000, 0, 0, 0 } },215{ { 0x000133A0, 0x001D4000, 0x00427400, 0, 0, 0 } } } };216static const struct IP_BASE UVD_BASE ={ { { { 0x00007800, 0x00007E00, 0x00012180, 0x00403000, 0, 0 } },217{ { 0x00007A00, 0x00009000, 0x000136E0, 0x0042DC00, 0, 0 } },218{ { 0, 0, 0, 0, 0, 0 } },219{ { 0, 0, 0, 0, 0, 0 } },220{ { 0, 0, 0, 0, 0, 0 } },221{ { 0, 0, 0, 0, 0, 0 } },222{ { 0, 0, 0, 0, 0, 0 } },223{ { 0, 0, 0, 0, 0, 0 } } } };224static const struct IP_BASE DBGU_IO_BASE ={ { { { 0x000001E0, 0x000125A0, 0x0040B400, 0, 0, 0 } },225{ { 0, 0, 0, 0, 0, 0 } },226{ { 0, 0, 0, 0, 0, 0 } },227{ { 0, 0, 0, 0, 0, 0 } },228{ { 0, 0, 0, 0, 0, 0 } },229{ { 0, 0, 0, 0, 0, 0 } },230{ { 0, 0, 0, 0, 0, 0 } },231{ { 0, 0, 0, 0, 0, 0 } } } };232static const struct IP_BASE RSMU_BASE ={ { { { 0x00012000, 0, 0, 0, 0, 0 } },233{ { 0, 0, 0, 0, 0, 0 } },234{ { 0, 0, 0, 0, 0, 0 } },235{ { 0, 0, 0, 0, 0, 0 } },236{ { 0, 0, 0, 0, 0, 0 } },237{ { 0, 0, 0, 0, 0, 0 } },238{ { 0, 0, 0, 0, 0, 0 } },239{ { 0, 0, 0, 0, 0, 0 } } } };240241242243#define ATHUB_BASE__INST0_SEG0 0x00000C20244#define ATHUB_BASE__INST0_SEG1 0x00012460245#define ATHUB_BASE__INST0_SEG2 0x00408C00246#define ATHUB_BASE__INST0_SEG3 0247#define ATHUB_BASE__INST0_SEG4 0248#define ATHUB_BASE__INST0_SEG5 0249250#define ATHUB_BASE__INST1_SEG0 0251#define ATHUB_BASE__INST1_SEG1 0252#define ATHUB_BASE__INST1_SEG2 0253#define ATHUB_BASE__INST1_SEG3 0254#define ATHUB_BASE__INST1_SEG4 0255#define ATHUB_BASE__INST1_SEG5 0256257#define ATHUB_BASE__INST2_SEG0 0258#define ATHUB_BASE__INST2_SEG1 0259#define ATHUB_BASE__INST2_SEG2 0260#define ATHUB_BASE__INST2_SEG3 0261#define ATHUB_BASE__INST2_SEG4 0262#define ATHUB_BASE__INST2_SEG5 0263264#define ATHUB_BASE__INST3_SEG0 0265#define ATHUB_BASE__INST3_SEG1 0266#define ATHUB_BASE__INST3_SEG2 0267#define ATHUB_BASE__INST3_SEG3 0268#define ATHUB_BASE__INST3_SEG4 0269#define ATHUB_BASE__INST3_SEG5 0270271#define ATHUB_BASE__INST4_SEG0 0272#define ATHUB_BASE__INST4_SEG1 0273#define ATHUB_BASE__INST4_SEG2 0274#define ATHUB_BASE__INST4_SEG3 0275#define ATHUB_BASE__INST4_SEG4 0276#define ATHUB_BASE__INST4_SEG5 0277278#define ATHUB_BASE__INST5_SEG0 0279#define ATHUB_BASE__INST5_SEG1 0280#define ATHUB_BASE__INST5_SEG2 0281#define ATHUB_BASE__INST5_SEG3 0282#define ATHUB_BASE__INST5_SEG4 0283#define ATHUB_BASE__INST5_SEG5 0284285#define ATHUB_BASE__INST6_SEG0 0286#define ATHUB_BASE__INST6_SEG1 0287#define ATHUB_BASE__INST6_SEG2 0288#define ATHUB_BASE__INST6_SEG3 0289#define ATHUB_BASE__INST6_SEG4 0290#define ATHUB_BASE__INST6_SEG5 0291292#define ATHUB_BASE__INST7_SEG0 0293#define ATHUB_BASE__INST7_SEG1 0294#define ATHUB_BASE__INST7_SEG2 0295#define ATHUB_BASE__INST7_SEG3 0296#define ATHUB_BASE__INST7_SEG4 0297#define ATHUB_BASE__INST7_SEG5 0298299#define CLK_BASE__INST0_SEG0 0x000120C0300#define CLK_BASE__INST0_SEG1 0x00016C00301#define CLK_BASE__INST0_SEG2 0x00401800302#define CLK_BASE__INST0_SEG3 0303#define CLK_BASE__INST0_SEG4 0304#define CLK_BASE__INST0_SEG5 0305306#define CLK_BASE__INST1_SEG0 0x000120E0307#define CLK_BASE__INST1_SEG1 0x00016E00308#define CLK_BASE__INST1_SEG2 0x00401C00309#define CLK_BASE__INST1_SEG3 0310#define CLK_BASE__INST1_SEG4 0311#define CLK_BASE__INST1_SEG5 0312313#define CLK_BASE__INST2_SEG0 0x00012100314#define CLK_BASE__INST2_SEG1 0x00017000315#define CLK_BASE__INST2_SEG2 0x00402000316#define CLK_BASE__INST2_SEG3 0317#define CLK_BASE__INST2_SEG4 0318#define CLK_BASE__INST2_SEG5 0319320#define CLK_BASE__INST3_SEG0 0x00012120321#define CLK_BASE__INST3_SEG1 0x00017200322#define CLK_BASE__INST3_SEG2 0x00402400323#define CLK_BASE__INST3_SEG3 0324#define CLK_BASE__INST3_SEG4 0325#define CLK_BASE__INST3_SEG5 0326327#define CLK_BASE__INST4_SEG0 0x000136C0328#define CLK_BASE__INST4_SEG1 0x0001B000329#define CLK_BASE__INST4_SEG2 0x0042D800330#define CLK_BASE__INST4_SEG3 0331#define CLK_BASE__INST4_SEG4 0332#define CLK_BASE__INST4_SEG5 0333334#define CLK_BASE__INST5_SEG0 0x00013720335#define CLK_BASE__INST5_SEG1 0x0001B200336#define CLK_BASE__INST5_SEG2 0x0042E400337#define CLK_BASE__INST5_SEG3 0338#define CLK_BASE__INST5_SEG4 0339#define CLK_BASE__INST5_SEG5 0340341#define CLK_BASE__INST6_SEG0 0x000125E0342#define CLK_BASE__INST6_SEG1 0x00017E00343#define CLK_BASE__INST6_SEG2 0x0040BC00344#define CLK_BASE__INST6_SEG3 0345#define CLK_BASE__INST6_SEG4 0346#define CLK_BASE__INST6_SEG5 0347348#define CLK_BASE__INST7_SEG0 0349#define CLK_BASE__INST7_SEG1 0350#define CLK_BASE__INST7_SEG2 0351#define CLK_BASE__INST7_SEG3 0352#define CLK_BASE__INST7_SEG4 0353#define CLK_BASE__INST7_SEG5 0354355#define DF_BASE__INST0_SEG0 0x00007000356#define DF_BASE__INST0_SEG1 0x000125C0357#define DF_BASE__INST0_SEG2 0x0040B800358#define DF_BASE__INST0_SEG3 0359#define DF_BASE__INST0_SEG4 0360#define DF_BASE__INST0_SEG5 0361362#define DF_BASE__INST1_SEG0 0363#define DF_BASE__INST1_SEG1 0364#define DF_BASE__INST1_SEG2 0365#define DF_BASE__INST1_SEG3 0366#define DF_BASE__INST1_SEG4 0367#define DF_BASE__INST1_SEG5 0368369#define DF_BASE__INST2_SEG0 0370#define DF_BASE__INST2_SEG1 0371#define DF_BASE__INST2_SEG2 0372#define DF_BASE__INST2_SEG3 0373#define DF_BASE__INST2_SEG4 0374#define DF_BASE__INST2_SEG5 0375376#define DF_BASE__INST3_SEG0 0377#define DF_BASE__INST3_SEG1 0378#define DF_BASE__INST3_SEG2 0379#define DF_BASE__INST3_SEG3 0380#define DF_BASE__INST3_SEG4 0381#define DF_BASE__INST3_SEG5 0382383#define DF_BASE__INST4_SEG0 0384#define DF_BASE__INST4_SEG1 0385#define DF_BASE__INST4_SEG2 0386#define DF_BASE__INST4_SEG3 0387#define DF_BASE__INST4_SEG4 0388#define DF_BASE__INST4_SEG5 0389390#define DF_BASE__INST5_SEG0 0391#define DF_BASE__INST5_SEG1 0392#define DF_BASE__INST5_SEG2 0393#define DF_BASE__INST5_SEG3 0394#define DF_BASE__INST5_SEG4 0395#define DF_BASE__INST5_SEG5 0396397#define DF_BASE__INST6_SEG0 0398#define DF_BASE__INST6_SEG1 0399#define DF_BASE__INST6_SEG2 0400#define DF_BASE__INST6_SEG3 0401#define DF_BASE__INST6_SEG4 0402#define DF_BASE__INST6_SEG5 0403404#define DF_BASE__INST7_SEG0 0405#define DF_BASE__INST7_SEG1 0406#define DF_BASE__INST7_SEG2 0407#define DF_BASE__INST7_SEG3 0408#define DF_BASE__INST7_SEG4 0409#define DF_BASE__INST7_SEG5 0410411#define FUSE_BASE__INST0_SEG0 0x000120A0412#define FUSE_BASE__INST0_SEG1 0x00017400413#define FUSE_BASE__INST0_SEG2 0x00401400414#define FUSE_BASE__INST0_SEG3 0415#define FUSE_BASE__INST0_SEG4 0416#define FUSE_BASE__INST0_SEG5 0417418#define FUSE_BASE__INST1_SEG0 0419#define FUSE_BASE__INST1_SEG1 0420#define FUSE_BASE__INST1_SEG2 0421#define FUSE_BASE__INST1_SEG3 0422#define FUSE_BASE__INST1_SEG4 0423#define FUSE_BASE__INST1_SEG5 0424425#define FUSE_BASE__INST2_SEG0 0426#define FUSE_BASE__INST2_SEG1 0427#define FUSE_BASE__INST2_SEG2 0428#define FUSE_BASE__INST2_SEG3 0429#define FUSE_BASE__INST2_SEG4 0430#define FUSE_BASE__INST2_SEG5 0431432#define FUSE_BASE__INST3_SEG0 0433#define FUSE_BASE__INST3_SEG1 0434#define FUSE_BASE__INST3_SEG2 0435#define FUSE_BASE__INST3_SEG3 0436#define FUSE_BASE__INST3_SEG4 0437#define FUSE_BASE__INST3_SEG5 0438439#define FUSE_BASE__INST4_SEG0 0440#define FUSE_BASE__INST4_SEG1 0441#define FUSE_BASE__INST4_SEG2 0442#define FUSE_BASE__INST4_SEG3 0443#define FUSE_BASE__INST4_SEG4 0444#define FUSE_BASE__INST4_SEG5 0445446#define FUSE_BASE__INST5_SEG0 0447#define FUSE_BASE__INST5_SEG1 0448#define FUSE_BASE__INST5_SEG2 0449#define FUSE_BASE__INST5_SEG3 0450#define FUSE_BASE__INST5_SEG4 0451#define FUSE_BASE__INST5_SEG5 0452453#define FUSE_BASE__INST6_SEG0 0454#define FUSE_BASE__INST6_SEG1 0455#define FUSE_BASE__INST6_SEG2 0456#define FUSE_BASE__INST6_SEG3 0457#define FUSE_BASE__INST6_SEG4 0458#define FUSE_BASE__INST6_SEG5 0459460#define FUSE_BASE__INST7_SEG0 0461#define FUSE_BASE__INST7_SEG1 0462#define FUSE_BASE__INST7_SEG2 0463#define FUSE_BASE__INST7_SEG3 0464#define FUSE_BASE__INST7_SEG4 0465#define FUSE_BASE__INST7_SEG5 0466467#define GC_BASE__INST0_SEG0 0x00002000468#define GC_BASE__INST0_SEG1 0x0000A000469#define GC_BASE__INST0_SEG2 0x00012160470#define GC_BASE__INST0_SEG3 0x00402C00471#define GC_BASE__INST0_SEG4 0472#define GC_BASE__INST0_SEG5 0473474#define GC_BASE__INST1_SEG0 0475#define GC_BASE__INST1_SEG1 0476#define GC_BASE__INST1_SEG2 0477#define GC_BASE__INST1_SEG3 0478#define GC_BASE__INST1_SEG4 0479#define GC_BASE__INST1_SEG5 0480481#define GC_BASE__INST2_SEG0 0482#define GC_BASE__INST2_SEG1 0483#define GC_BASE__INST2_SEG2 0484#define GC_BASE__INST2_SEG3 0485#define GC_BASE__INST2_SEG4 0486#define GC_BASE__INST2_SEG5 0487488#define GC_BASE__INST3_SEG0 0489#define GC_BASE__INST3_SEG1 0490#define GC_BASE__INST3_SEG2 0491#define GC_BASE__INST3_SEG3 0492#define GC_BASE__INST3_SEG4 0493#define GC_BASE__INST3_SEG5 0494495#define GC_BASE__INST4_SEG0 0496#define GC_BASE__INST4_SEG1 0497#define GC_BASE__INST4_SEG2 0498#define GC_BASE__INST4_SEG3 0499#define GC_BASE__INST4_SEG4 0500#define GC_BASE__INST4_SEG5 0501502#define GC_BASE__INST5_SEG0 0503#define GC_BASE__INST5_SEG1 0504#define GC_BASE__INST5_SEG2 0505#define GC_BASE__INST5_SEG3 0506#define GC_BASE__INST5_SEG4 0507#define GC_BASE__INST5_SEG5 0508509#define GC_BASE__INST6_SEG0 0510#define GC_BASE__INST6_SEG1 0511#define GC_BASE__INST6_SEG2 0512#define GC_BASE__INST6_SEG3 0513#define GC_BASE__INST6_SEG4 0514#define GC_BASE__INST6_SEG5 0515516#define GC_BASE__INST7_SEG0 0517#define GC_BASE__INST7_SEG1 0518#define GC_BASE__INST7_SEG2 0519#define GC_BASE__INST7_SEG3 0520#define GC_BASE__INST7_SEG4 0521#define GC_BASE__INST7_SEG5 0522523#define HDP_BASE__INST0_SEG0 0x00000F20524#define HDP_BASE__INST0_SEG1 0x00012520525#define HDP_BASE__INST0_SEG2 0x0040A400526#define HDP_BASE__INST0_SEG3 0527#define HDP_BASE__INST0_SEG4 0528#define HDP_BASE__INST0_SEG5 0529530#define HDP_BASE__INST1_SEG0 0531#define HDP_BASE__INST1_SEG1 0532#define HDP_BASE__INST1_SEG2 0533#define HDP_BASE__INST1_SEG3 0534#define HDP_BASE__INST1_SEG4 0535#define HDP_BASE__INST1_SEG5 0536537#define HDP_BASE__INST2_SEG0 0538#define HDP_BASE__INST2_SEG1 0539#define HDP_BASE__INST2_SEG2 0540#define HDP_BASE__INST2_SEG3 0541#define HDP_BASE__INST2_SEG4 0542#define HDP_BASE__INST2_SEG5 0543544#define HDP_BASE__INST3_SEG0 0545#define HDP_BASE__INST3_SEG1 0546#define HDP_BASE__INST3_SEG2 0547#define HDP_BASE__INST3_SEG3 0548#define HDP_BASE__INST3_SEG4 0549#define HDP_BASE__INST3_SEG5 0550551#define HDP_BASE__INST4_SEG0 0552#define HDP_BASE__INST4_SEG1 0553#define HDP_BASE__INST4_SEG2 0554#define HDP_BASE__INST4_SEG3 0555#define HDP_BASE__INST4_SEG4 0556#define HDP_BASE__INST4_SEG5 0557558#define HDP_BASE__INST5_SEG0 0559#define HDP_BASE__INST5_SEG1 0560#define HDP_BASE__INST5_SEG2 0561#define HDP_BASE__INST5_SEG3 0562#define HDP_BASE__INST5_SEG4 0563#define HDP_BASE__INST5_SEG5 0564565#define HDP_BASE__INST6_SEG0 0566#define HDP_BASE__INST6_SEG1 0567#define HDP_BASE__INST6_SEG2 0568#define HDP_BASE__INST6_SEG3 0569#define HDP_BASE__INST6_SEG4 0570#define HDP_BASE__INST6_SEG5 0571572#define HDP_BASE__INST7_SEG0 0573#define HDP_BASE__INST7_SEG1 0574#define HDP_BASE__INST7_SEG2 0575#define HDP_BASE__INST7_SEG3 0576#define HDP_BASE__INST7_SEG4 0577#define HDP_BASE__INST7_SEG5 0578579#define MMHUB_BASE__INST0_SEG0 0x00012440580#define MMHUB_BASE__INST0_SEG1 0x0001A000581#define MMHUB_BASE__INST0_SEG2 0x00408800582#define MMHUB_BASE__INST0_SEG3 0583#define MMHUB_BASE__INST0_SEG4 0584#define MMHUB_BASE__INST0_SEG5 0585586#define MMHUB_BASE__INST1_SEG0 0587#define MMHUB_BASE__INST1_SEG1 0588#define MMHUB_BASE__INST1_SEG2 0589#define MMHUB_BASE__INST1_SEG3 0590#define MMHUB_BASE__INST1_SEG4 0591#define MMHUB_BASE__INST1_SEG5 0592593#define MMHUB_BASE__INST2_SEG0 0594#define MMHUB_BASE__INST2_SEG1 0595#define MMHUB_BASE__INST2_SEG2 0596#define MMHUB_BASE__INST2_SEG3 0597#define MMHUB_BASE__INST2_SEG4 0598#define MMHUB_BASE__INST2_SEG5 0599600#define MMHUB_BASE__INST3_SEG0 0601#define MMHUB_BASE__INST3_SEG1 0602#define MMHUB_BASE__INST3_SEG2 0603#define MMHUB_BASE__INST3_SEG3 0604#define MMHUB_BASE__INST3_SEG4 0605#define MMHUB_BASE__INST3_SEG5 0606607#define MMHUB_BASE__INST4_SEG0 0608#define MMHUB_BASE__INST4_SEG1 0609#define MMHUB_BASE__INST4_SEG2 0610#define MMHUB_BASE__INST4_SEG3 0611#define MMHUB_BASE__INST4_SEG4 0612#define MMHUB_BASE__INST4_SEG5 0613614#define MMHUB_BASE__INST5_SEG0 0615#define MMHUB_BASE__INST5_SEG1 0616#define MMHUB_BASE__INST5_SEG2 0617#define MMHUB_BASE__INST5_SEG3 0618#define MMHUB_BASE__INST5_SEG4 0619#define MMHUB_BASE__INST5_SEG5 0620621#define MMHUB_BASE__INST6_SEG0 0622#define MMHUB_BASE__INST6_SEG1 0623#define MMHUB_BASE__INST6_SEG2 0624#define MMHUB_BASE__INST6_SEG3 0625#define MMHUB_BASE__INST6_SEG4 0626#define MMHUB_BASE__INST6_SEG5 0627628#define MMHUB_BASE__INST7_SEG0 0629#define MMHUB_BASE__INST7_SEG1 0630#define MMHUB_BASE__INST7_SEG2 0631#define MMHUB_BASE__INST7_SEG3 0632#define MMHUB_BASE__INST7_SEG4 0633#define MMHUB_BASE__INST7_SEG5 0634635#define MP0_BASE__INST0_SEG0 0x00013FE0636#define MP0_BASE__INST0_SEG1 0x00016000637#define MP0_BASE__INST0_SEG2 0x0043FC00638#define MP0_BASE__INST0_SEG3 0x00DC0000639#define MP0_BASE__INST0_SEG4 0x00E00000640#define MP0_BASE__INST0_SEG5 0x00E40000641642#define MP0_BASE__INST1_SEG0 0643#define MP0_BASE__INST1_SEG1 0644#define MP0_BASE__INST1_SEG2 0645#define MP0_BASE__INST1_SEG3 0646#define MP0_BASE__INST1_SEG4 0647#define MP0_BASE__INST1_SEG5 0648649#define MP0_BASE__INST2_SEG0 0650#define MP0_BASE__INST2_SEG1 0651#define MP0_BASE__INST2_SEG2 0652#define MP0_BASE__INST2_SEG3 0653#define MP0_BASE__INST2_SEG4 0654#define MP0_BASE__INST2_SEG5 0655656#define MP0_BASE__INST3_SEG0 0657#define MP0_BASE__INST3_SEG1 0658#define MP0_BASE__INST3_SEG2 0659#define MP0_BASE__INST3_SEG3 0660#define MP0_BASE__INST3_SEG4 0661#define MP0_BASE__INST3_SEG5 0662663#define MP0_BASE__INST4_SEG0 0664#define MP0_BASE__INST4_SEG1 0665#define MP0_BASE__INST4_SEG2 0666#define MP0_BASE__INST4_SEG3 0667#define MP0_BASE__INST4_SEG4 0668#define MP0_BASE__INST4_SEG5 0669670#define MP0_BASE__INST5_SEG0 0671#define MP0_BASE__INST5_SEG1 0672#define MP0_BASE__INST5_SEG2 0673#define MP0_BASE__INST5_SEG3 0674#define MP0_BASE__INST5_SEG4 0675#define MP0_BASE__INST5_SEG5 0676677#define MP0_BASE__INST6_SEG0 0678#define MP0_BASE__INST6_SEG1 0679#define MP0_BASE__INST6_SEG2 0680#define MP0_BASE__INST6_SEG3 0681#define MP0_BASE__INST6_SEG4 0682#define MP0_BASE__INST6_SEG5 0683684#define MP0_BASE__INST7_SEG0 0685#define MP0_BASE__INST7_SEG1 0686#define MP0_BASE__INST7_SEG2 0687#define MP0_BASE__INST7_SEG3 0688#define MP0_BASE__INST7_SEG4 0689#define MP0_BASE__INST7_SEG5 0690691#define MP1_BASE__INST0_SEG0 0x00012020692#define MP1_BASE__INST0_SEG1 0x00016200693#define MP1_BASE__INST0_SEG2 0x00400400694#define MP1_BASE__INST0_SEG3 0x00E80000695#define MP1_BASE__INST0_SEG4 0x00EC0000696#define MP1_BASE__INST0_SEG5 0x00F00000697698#define MP1_BASE__INST1_SEG0 0699#define MP1_BASE__INST1_SEG1 0700#define MP1_BASE__INST1_SEG2 0701#define MP1_BASE__INST1_SEG3 0702#define MP1_BASE__INST1_SEG4 0703#define MP1_BASE__INST1_SEG5 0704705#define MP1_BASE__INST2_SEG0 0706#define MP1_BASE__INST2_SEG1 0707#define MP1_BASE__INST2_SEG2 0708#define MP1_BASE__INST2_SEG3 0709#define MP1_BASE__INST2_SEG4 0710#define MP1_BASE__INST2_SEG5 0711712#define MP1_BASE__INST3_SEG0 0713#define MP1_BASE__INST3_SEG1 0714#define MP1_BASE__INST3_SEG2 0715#define MP1_BASE__INST3_SEG3 0716#define MP1_BASE__INST3_SEG4 0717#define MP1_BASE__INST3_SEG5 0718719#define MP1_BASE__INST4_SEG0 0720#define MP1_BASE__INST4_SEG1 0721#define MP1_BASE__INST4_SEG2 0722#define MP1_BASE__INST4_SEG3 0723#define MP1_BASE__INST4_SEG4 0724#define MP1_BASE__INST4_SEG5 0725726#define MP1_BASE__INST5_SEG0 0727#define MP1_BASE__INST5_SEG1 0728#define MP1_BASE__INST5_SEG2 0729#define MP1_BASE__INST5_SEG3 0730#define MP1_BASE__INST5_SEG4 0731#define MP1_BASE__INST5_SEG5 0732733#define MP1_BASE__INST6_SEG0 0734#define MP1_BASE__INST6_SEG1 0735#define MP1_BASE__INST6_SEG2 0736#define MP1_BASE__INST6_SEG3 0737#define MP1_BASE__INST6_SEG4 0738#define MP1_BASE__INST6_SEG5 0739740#define MP1_BASE__INST7_SEG0 0741#define MP1_BASE__INST7_SEG1 0742#define MP1_BASE__INST7_SEG2 0743#define MP1_BASE__INST7_SEG3 0744#define MP1_BASE__INST7_SEG4 0745#define MP1_BASE__INST7_SEG5 0746747#define NBIF0_BASE__INST0_SEG0 0x00000000748#define NBIF0_BASE__INST0_SEG1 0x00000014749#define NBIF0_BASE__INST0_SEG2 0x00000D20750#define NBIF0_BASE__INST0_SEG3 0x00010400751#define NBIF0_BASE__INST0_SEG4 0x00012D80752#define NBIF0_BASE__INST0_SEG5 0x0041B000753754#define NBIF0_BASE__INST1_SEG0 0755#define NBIF0_BASE__INST1_SEG1 0756#define NBIF0_BASE__INST1_SEG2 0757#define NBIF0_BASE__INST1_SEG3 0758#define NBIF0_BASE__INST1_SEG4 0759#define NBIF0_BASE__INST1_SEG5 0760761#define NBIF0_BASE__INST2_SEG0 0762#define NBIF0_BASE__INST2_SEG1 0763#define NBIF0_BASE__INST2_SEG2 0764#define NBIF0_BASE__INST2_SEG3 0765#define NBIF0_BASE__INST2_SEG4 0766#define NBIF0_BASE__INST2_SEG5 0767768#define NBIF0_BASE__INST3_SEG0 0769#define NBIF0_BASE__INST3_SEG1 0770#define NBIF0_BASE__INST3_SEG2 0771#define NBIF0_BASE__INST3_SEG3 0772#define NBIF0_BASE__INST3_SEG4 0773#define NBIF0_BASE__INST3_SEG5 0774775#define NBIF0_BASE__INST4_SEG0 0776#define NBIF0_BASE__INST4_SEG1 0777#define NBIF0_BASE__INST4_SEG2 0778#define NBIF0_BASE__INST4_SEG3 0779#define NBIF0_BASE__INST4_SEG4 0780#define NBIF0_BASE__INST4_SEG5 0781782#define NBIF0_BASE__INST5_SEG0 0783#define NBIF0_BASE__INST5_SEG1 0784#define NBIF0_BASE__INST5_SEG2 0785#define NBIF0_BASE__INST5_SEG3 0786#define NBIF0_BASE__INST5_SEG4 0787#define NBIF0_BASE__INST5_SEG5 0788789#define NBIF0_BASE__INST6_SEG0 0790#define NBIF0_BASE__INST6_SEG1 0791#define NBIF0_BASE__INST6_SEG2 0792#define NBIF0_BASE__INST6_SEG3 0793#define NBIF0_BASE__INST6_SEG4 0794#define NBIF0_BASE__INST6_SEG5 0795796#define NBIF0_BASE__INST7_SEG0 0797#define NBIF0_BASE__INST7_SEG1 0798#define NBIF0_BASE__INST7_SEG2 0799#define NBIF0_BASE__INST7_SEG3 0800#define NBIF0_BASE__INST7_SEG4 0801#define NBIF0_BASE__INST7_SEG5 0802803#define OSSSYS_BASE__INST0_SEG0 0x000010A0804#define OSSSYS_BASE__INST0_SEG1 0x00012500805#define OSSSYS_BASE__INST0_SEG2 0x0040A000806#define OSSSYS_BASE__INST0_SEG3 0807#define OSSSYS_BASE__INST0_SEG4 0808#define OSSSYS_BASE__INST0_SEG5 0809810#define OSSSYS_BASE__INST1_SEG0 0811#define OSSSYS_BASE__INST1_SEG1 0812#define OSSSYS_BASE__INST1_SEG2 0813#define OSSSYS_BASE__INST1_SEG3 0814#define OSSSYS_BASE__INST1_SEG4 0815#define OSSSYS_BASE__INST1_SEG5 0816817#define OSSSYS_BASE__INST2_SEG0 0818#define OSSSYS_BASE__INST2_SEG1 0819#define OSSSYS_BASE__INST2_SEG2 0820#define OSSSYS_BASE__INST2_SEG3 0821#define OSSSYS_BASE__INST2_SEG4 0822#define OSSSYS_BASE__INST2_SEG5 0823824#define OSSSYS_BASE__INST3_SEG0 0825#define OSSSYS_BASE__INST3_SEG1 0826#define OSSSYS_BASE__INST3_SEG2 0827#define OSSSYS_BASE__INST3_SEG3 0828#define OSSSYS_BASE__INST3_SEG4 0829#define OSSSYS_BASE__INST3_SEG5 0830831#define OSSSYS_BASE__INST4_SEG0 0832#define OSSSYS_BASE__INST4_SEG1 0833#define OSSSYS_BASE__INST4_SEG2 0834#define OSSSYS_BASE__INST4_SEG3 0835#define OSSSYS_BASE__INST4_SEG4 0836#define OSSSYS_BASE__INST4_SEG5 0837838#define OSSSYS_BASE__INST5_SEG0 0839#define OSSSYS_BASE__INST5_SEG1 0840#define OSSSYS_BASE__INST5_SEG2 0841#define OSSSYS_BASE__INST5_SEG3 0842#define OSSSYS_BASE__INST5_SEG4 0843#define OSSSYS_BASE__INST5_SEG5 0844845#define OSSSYS_BASE__INST6_SEG0 0846#define OSSSYS_BASE__INST6_SEG1 0847#define OSSSYS_BASE__INST6_SEG2 0848#define OSSSYS_BASE__INST6_SEG3 0849#define OSSSYS_BASE__INST6_SEG4 0850#define OSSSYS_BASE__INST6_SEG5 0851852#define OSSSYS_BASE__INST7_SEG0 0853#define OSSSYS_BASE__INST7_SEG1 0854#define OSSSYS_BASE__INST7_SEG2 0855#define OSSSYS_BASE__INST7_SEG3 0856#define OSSSYS_BASE__INST7_SEG4 0857#define OSSSYS_BASE__INST7_SEG5 0858859#define PCIE0_BASE__INST0_SEG0 0x000128C0860#define PCIE0_BASE__INST0_SEG1 0x00411800861#define PCIE0_BASE__INST0_SEG2 0x04440000862#define PCIE0_BASE__INST0_SEG3 0863#define PCIE0_BASE__INST0_SEG4 0864#define PCIE0_BASE__INST0_SEG5 0865866#define PCIE0_BASE__INST1_SEG0 0867#define PCIE0_BASE__INST1_SEG1 0868#define PCIE0_BASE__INST1_SEG2 0869#define PCIE0_BASE__INST1_SEG3 0870#define PCIE0_BASE__INST1_SEG4 0871#define PCIE0_BASE__INST1_SEG5 0872873#define PCIE0_BASE__INST2_SEG0 0874#define PCIE0_BASE__INST2_SEG1 0875#define PCIE0_BASE__INST2_SEG2 0876#define PCIE0_BASE__INST2_SEG3 0877#define PCIE0_BASE__INST2_SEG4 0878#define PCIE0_BASE__INST2_SEG5 0879880#define PCIE0_BASE__INST3_SEG0 0881#define PCIE0_BASE__INST3_SEG1 0882#define PCIE0_BASE__INST3_SEG2 0883#define PCIE0_BASE__INST3_SEG3 0884#define PCIE0_BASE__INST3_SEG4 0885#define PCIE0_BASE__INST3_SEG5 0886887#define PCIE0_BASE__INST4_SEG0 0888#define PCIE0_BASE__INST4_SEG1 0889#define PCIE0_BASE__INST4_SEG2 0890#define PCIE0_BASE__INST4_SEG3 0891#define PCIE0_BASE__INST4_SEG4 0892#define PCIE0_BASE__INST4_SEG5 0893894#define PCIE0_BASE__INST5_SEG0 0895#define PCIE0_BASE__INST5_SEG1 0896#define PCIE0_BASE__INST5_SEG2 0897#define PCIE0_BASE__INST5_SEG3 0898#define PCIE0_BASE__INST5_SEG4 0899#define PCIE0_BASE__INST5_SEG5 0900901#define PCIE0_BASE__INST6_SEG0 0902#define PCIE0_BASE__INST6_SEG1 0903#define PCIE0_BASE__INST6_SEG2 0904#define PCIE0_BASE__INST6_SEG3 0905#define PCIE0_BASE__INST6_SEG4 0906#define PCIE0_BASE__INST6_SEG5 0907908#define PCIE0_BASE__INST7_SEG0 0909#define PCIE0_BASE__INST7_SEG1 0910#define PCIE0_BASE__INST7_SEG2 0911#define PCIE0_BASE__INST7_SEG3 0912#define PCIE0_BASE__INST7_SEG4 0913#define PCIE0_BASE__INST7_SEG5 0914915#define SDMA0_BASE__INST0_SEG0 0x00001260916#define SDMA0_BASE__INST0_SEG1 0x00012540917#define SDMA0_BASE__INST0_SEG2 0x0040A800918#define SDMA0_BASE__INST0_SEG3 0919#define SDMA0_BASE__INST0_SEG4 0920#define SDMA0_BASE__INST0_SEG5 0921922#define SDMA0_BASE__INST1_SEG0 0923#define SDMA0_BASE__INST1_SEG1 0924#define SDMA0_BASE__INST1_SEG2 0925#define SDMA0_BASE__INST1_SEG3 0926#define SDMA0_BASE__INST1_SEG4 0927#define SDMA0_BASE__INST1_SEG5 0928929#define SDMA0_BASE__INST2_SEG0 0930#define SDMA0_BASE__INST2_SEG1 0931#define SDMA0_BASE__INST2_SEG2 0932#define SDMA0_BASE__INST2_SEG3 0933#define SDMA0_BASE__INST2_SEG4 0934#define SDMA0_BASE__INST2_SEG5 0935936#define SDMA0_BASE__INST3_SEG0 0937#define SDMA0_BASE__INST3_SEG1 0938#define SDMA0_BASE__INST3_SEG2 0939#define SDMA0_BASE__INST3_SEG3 0940#define SDMA0_BASE__INST3_SEG4 0941#define SDMA0_BASE__INST3_SEG5 0942943#define SDMA0_BASE__INST4_SEG0 0944#define SDMA0_BASE__INST4_SEG1 0945#define SDMA0_BASE__INST4_SEG2 0946#define SDMA0_BASE__INST4_SEG3 0947#define SDMA0_BASE__INST4_SEG4 0948#define SDMA0_BASE__INST4_SEG5 0949950#define SDMA0_BASE__INST5_SEG0 0951#define SDMA0_BASE__INST5_SEG1 0952#define SDMA0_BASE__INST5_SEG2 0953#define SDMA0_BASE__INST5_SEG3 0954#define SDMA0_BASE__INST5_SEG4 0955#define SDMA0_BASE__INST5_SEG5 0956957#define SDMA0_BASE__INST6_SEG0 0958#define SDMA0_BASE__INST6_SEG1 0959#define SDMA0_BASE__INST6_SEG2 0960#define SDMA0_BASE__INST6_SEG3 0961#define SDMA0_BASE__INST6_SEG4 0962#define SDMA0_BASE__INST6_SEG5 0963964#define SDMA1_BASE__INST0_SEG0 0x00001860965#define SDMA1_BASE__INST0_SEG1 0x00012560966#define SDMA1_BASE__INST0_SEG2 0x0040AC00967#define SDMA1_BASE__INST0_SEG3 0968#define SDMA1_BASE__INST0_SEG4 0969#define SDMA1_BASE__INST0_SEG5 0970971#define SDMA1_BASE__INST1_SEG0 0972#define SDMA1_BASE__INST1_SEG1 0973#define SDMA1_BASE__INST1_SEG2 0974#define SDMA1_BASE__INST1_SEG3 0975#define SDMA1_BASE__INST1_SEG4 0976#define SDMA1_BASE__INST1_SEG5 0977978#define SDMA1_BASE__INST2_SEG0 0979#define SDMA1_BASE__INST2_SEG1 0980#define SDMA1_BASE__INST2_SEG2 0981#define SDMA1_BASE__INST2_SEG3 0982#define SDMA1_BASE__INST2_SEG4 0983#define SDMA1_BASE__INST2_SEG5 0984985#define SDMA1_BASE__INST3_SEG0 0986#define SDMA1_BASE__INST3_SEG1 0987#define SDMA1_BASE__INST3_SEG2 0988#define SDMA1_BASE__INST3_SEG3 0989#define SDMA1_BASE__INST3_SEG4 0990#define SDMA1_BASE__INST3_SEG5 0991992#define SDMA1_BASE__INST4_SEG0 0993#define SDMA1_BASE__INST4_SEG1 0994#define SDMA1_BASE__INST4_SEG2 0995#define SDMA1_BASE__INST4_SEG3 0996#define SDMA1_BASE__INST4_SEG4 0997#define SDMA1_BASE__INST4_SEG5 0998999#define SDMA1_BASE__INST5_SEG0 01000#define SDMA1_BASE__INST5_SEG1 01001#define SDMA1_BASE__INST5_SEG2 01002#define SDMA1_BASE__INST5_SEG3 01003#define SDMA1_BASE__INST5_SEG4 01004#define SDMA1_BASE__INST5_SEG5 0100510061007#define SDMA1_BASE__INST6_SEG0 01008#define SDMA1_BASE__INST6_SEG1 01009#define SDMA1_BASE__INST6_SEG2 01010#define SDMA1_BASE__INST6_SEG3 01011#define SDMA1_BASE__INST6_SEG4 01012#define SDMA1_BASE__INST6_SEG5 0101310141015#define SDMA2_BASE__INST0_SEG0 0x000137601016#define SDMA2_BASE__INST0_SEG1 0x0001E0001017#define SDMA2_BASE__INST0_SEG2 0x0042EC001018#define SDMA2_BASE__INST0_SEG3 01019#define SDMA2_BASE__INST0_SEG4 01020#define SDMA2_BASE__INST0_SEG5 0102110221023#define SDMA2_BASE__INST1_SEG0 01024#define SDMA2_BASE__INST1_SEG1 01025#define SDMA2_BASE__INST1_SEG2 01026#define SDMA2_BASE__INST1_SEG3 01027#define SDMA2_BASE__INST1_SEG4 01028#define SDMA2_BASE__INST1_SEG5 010291030#define SDMA2_BASE__INST2_SEG0 01031#define SDMA2_BASE__INST2_SEG1 01032#define SDMA2_BASE__INST2_SEG2 01033#define SDMA2_BASE__INST2_SEG3 01034#define SDMA2_BASE__INST2_SEG4 01035#define SDMA2_BASE__INST2_SEG5 010361037#define SDMA2_BASE__INST3_SEG0 01038#define SDMA2_BASE__INST3_SEG1 01039#define SDMA2_BASE__INST3_SEG2 01040#define SDMA2_BASE__INST3_SEG3 01041#define SDMA2_BASE__INST3_SEG4 01042#define SDMA2_BASE__INST3_SEG5 010431044#define SDMA2_BASE__INST4_SEG0 01045#define SDMA2_BASE__INST4_SEG1 01046#define SDMA2_BASE__INST4_SEG2 01047#define SDMA2_BASE__INST4_SEG3 01048#define SDMA2_BASE__INST4_SEG4 01049#define SDMA2_BASE__INST4_SEG5 010501051#define SDMA2_BASE__INST5_SEG0 01052#define SDMA2_BASE__INST5_SEG1 01053#define SDMA2_BASE__INST5_SEG2 01054#define SDMA2_BASE__INST5_SEG3 01055#define SDMA2_BASE__INST5_SEG4 01056#define SDMA2_BASE__INST5_SEG5 010571058#define SDMA2_BASE__INST6_SEG0 01059#define SDMA2_BASE__INST6_SEG1 01060#define SDMA2_BASE__INST6_SEG2 01061#define SDMA2_BASE__INST6_SEG3 01062#define SDMA2_BASE__INST6_SEG4 01063#define SDMA2_BASE__INST6_SEG5 010641065#define SDMA3_BASE__INST0_SEG0 0x000137801066#define SDMA3_BASE__INST0_SEG1 0x0001E4001067#define SDMA3_BASE__INST0_SEG2 0x0042F0001068#define SDMA3_BASE__INST0_SEG3 01069#define SDMA3_BASE__INST0_SEG4 01070#define SDMA3_BASE__INST0_SEG5 010711072#define SDMA3_BASE__INST1_SEG0 01073#define SDMA3_BASE__INST1_SEG1 01074#define SDMA3_BASE__INST1_SEG2 01075#define SDMA3_BASE__INST1_SEG3 01076#define SDMA3_BASE__INST1_SEG4 01077#define SDMA3_BASE__INST1_SEG5 010781079#define SDMA3_BASE__INST2_SEG0 01080#define SDMA3_BASE__INST2_SEG1 01081#define SDMA3_BASE__INST2_SEG2 01082#define SDMA3_BASE__INST2_SEG3 01083#define SDMA3_BASE__INST2_SEG4 01084#define SDMA3_BASE__INST2_SEG5 010851086#define SDMA3_BASE__INST3_SEG0 01087#define SDMA3_BASE__INST3_SEG1 01088#define SDMA3_BASE__INST3_SEG2 01089#define SDMA3_BASE__INST3_SEG3 01090#define SDMA3_BASE__INST3_SEG4 01091#define SDMA3_BASE__INST3_SEG5 010921093#define SDMA3_BASE__INST4_SEG0 01094#define SDMA3_BASE__INST4_SEG1 01095#define SDMA3_BASE__INST4_SEG2 01096#define SDMA3_BASE__INST4_SEG3 01097#define SDMA3_BASE__INST4_SEG4 01098#define SDMA3_BASE__INST4_SEG5 010991100#define SDMA3_BASE__INST5_SEG0 01101#define SDMA3_BASE__INST5_SEG1 01102#define SDMA3_BASE__INST5_SEG2 01103#define SDMA3_BASE__INST5_SEG3 01104#define SDMA3_BASE__INST5_SEG4 01105#define SDMA3_BASE__INST5_SEG5 011061107#define SDMA3_BASE__INST6_SEG0 01108#define SDMA3_BASE__INST6_SEG1 01109#define SDMA3_BASE__INST6_SEG2 01110#define SDMA3_BASE__INST6_SEG3 01111#define SDMA3_BASE__INST6_SEG4 01112#define SDMA3_BASE__INST6_SEG5 011131114#define SDMA4_BASE__INST0_SEG0 0x000137A01115#define SDMA4_BASE__INST0_SEG1 0x0001E8001116#define SDMA4_BASE__INST0_SEG2 0x0042F4001117#define SDMA4_BASE__INST0_SEG3 01118#define SDMA4_BASE__INST0_SEG4 01119#define SDMA4_BASE__INST0_SEG5 011201121#define SDMA4_BASE__INST1_SEG0 01122#define SDMA4_BASE__INST1_SEG1 01123#define SDMA4_BASE__INST1_SEG2 01124#define SDMA4_BASE__INST1_SEG3 01125#define SDMA4_BASE__INST1_SEG4 01126#define SDMA4_BASE__INST1_SEG5 011271128#define SDMA4_BASE__INST2_SEG0 01129#define SDMA4_BASE__INST2_SEG1 01130#define SDMA4_BASE__INST2_SEG2 01131#define SDMA4_BASE__INST2_SEG3 01132#define SDMA4_BASE__INST2_SEG4 01133#define SDMA4_BASE__INST2_SEG5 011341135#define SDMA4_BASE__INST3_SEG0 01136#define SDMA4_BASE__INST3_SEG1 01137#define SDMA4_BASE__INST3_SEG2 01138#define SDMA4_BASE__INST3_SEG3 01139#define SDMA4_BASE__INST3_SEG4 01140#define SDMA4_BASE__INST3_SEG5 011411142#define SDMA4_BASE__INST4_SEG0 01143#define SDMA4_BASE__INST4_SEG1 01144#define SDMA4_BASE__INST4_SEG2 01145#define SDMA4_BASE__INST4_SEG3 01146#define SDMA4_BASE__INST4_SEG4 01147#define SDMA4_BASE__INST4_SEG5 011481149#define SDMA4_BASE__INST5_SEG0 01150#define SDMA4_BASE__INST5_SEG1 01151#define SDMA4_BASE__INST5_SEG2 01152#define SDMA4_BASE__INST5_SEG3 01153#define SDMA4_BASE__INST5_SEG4 01154#define SDMA4_BASE__INST5_SEG5 011551156#define SDMA4_BASE__INST6_SEG0 01157#define SDMA4_BASE__INST6_SEG1 01158#define SDMA4_BASE__INST6_SEG2 01159#define SDMA4_BASE__INST6_SEG3 01160#define SDMA4_BASE__INST6_SEG4 01161#define SDMA4_BASE__INST6_SEG5 011621163#define SDMA5_BASE__INST0_SEG0 0x000137C01164#define SDMA5_BASE__INST0_SEG1 0x0001EC001165#define SDMA5_BASE__INST0_SEG2 0x0042F8001166#define SDMA5_BASE__INST0_SEG3 01167#define SDMA5_BASE__INST0_SEG4 01168#define SDMA5_BASE__INST0_SEG5 011691170#define SDMA5_BASE__INST1_SEG0 01171#define SDMA5_BASE__INST1_SEG1 01172#define SDMA5_BASE__INST1_SEG2 01173#define SDMA5_BASE__INST1_SEG3 01174#define SDMA5_BASE__INST1_SEG4 01175#define SDMA5_BASE__INST1_SEG5 011761177#define SDMA5_BASE__INST2_SEG0 01178#define SDMA5_BASE__INST2_SEG1 01179#define SDMA5_BASE__INST2_SEG2 01180#define SDMA5_BASE__INST2_SEG3 01181#define SDMA5_BASE__INST2_SEG4 01182#define SDMA5_BASE__INST2_SEG5 011831184#define SDMA5_BASE__INST3_SEG0 01185#define SDMA5_BASE__INST3_SEG1 01186#define SDMA5_BASE__INST3_SEG2 01187#define SDMA5_BASE__INST3_SEG3 01188#define SDMA5_BASE__INST3_SEG4 01189#define SDMA5_BASE__INST3_SEG5 011901191#define SDMA5_BASE__INST4_SEG0 01192#define SDMA5_BASE__INST4_SEG1 01193#define SDMA5_BASE__INST4_SEG2 01194#define SDMA5_BASE__INST4_SEG3 01195#define SDMA5_BASE__INST4_SEG4 01196#define SDMA5_BASE__INST4_SEG5 011971198#define SDMA5_BASE__INST5_SEG0 01199#define SDMA5_BASE__INST5_SEG1 01200#define SDMA5_BASE__INST5_SEG2 01201#define SDMA5_BASE__INST5_SEG3 01202#define SDMA5_BASE__INST5_SEG4 01203#define SDMA5_BASE__INST5_SEG5 012041205#define SDMA5_BASE__INST6_SEG0 01206#define SDMA5_BASE__INST6_SEG1 01207#define SDMA5_BASE__INST6_SEG2 01208#define SDMA5_BASE__INST6_SEG3 01209#define SDMA5_BASE__INST6_SEG4 01210#define SDMA5_BASE__INST6_SEG5 012111212#define SDMA6_BASE__INST0_SEG0 0x000137E01213#define SDMA6_BASE__INST0_SEG1 0x0001F0001214#define SDMA6_BASE__INST0_SEG2 0x0042FC001215#define SDMA6_BASE__INST0_SEG3 01216#define SDMA6_BASE__INST0_SEG4 01217#define SDMA6_BASE__INST0_SEG5 012181219#define SDMA6_BASE__INST1_SEG0 01220#define SDMA6_BASE__INST1_SEG1 01221#define SDMA6_BASE__INST1_SEG2 01222#define SDMA6_BASE__INST1_SEG3 01223#define SDMA6_BASE__INST1_SEG4 01224#define SDMA6_BASE__INST1_SEG5 012251226#define SDMA6_BASE__INST2_SEG0 01227#define SDMA6_BASE__INST2_SEG1 01228#define SDMA6_BASE__INST2_SEG2 01229#define SDMA6_BASE__INST2_SEG3 01230#define SDMA6_BASE__INST2_SEG4 01231#define SDMA6_BASE__INST2_SEG5 012321233#define SDMA6_BASE__INST3_SEG0 01234#define SDMA6_BASE__INST3_SEG1 01235#define SDMA6_BASE__INST3_SEG2 01236#define SDMA6_BASE__INST3_SEG3 01237#define SDMA6_BASE__INST3_SEG4 01238#define SDMA6_BASE__INST3_SEG5 012391240#define SDMA6_BASE__INST4_SEG0 01241#define SDMA6_BASE__INST4_SEG1 01242#define SDMA6_BASE__INST4_SEG2 01243#define SDMA6_BASE__INST4_SEG3 01244#define SDMA6_BASE__INST4_SEG4 01245#define SDMA6_BASE__INST4_SEG5 012461247#define SDMA6_BASE__INST5_SEG0 01248#define SDMA6_BASE__INST5_SEG1 01249#define SDMA6_BASE__INST5_SEG2 01250#define SDMA6_BASE__INST5_SEG3 01251#define SDMA6_BASE__INST5_SEG4 01252#define SDMA6_BASE__INST5_SEG5 012531254#define SDMA6_BASE__INST6_SEG0 01255#define SDMA6_BASE__INST6_SEG1 01256#define SDMA6_BASE__INST6_SEG2 01257#define SDMA6_BASE__INST6_SEG3 01258#define SDMA6_BASE__INST6_SEG4 01259#define SDMA6_BASE__INST6_SEG5 012601261#define SDMA7_BASE__INST0_SEG0 0x000138001262#define SDMA7_BASE__INST0_SEG1 0x0001F4001263#define SDMA7_BASE__INST0_SEG2 0x004300001264#define SDMA7_BASE__INST0_SEG3 01265#define SDMA7_BASE__INST0_SEG4 01266#define SDMA7_BASE__INST0_SEG5 012671268#define SDMA7_BASE__INST1_SEG0 01269#define SDMA7_BASE__INST1_SEG1 01270#define SDMA7_BASE__INST1_SEG2 01271#define SDMA7_BASE__INST1_SEG3 01272#define SDMA7_BASE__INST1_SEG4 01273#define SDMA7_BASE__INST1_SEG5 012741275#define SDMA7_BASE__INST2_SEG0 01276#define SDMA7_BASE__INST2_SEG1 01277#define SDMA7_BASE__INST2_SEG2 01278#define SDMA7_BASE__INST2_SEG3 01279#define SDMA7_BASE__INST2_SEG4 01280#define SDMA7_BASE__INST2_SEG5 012811282#define SDMA7_BASE__INST3_SEG0 01283#define SDMA7_BASE__INST3_SEG1 01284#define SDMA7_BASE__INST3_SEG2 01285#define SDMA7_BASE__INST3_SEG3 01286#define SDMA7_BASE__INST3_SEG4 01287#define SDMA7_BASE__INST3_SEG5 012881289#define SDMA7_BASE__INST4_SEG0 01290#define SDMA7_BASE__INST4_SEG1 01291#define SDMA7_BASE__INST4_SEG2 01292#define SDMA7_BASE__INST4_SEG3 01293#define SDMA7_BASE__INST4_SEG4 01294#define SDMA7_BASE__INST4_SEG5 012951296#define SDMA7_BASE__INST5_SEG0 01297#define SDMA7_BASE__INST5_SEG1 01298#define SDMA7_BASE__INST5_SEG2 01299#define SDMA7_BASE__INST5_SEG3 01300#define SDMA7_BASE__INST5_SEG4 01301#define SDMA7_BASE__INST5_SEG5 013021303#define SDMA7_BASE__INST6_SEG0 01304#define SDMA7_BASE__INST6_SEG1 01305#define SDMA7_BASE__INST6_SEG2 01306#define SDMA7_BASE__INST6_SEG3 01307#define SDMA7_BASE__INST6_SEG4 01308#define SDMA7_BASE__INST6_SEG5 013091310#define SMUIO_BASE__INST0_SEG0 0x000120801311#define SMUIO_BASE__INST0_SEG1 0x000168001312#define SMUIO_BASE__INST0_SEG2 0x00016A001313#define SMUIO_BASE__INST0_SEG3 0x004010001314#define SMUIO_BASE__INST0_SEG4 0x004400001315#define SMUIO_BASE__INST0_SEG5 013161317#define SMUIO_BASE__INST1_SEG0 01318#define SMUIO_BASE__INST1_SEG1 01319#define SMUIO_BASE__INST1_SEG2 01320#define SMUIO_BASE__INST1_SEG3 01321#define SMUIO_BASE__INST1_SEG4 01322#define SMUIO_BASE__INST1_SEG5 013231324#define SMUIO_BASE__INST2_SEG0 01325#define SMUIO_BASE__INST2_SEG1 01326#define SMUIO_BASE__INST2_SEG2 01327#define SMUIO_BASE__INST2_SEG3 01328#define SMUIO_BASE__INST2_SEG4 01329#define SMUIO_BASE__INST2_SEG5 013301331#define SMUIO_BASE__INST3_SEG0 01332#define SMUIO_BASE__INST3_SEG1 01333#define SMUIO_BASE__INST3_SEG2 01334#define SMUIO_BASE__INST3_SEG3 01335#define SMUIO_BASE__INST3_SEG4 01336#define SMUIO_BASE__INST3_SEG5 013371338#define SMUIO_BASE__INST4_SEG0 01339#define SMUIO_BASE__INST4_SEG1 01340#define SMUIO_BASE__INST4_SEG2 01341#define SMUIO_BASE__INST4_SEG3 01342#define SMUIO_BASE__INST4_SEG4 01343#define SMUIO_BASE__INST4_SEG5 013441345#define SMUIO_BASE__INST5_SEG0 01346#define SMUIO_BASE__INST5_SEG1 01347#define SMUIO_BASE__INST5_SEG2 01348#define SMUIO_BASE__INST5_SEG3 01349#define SMUIO_BASE__INST5_SEG4 01350#define SMUIO_BASE__INST5_SEG5 013511352#define SMUIO_BASE__INST6_SEG0 01353#define SMUIO_BASE__INST6_SEG1 01354#define SMUIO_BASE__INST6_SEG2 01355#define SMUIO_BASE__INST6_SEG3 01356#define SMUIO_BASE__INST6_SEG4 01357#define SMUIO_BASE__INST6_SEG5 013581359#define SMUIO_BASE__INST7_SEG0 01360#define SMUIO_BASE__INST7_SEG1 01361#define SMUIO_BASE__INST7_SEG2 01362#define SMUIO_BASE__INST7_SEG3 01363#define SMUIO_BASE__INST7_SEG4 01364#define SMUIO_BASE__INST7_SEG5 013651366#define THM_BASE__INST0_SEG0 0x000120601367#define THM_BASE__INST0_SEG1 0x000166001368#define THM_BASE__INST0_SEG2 0x00400C001369#define THM_BASE__INST0_SEG3 01370#define THM_BASE__INST0_SEG4 01371#define THM_BASE__INST0_SEG5 013721373#define THM_BASE__INST1_SEG0 01374#define THM_BASE__INST1_SEG1 01375#define THM_BASE__INST1_SEG2 01376#define THM_BASE__INST1_SEG3 01377#define THM_BASE__INST1_SEG4 01378#define THM_BASE__INST1_SEG5 013791380#define THM_BASE__INST2_SEG0 01381#define THM_BASE__INST2_SEG1 01382#define THM_BASE__INST2_SEG2 01383#define THM_BASE__INST2_SEG3 01384#define THM_BASE__INST2_SEG4 01385#define THM_BASE__INST2_SEG5 013861387#define THM_BASE__INST3_SEG0 01388#define THM_BASE__INST3_SEG1 01389#define THM_BASE__INST3_SEG2 01390#define THM_BASE__INST3_SEG3 01391#define THM_BASE__INST3_SEG4 01392#define THM_BASE__INST3_SEG5 013931394#define THM_BASE__INST4_SEG0 01395#define THM_BASE__INST4_SEG1 01396#define THM_BASE__INST4_SEG2 01397#define THM_BASE__INST4_SEG3 01398#define THM_BASE__INST4_SEG4 01399#define THM_BASE__INST4_SEG5 014001401#define THM_BASE__INST5_SEG0 01402#define THM_BASE__INST5_SEG1 01403#define THM_BASE__INST5_SEG2 01404#define THM_BASE__INST5_SEG3 01405#define THM_BASE__INST5_SEG4 01406#define THM_BASE__INST5_SEG5 014071408#define THM_BASE__INST6_SEG0 01409#define THM_BASE__INST6_SEG1 01410#define THM_BASE__INST6_SEG2 01411#define THM_BASE__INST6_SEG3 01412#define THM_BASE__INST6_SEG4 01413#define THM_BASE__INST6_SEG5 014141415#define THM_BASE__INST7_SEG0 01416#define THM_BASE__INST7_SEG1 01417#define THM_BASE__INST7_SEG2 01418#define THM_BASE__INST7_SEG3 01419#define THM_BASE__INST7_SEG4 01420#define THM_BASE__INST7_SEG5 014211422#define UMC_BASE__INST0_SEG0 0x000132C01423#define UMC_BASE__INST0_SEG1 0x000140001424#define UMC_BASE__INST0_SEG2 0x004258001425#define UMC_BASE__INST0_SEG3 01426#define UMC_BASE__INST0_SEG4 01427#define UMC_BASE__INST0_SEG5 014281429#define UMC_BASE__INST1_SEG0 0x000132E01430#define UMC_BASE__INST1_SEG1 0x000540001431#define UMC_BASE__INST1_SEG2 0x00425C001432#define UMC_BASE__INST1_SEG3 01433#define UMC_BASE__INST1_SEG4 01434#define UMC_BASE__INST1_SEG5 014351436#define UMC_BASE__INST2_SEG0 0x000133001437#define UMC_BASE__INST2_SEG1 0x000940001438#define UMC_BASE__INST2_SEG2 0x004260001439#define UMC_BASE__INST2_SEG3 01440#define UMC_BASE__INST2_SEG4 01441#define UMC_BASE__INST2_SEG5 014421443#define UMC_BASE__INST3_SEG0 0x000133201444#define UMC_BASE__INST3_SEG1 0x000D40001445#define UMC_BASE__INST3_SEG2 0x004264001446#define UMC_BASE__INST3_SEG3 01447#define UMC_BASE__INST3_SEG4 01448#define UMC_BASE__INST3_SEG5 014491450#define UMC_BASE__INST4_SEG0 0x000133401451#define UMC_BASE__INST4_SEG1 0x001140001452#define UMC_BASE__INST4_SEG2 0x004268001453#define UMC_BASE__INST4_SEG3 01454#define UMC_BASE__INST4_SEG4 01455#define UMC_BASE__INST4_SEG5 014561457#define UMC_BASE__INST5_SEG0 0x000133601458#define UMC_BASE__INST5_SEG1 0x001540001459#define UMC_BASE__INST5_SEG2 0x00426C001460#define UMC_BASE__INST5_SEG3 01461#define UMC_BASE__INST5_SEG4 01462#define UMC_BASE__INST5_SEG5 014631464#define UMC_BASE__INST6_SEG0 0x000133801465#define UMC_BASE__INST6_SEG1 0x001940001466#define UMC_BASE__INST6_SEG2 0x004270001467#define UMC_BASE__INST6_SEG3 01468#define UMC_BASE__INST6_SEG4 01469#define UMC_BASE__INST6_SEG5 014701471#define UMC_BASE__INST7_SEG0 0x000133A01472#define UMC_BASE__INST7_SEG1 0x001D40001473#define UMC_BASE__INST7_SEG2 0x004274001474#define UMC_BASE__INST7_SEG3 01475#define UMC_BASE__INST7_SEG4 01476#define UMC_BASE__INST7_SEG5 014771478#define UVD_BASE__INST0_SEG0 0x000078001479#define UVD_BASE__INST0_SEG1 0x00007E001480#define UVD_BASE__INST0_SEG2 0x000121801481#define UVD_BASE__INST0_SEG3 0x004030001482#define UVD_BASE__INST0_SEG4 01483#define UVD_BASE__INST0_SEG5 014841485#define UVD_BASE__INST1_SEG0 0x00007A001486#define UVD_BASE__INST1_SEG1 0x000090001487#define UVD_BASE__INST1_SEG2 0x000136E01488#define UVD_BASE__INST1_SEG3 0x0042DC001489#define UVD_BASE__INST1_SEG4 01490#define UVD_BASE__INST1_SEG5 014911492#define UVD_BASE__INST2_SEG0 01493#define UVD_BASE__INST2_SEG1 01494#define UVD_BASE__INST2_SEG2 01495#define UVD_BASE__INST2_SEG3 01496#define UVD_BASE__INST2_SEG4 01497#define UVD_BASE__INST2_SEG5 014981499#define UVD_BASE__INST3_SEG0 01500#define UVD_BASE__INST3_SEG1 01501#define UVD_BASE__INST3_SEG2 01502#define UVD_BASE__INST3_SEG3 01503#define UVD_BASE__INST3_SEG4 01504#define UVD_BASE__INST3_SEG5 015051506#define UVD_BASE__INST4_SEG0 01507#define UVD_BASE__INST4_SEG1 01508#define UVD_BASE__INST4_SEG2 01509#define UVD_BASE__INST4_SEG3 01510#define UVD_BASE__INST4_SEG4 01511#define UVD_BASE__INST4_SEG5 015121513#define UVD_BASE__INST5_SEG0 01514#define UVD_BASE__INST5_SEG1 01515#define UVD_BASE__INST5_SEG2 01516#define UVD_BASE__INST5_SEG3 01517#define UVD_BASE__INST5_SEG4 01518#define UVD_BASE__INST5_SEG5 015191520#define UVD_BASE__INST6_SEG0 01521#define UVD_BASE__INST6_SEG1 01522#define UVD_BASE__INST6_SEG2 01523#define UVD_BASE__INST6_SEG3 01524#define UVD_BASE__INST6_SEG4 01525#define UVD_BASE__INST6_SEG5 015261527#define UVD_BASE__INST7_SEG0 01528#define UVD_BASE__INST7_SEG1 01529#define UVD_BASE__INST7_SEG2 01530#define UVD_BASE__INST7_SEG3 01531#define UVD_BASE__INST7_SEG4 01532#define UVD_BASE__INST7_SEG5 015331534#define DBGU_IO_BASE__INST0_SEG0 0x000001E01535#define DBGU_IO_BASE__INST0_SEG1 0x000125A01536#define DBGU_IO_BASE__INST0_SEG2 0x0040B4001537#define DBGU_IO_BASE__INST0_SEG3 01538#define DBGU_IO_BASE__INST0_SEG4 01539#define DBGU_IO_BASE__INST0_SEG5 015401541#define DBGU_IO_BASE__INST1_SEG0 01542#define DBGU_IO_BASE__INST1_SEG1 01543#define DBGU_IO_BASE__INST1_SEG2 01544#define DBGU_IO_BASE__INST1_SEG3 01545#define DBGU_IO_BASE__INST1_SEG4 01546#define DBGU_IO_BASE__INST1_SEG5 015471548#define DBGU_IO_BASE__INST2_SEG0 01549#define DBGU_IO_BASE__INST2_SEG1 01550#define DBGU_IO_BASE__INST2_SEG2 01551#define DBGU_IO_BASE__INST2_SEG3 01552#define DBGU_IO_BASE__INST2_SEG4 01553#define DBGU_IO_BASE__INST2_SEG5 015541555#define DBGU_IO_BASE__INST3_SEG0 01556#define DBGU_IO_BASE__INST3_SEG1 01557#define DBGU_IO_BASE__INST3_SEG2 01558#define DBGU_IO_BASE__INST3_SEG3 01559#define DBGU_IO_BASE__INST3_SEG4 01560#define DBGU_IO_BASE__INST3_SEG5 015611562#define DBGU_IO_BASE__INST4_SEG0 01563#define DBGU_IO_BASE__INST4_SEG1 01564#define DBGU_IO_BASE__INST4_SEG2 01565#define DBGU_IO_BASE__INST4_SEG3 01566#define DBGU_IO_BASE__INST4_SEG4 01567#define DBGU_IO_BASE__INST4_SEG5 015681569#define DBGU_IO_BASE__INST5_SEG0 01570#define DBGU_IO_BASE__INST5_SEG1 01571#define DBGU_IO_BASE__INST5_SEG2 01572#define DBGU_IO_BASE__INST5_SEG3 01573#define DBGU_IO_BASE__INST5_SEG4 01574#define DBGU_IO_BASE__INST5_SEG5 015751576#define DBGU_IO_BASE__INST6_SEG0 01577#define DBGU_IO_BASE__INST6_SEG1 01578#define DBGU_IO_BASE__INST6_SEG2 01579#define DBGU_IO_BASE__INST6_SEG3 01580#define DBGU_IO_BASE__INST6_SEG4 01581#define DBGU_IO_BASE__INST6_SEG5 015821583#define DBGU_IO_BASE__INST7_SEG0 01584#define DBGU_IO_BASE__INST7_SEG1 01585#define DBGU_IO_BASE__INST7_SEG2 01586#define DBGU_IO_BASE__INST7_SEG3 01587#define DBGU_IO_BASE__INST7_SEG4 01588#define DBGU_IO_BASE__INST7_SEG5 015891590#define RSMU_BASE__INST0_SEG0 0x000120001591#define RSMU_BASE__INST0_SEG1 01592#define RSMU_BASE__INST0_SEG2 01593#define RSMU_BASE__INST0_SEG3 01594#define RSMU_BASE__INST0_SEG4 01595#define RSMU_BASE__INST0_SEG5 015961597#define RSMU_BASE__INST1_SEG0 01598#define RSMU_BASE__INST1_SEG1 01599#define RSMU_BASE__INST1_SEG2 01600#define RSMU_BASE__INST1_SEG3 01601#define RSMU_BASE__INST1_SEG4 01602#define RSMU_BASE__INST1_SEG5 016031604#define RSMU_BASE__INST2_SEG0 01605#define RSMU_BASE__INST2_SEG1 01606#define RSMU_BASE__INST2_SEG2 01607#define RSMU_BASE__INST2_SEG3 01608#define RSMU_BASE__INST2_SEG4 01609#define RSMU_BASE__INST2_SEG5 016101611#define RSMU_BASE__INST3_SEG0 01612#define RSMU_BASE__INST3_SEG1 01613#define RSMU_BASE__INST3_SEG2 01614#define RSMU_BASE__INST3_SEG3 01615#define RSMU_BASE__INST3_SEG4 01616#define RSMU_BASE__INST3_SEG5 016171618#define RSMU_BASE__INST4_SEG0 01619#define RSMU_BASE__INST4_SEG1 01620#define RSMU_BASE__INST4_SEG2 01621#define RSMU_BASE__INST4_SEG3 01622#define RSMU_BASE__INST4_SEG4 01623#define RSMU_BASE__INST4_SEG5 016241625#define RSMU_BASE__INST5_SEG0 01626#define RSMU_BASE__INST5_SEG1 01627#define RSMU_BASE__INST5_SEG2 01628#define RSMU_BASE__INST5_SEG3 01629#define RSMU_BASE__INST5_SEG4 01630#define RSMU_BASE__INST5_SEG5 016311632#define RSMU_BASE__INST6_SEG0 01633#define RSMU_BASE__INST6_SEG1 01634#define RSMU_BASE__INST6_SEG2 01635#define RSMU_BASE__INST6_SEG3 01636#define RSMU_BASE__INST6_SEG4 01637#define RSMU_BASE__INST6_SEG5 016381639#define RSMU_BASE__INST7_SEG0 01640#define RSMU_BASE__INST7_SEG1 01641#define RSMU_BASE__INST7_SEG2 01642#define RSMU_BASE__INST7_SEG3 01643#define RSMU_BASE__INST7_SEG4 01644#define RSMU_BASE__INST7_SEG5 0164516461647#endif164816491650