Path: blob/master/drivers/gpu/drm/amd/include/atombios.h
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/*1* Copyright 2006-2007 Advanced Micro Devices, Inc.2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice shall be included in11* all copies or substantial portions of the Software.12*13* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR14* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,15* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL16* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR17* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,18* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR19* OTHER DEALINGS IN THE SOFTWARE.20*/212223/****************************************************************************/24/*Portion I: Definitions shared between VBIOS and Driver */25/****************************************************************************/2627#ifndef _ATOMBIOS_H28#define _ATOMBIOS_H2930#define ATOM_VERSION_MAJOR 0x0002000031#define ATOM_VERSION_MINOR 0x000000023233#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)3435/* Endianness should be specified before inclusion,36* default to little endian37*/38#ifndef ATOM_BIG_ENDIAN39#error Endian not specified40#endif4142#ifdef _H2INC43#ifndef ULONG44typedef unsigned long ULONG;45#endif4647#ifndef UCHAR48typedef unsigned char UCHAR;49#endif5051#ifndef USHORT52typedef unsigned short USHORT;53#endif54#endif5556#define ATOM_DAC_A 057#define ATOM_DAC_B 158#define ATOM_EXT_DAC 25960#define ATOM_CRTC1 061#define ATOM_CRTC2 162#define ATOM_CRTC3 263#define ATOM_CRTC4 364#define ATOM_CRTC5 465#define ATOM_CRTC6 56667#define ATOM_UNDERLAY_PIPE0 1668#define ATOM_UNDERLAY_PIPE1 176970#define ATOM_CRTC_INVALID 0xFF7172#define ATOM_DIGA 073#define ATOM_DIGB 17475#define ATOM_PPLL1 076#define ATOM_PPLL2 177#define ATOM_DCPLL 278#define ATOM_PPLL0 279#define ATOM_PPLL3 38081#define ATOM_PHY_PLL0 482#define ATOM_PHY_PLL1 58384#define ATOM_EXT_PLL1 885#define ATOM_GCK_DFS 886#define ATOM_EXT_PLL2 987#define ATOM_FCH_CLK 988#define ATOM_EXT_CLOCK 1089#define ATOM_DP_DTO 119091#define ATOM_COMBOPHY_PLL0 2092#define ATOM_COMBOPHY_PLL1 2193#define ATOM_COMBOPHY_PLL2 2294#define ATOM_COMBOPHY_PLL3 2395#define ATOM_COMBOPHY_PLL4 2496#define ATOM_COMBOPHY_PLL5 259798#define ATOM_PPLL_INVALID 0xFF99100#define ENCODER_REFCLK_SRC_P1PLL 0101#define ENCODER_REFCLK_SRC_P2PLL 1102#define ENCODER_REFCLK_SRC_DCPLL 2103#define ENCODER_REFCLK_SRC_EXTCLK 3104#define ENCODER_REFCLK_SRC_INVALID 0xFF105106#define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication107#define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication108#define ATOM_SCALER_EXPANSION 2 //For Fudo, it's 2 Tap alpha blending mode109#define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV, only used by Bios110111#define ATOM_DISABLE 0112#define ATOM_ENABLE 1113#define ATOM_LCD_BLOFF (ATOM_DISABLE+2)114#define ATOM_LCD_BLON (ATOM_ENABLE+2)115#define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3)116#define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5)117#define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5)118#define ATOM_ENCODER_INIT (ATOM_DISABLE+7)119#define ATOM_INIT (ATOM_DISABLE+7)120#define ATOM_GET_STATUS (ATOM_DISABLE+8)121122#define ATOM_BLANKING 1123#define ATOM_BLANKING_OFF 0124125126#define ATOM_CRT1 0127#define ATOM_CRT2 1128129#define ATOM_TV_NTSC 1130#define ATOM_TV_NTSCJ 2131#define ATOM_TV_PAL 3132#define ATOM_TV_PALM 4133#define ATOM_TV_PALCN 5134#define ATOM_TV_PALN 6135#define ATOM_TV_PAL60 7136#define ATOM_TV_SECAM 8137#define ATOM_TV_CV 16138139#define ATOM_DAC1_PS2 1140#define ATOM_DAC1_CV 2141#define ATOM_DAC1_NTSC 3142#define ATOM_DAC1_PAL 4143144#define ATOM_DAC2_PS2 ATOM_DAC1_PS2145#define ATOM_DAC2_CV ATOM_DAC1_CV146#define ATOM_DAC2_NTSC ATOM_DAC1_NTSC147#define ATOM_DAC2_PAL ATOM_DAC1_PAL148149#define ATOM_PM_ON 0150#define ATOM_PM_STANDBY 1151#define ATOM_PM_SUSPEND 2152#define ATOM_PM_OFF 3153154// For ATOM_LVDS_INFO_V12155// Bit0:{=0:single, =1:dual},156// Bit1 {=0:666RGB, =1:888RGB},157// Bit2:3:{Grey level}158// Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}159#define ATOM_PANEL_MISC_DUAL 0x00000001160#define ATOM_PANEL_MISC_888RGB 0x00000002161#define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C162#define ATOM_PANEL_MISC_FPDI 0x00000010163#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2164#define ATOM_PANEL_MISC_SPATIAL 0x00000020165#define ATOM_PANEL_MISC_TEMPORAL 0x00000040166#define ATOM_PANEL_MISC_API_ENABLED 0x00000080167168#define MEMTYPE_DDR1 "DDR1"169#define MEMTYPE_DDR2 "DDR2"170#define MEMTYPE_DDR3 "DDR3"171#define MEMTYPE_DDR4 "DDR4"172173#define ASIC_BUS_TYPE_PCI "PCI"174#define ASIC_BUS_TYPE_AGP "AGP"175#define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS"176177//Maximum size of that FireGL flag string178#define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support179#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING )180181#define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop182#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING183184#define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support185#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING )186187#define HW_ASSISTED_I2C_STATUS_FAILURE 2188#define HW_ASSISTED_I2C_STATUS_SUCCESS 1189190#pragma pack(1) // BIOS data must use byte alignment191192// Define offset to location of ROM header.193#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L194#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L195196#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94197#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 //including the terminator 0x0!198#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f199#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e200201/****************************************************************************/202// Common header for all tables (Data table, Command table).203// Every table pointed _ATOM_MASTER_DATA_TABLE has this common header.204// And the pointer actually points to this header.205/****************************************************************************/206207typedef struct _ATOM_COMMON_TABLE_HEADER208{209USHORT usStructureSize;210UCHAR ucTableFormatRevision; //Change it when the Parser is not backward compatible211UCHAR ucTableContentRevision; //Change it only when the table needs to change but the firmware212//Image can't be updated, while Driver needs to carry the new table!213}ATOM_COMMON_TABLE_HEADER;214215/****************************************************************************/216// Structure stores the ROM header.217/****************************************************************************/218typedef struct _ATOM_ROM_HEADER219{220ATOM_COMMON_TABLE_HEADER sHeader;221UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,222//atombios should init it as "ATOM", don't change the position223USHORT usBiosRuntimeSegmentAddress;224USHORT usProtectedModeInfoOffset;225USHORT usConfigFilenameOffset;226USHORT usCRC_BlockOffset;227USHORT usBIOS_BootupMessageOffset;228USHORT usInt10Offset;229USHORT usPciBusDevInitCode;230USHORT usIoBaseAddress;231USHORT usSubsystemVendorID;232USHORT usSubsystemID;233USHORT usPCI_InfoOffset;234USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position235USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position236UCHAR ucExtendedFunctionCode;237UCHAR ucReserved;238}ATOM_ROM_HEADER;239240241typedef struct _ATOM_ROM_HEADER_V2_1242{243ATOM_COMMON_TABLE_HEADER sHeader;244UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,245//atombios should init it as "ATOM", don't change the position246USHORT usBiosRuntimeSegmentAddress;247USHORT usProtectedModeInfoOffset;248USHORT usConfigFilenameOffset;249USHORT usCRC_BlockOffset;250USHORT usBIOS_BootupMessageOffset;251USHORT usInt10Offset;252USHORT usPciBusDevInitCode;253USHORT usIoBaseAddress;254USHORT usSubsystemVendorID;255USHORT usSubsystemID;256USHORT usPCI_InfoOffset;257USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position258USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position259UCHAR ucExtendedFunctionCode;260UCHAR ucReserved;261ULONG ulPSPDirTableOffset;262}ATOM_ROM_HEADER_V2_1;263264265//==============================Command Table Portion====================================266267268/****************************************************************************/269// Structures used in Command.mtb270/****************************************************************************/271typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{272USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1273USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON274USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init275USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios276USHORT DIGxEncoderControl; //Only used by Bios277USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init278USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1279USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed280USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2281USHORT GPIOPinControl; //Atomic Table, only used by Bios282USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1283USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1284USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2285USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init286USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock287USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock288USHORT MemoryPLLInit; //Atomic Table, used only by Bios289USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes.290USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock291USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios292USHORT SetUniphyInstance; //Atomic Table, only used by Bios293USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2294USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3295USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1296USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1297USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1298USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1299USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead300USHORT GetConditionalGoldenSetting; //Only used by Bios301USHORT SMC_Init; //Function Table,directly used by various SW components,latest version 1.1302USHORT PatchMCSetting; //only used by BIOS303USHORT MC_SEQ_Control; //only used by BIOS304USHORT Gfx_Harvesting; //Atomic Table, Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting305USHORT EnableScaler; //Atomic Table, used only by Bios306USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1307USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1308USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1309USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1310USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios311USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1312USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1313USHORT GetSMUClockInfo; //Atomic Table, used only by Bios314USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1315USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios316USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios317USHORT LUT_AutoFill; //Atomic Table, only used by Bios318USHORT SetDCEClock; //Atomic Table, start from DCE11.1, shared by driver and VBIOS, change DISPCLK and DPREFCLK319USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1320USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1321USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1322USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1323USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1324USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios325USHORT MemoryCleanUp; //Atomic Table, only used by Bios326USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios327USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components328USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components329USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init330USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1331USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock332USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock333USHORT Gfx_Init; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock334USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios335USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock336USHORT MemoryTraining; //Atomic Table, used only by Bios337USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2338USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1339USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1340USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1341USHORT ReadEfuseValue; //Atomic Table, directly used by various SW components,latest version 1.1342USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"343USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init344USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock345USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender346USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1347USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1348USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1349USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1350USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios351USHORT DPEncoderService; //Function Table,only used by Bios352USHORT GetVoltageInfo; //Function Table,only used by Bios since SI353}ATOM_MASTER_LIST_OF_COMMAND_TABLES;354355// For backward compatible356#define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction357#define DPTranslatorControl DIG2EncoderControl358#define UNIPHYTransmitterControl DIG1TransmitterControl359#define LVTMATransmitterControl DIG2TransmitterControl360#define SetCRTC_DPM_State GetConditionalGoldenSetting361#define ASIC_StaticPwrMgtStatusChange SetUniphyInstance362#define HPDInterruptService ReadHWAssistedI2CStatus363#define EnableVGA_Access GetSCLKOverMCLKRatio364#define EnableYUV GetDispObjectInfo365#define DynamicClockGating EnableDispPowerGating366#define SetupHWAssistedI2CStatus ComputeMemoryClockParam367#define DAC2OutputControl ReadEfuseValue368369#define TMDSAEncoderControl PatchMCSetting370#define LVDSEncoderControl MC_SEQ_Control371#define LCD1OutputControl HW_Misc_Operation372#define TV1OutputControl Gfx_Harvesting373#define TVEncoderControl SMC_Init374#define EnableHW_IconCursor SetDCEClock375#define SetCRTC_Replication GetSMUClockInfo376377#define MemoryRefreshConversion Gfx_Init378379typedef struct _ATOM_MASTER_COMMAND_TABLE380{381ATOM_COMMON_TABLE_HEADER sHeader;382ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;383}ATOM_MASTER_COMMAND_TABLE;384385/****************************************************************************/386// Structures used in every command table387/****************************************************************************/388typedef struct _ATOM_TABLE_ATTRIBUTE389{390#if ATOM_BIG_ENDIAN391USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag392USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),393USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),394#else395USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),396USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),397USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag398#endif399}ATOM_TABLE_ATTRIBUTE;400401/****************************************************************************/402// Common header for all command tables.403// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header.404// And the pointer actually points to this header.405/****************************************************************************/406typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER407{408ATOM_COMMON_TABLE_HEADER CommonHeader;409ATOM_TABLE_ATTRIBUTE TableAttribute;410}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;411412/****************************************************************************/413// Structures used by ComputeMemoryEnginePLLTable414/****************************************************************************/415416#define COMPUTE_MEMORY_PLL_PARAM 1417#define COMPUTE_ENGINE_PLL_PARAM 2418#define ADJUST_MC_SETTING_PARAM 3419420/****************************************************************************/421// Structures used by AdjustMemoryControllerTable422/****************************************************************************/423typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ424{425#if ATOM_BIG_ENDIAN426ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block427ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]428ULONG ulClockFreq:24;429#else430ULONG ulClockFreq:24;431ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]432ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block433#endif434}ATOM_ADJUST_MEMORY_CLOCK_FREQ;435#define POINTER_RETURN_FLAG 0x80436437typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS438{439ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div440UCHAR ucAction; //0:reserved //1:Memory //2:Engine441UCHAR ucReserved; //may expand to return larger Fbdiv later442UCHAR ucFbDiv; //return value443UCHAR ucPostDiv; //return value444}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;445446typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2447{448ULONG ulClock; //When return, [23:0] return real clock449UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register450USHORT usFbDiv; //return Feedback value to be written to register451UCHAR ucPostDiv; //return post div to be written to register452}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;453454#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS455456#define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value457#define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)458#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition459#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change460#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup461#define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL462#define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK463464#define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)465#define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition466#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change467#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup468#define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL469#define b3DRAM_SELF_REFRESH_EXIT 0x20 //Applicable to DRAM self refresh exit only. when set, it means it will go to program DRAM self refresh exit path470#define b3SRIOV_INIT_BOOT 0x40 //Use by HV GPU driver only, to load uCode. for ASIC_InitTable SCLK parameter only471#define b3SRIOV_LOAD_UCODE 0x40 //Use by HV GPU driver only, to load uCode. for ASIC_InitTable SCLK parameter only472#define b3SRIOV_SKIP_ASIC_INIT 0x02 //Use by HV GPU driver only, skip ASIC_Init for primary adapter boot. for ASIC_InitTable SCLK parameter only473474typedef struct _ATOM_COMPUTE_CLOCK_FREQ475{476#if ATOM_BIG_ENDIAN477ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM478ULONG ulClockFreq:24; // in unit of 10kHz479#else480ULONG ulClockFreq:24; // in unit of 10kHz481ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM482#endif483}ATOM_COMPUTE_CLOCK_FREQ;484485typedef struct _ATOM_S_MPLL_FB_DIVIDER486{487USHORT usFbDivFrac;488USHORT usFbDiv;489}ATOM_S_MPLL_FB_DIVIDER;490491typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3492{493union494{495ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter496ULONG ulClockParams; //ULONG access for BE497ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter498};499UCHAR ucRefDiv; //Output Parameter500UCHAR ucPostDiv; //Output Parameter501UCHAR ucCntlFlag; //Output Parameter502UCHAR ucReserved;503}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3;504505// ucCntlFlag506#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1507#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2508#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4509#define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8510511512// V4 are only used for APU which PLL outside GPU513typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4514{515#if ATOM_BIG_ENDIAN516ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly517ULONG ulClock:24; //Input= target clock, output = actual clock518#else519ULONG ulClock:24; //Input= target clock, output = actual clock520ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly521#endif522}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4;523524typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5525{526union527{528ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter529ULONG ulClockParams; //ULONG access for BE530ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter531};532UCHAR ucRefDiv; //Output Parameter533UCHAR ucPostDiv; //Output Parameter534union535{536UCHAR ucCntlFlag; //Output Flags537UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode538};539UCHAR ucReserved;540}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5;541542543typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6544{545ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter546ULONG ulReserved[2];547}COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6;548549//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag550#define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f551#define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00552#define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01553554555typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6556{557COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider558ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter: PLL FB divider559UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider560UCHAR ucPllPostDiv; //Output Parameter: PLL post divider561UCHAR ucPllCntlFlag; //Output Flags: control flag562UCHAR ucReserved;563}COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6;564565//ucPllCntlFlag566#define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03567568typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7569{570ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter571ULONG ulReserved[5];572}COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7;573574//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag575#define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f576#define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00577#define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01578579typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7580{581COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider582USHORT usSclk_fcw_frac; //fractional divider of fcw = usSclk_fcw_frac/65536583USHORT usSclk_fcw_int; //integer divider of fcwc584UCHAR ucSclkPostDiv; //PLL post divider = 2^ucSclkPostDiv585UCHAR ucSclkVcoMode; //0: 4G~8Ghz, 1:3G~6Ghz,3: 2G~4Ghz, 2:Reserved586UCHAR ucSclkPllRange; //GreenTable SCLK PLL range entry index ( 0~7 )587UCHAR ucSscEnable;588USHORT usSsc_fcw1_frac; //fcw1_frac when SSC enable589USHORT usSsc_fcw1_int; //fcw1_int when SSC enable590USHORT usReserved;591USHORT usPcc_fcw_int;592USHORT usSsc_fcw_slew_frac; //fcw_slew_frac when SSC enable593USHORT usPcc_fcw_slew_frac;594}COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7;595596// ucInputFlag597#define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode598599// use for ComputeMemoryClockParamTable600typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1601{602union603{604ULONG ulClock;605ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)606};607UCHAR ucDllSpeed; //Output608UCHAR ucPostDiv; //Output609union{610UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode611UCHAR ucPllCntlFlag; //Output:612};613UCHAR ucBWCntl;614}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1;615616// definition of ucInputFlag617#define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01618// definition of ucPllCntlFlag619#define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03620#define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04621#define MPLL_CNTL_FLAG_QDR_ENABLE 0x08622#define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10623624//MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL625#define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04626627// use for ComputeMemoryClockParamTable628typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2629{630COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock;631ULONG ulReserved;632}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2;633634typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3635{636COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock;637USHORT usMclk_fcw_frac; //fractional divider of fcw = usSclk_fcw_frac/65536638USHORT usMclk_fcw_int; //integer divider of fcwc639}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3;640641//Input parameter of DynamicMemorySettingsTable642//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag = COMPUTE_MEMORY_PLL_PARAM643typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER644{645ATOM_COMPUTE_CLOCK_FREQ ulClock;646ULONG ulReserved[2];647}DYNAMICE_MEMORY_SETTINGS_PARAMETER;648649//Input parameter of DynamicMemorySettingsTable650//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag == COMPUTE_ENGINE_PLL_PARAM651typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER652{653ATOM_COMPUTE_CLOCK_FREQ ulClock;654ULONG ulMemoryClock;655ULONG ulReserved;656}DYNAMICE_ENGINE_SETTINGS_PARAMETER;657658//Input parameter of DynamicMemorySettingsTable ver2.1 and above659//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag == ADJUST_MC_SETTING_PARAM660typedef struct _DYNAMICE_MC_DPM_SETTINGS_PARAMETER661{662ATOM_COMPUTE_CLOCK_FREQ ulClock;663UCHAR ucMclkDPMState;664UCHAR ucReserved[3];665ULONG ulReserved;666}DYNAMICE_MC_DPM_SETTINGS_PARAMETER;667668//ucMclkDPMState669#define DYNAMIC_MC_DPM_SETTING_LOW_DPM_STATE 0670#define DYNAMIC_MC_DPM_SETTING_MEDIUM_DPM_STATE 1671#define DYNAMIC_MC_DPM_SETTING_HIGH_DPM_STATE 2672673typedef union _DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1674{675DYNAMICE_MEMORY_SETTINGS_PARAMETER asMCReg;676DYNAMICE_ENGINE_SETTINGS_PARAMETER asMCArbReg;677DYNAMICE_MC_DPM_SETTINGS_PARAMETER asDPMMCReg;678}DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1;679680681/****************************************************************************/682// Structures used by SetEngineClockTable683/****************************************************************************/684typedef struct _SET_ENGINE_CLOCK_PARAMETERS685{686ULONG ulTargetEngineClock; //In 10Khz unit687}SET_ENGINE_CLOCK_PARAMETERS;688689typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION690{691ULONG ulTargetEngineClock; //In 10Khz unit692COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;693}SET_ENGINE_CLOCK_PS_ALLOCATION;694695typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2696{697ULONG ulTargetEngineClock; //In 10Khz unit698COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7 sReserved;699}SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2;700701702/****************************************************************************/703// Structures used by SetMemoryClockTable704/****************************************************************************/705typedef struct _SET_MEMORY_CLOCK_PARAMETERS706{707ULONG ulTargetMemoryClock; //In 10Khz unit708}SET_MEMORY_CLOCK_PARAMETERS;709710typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION711{712ULONG ulTargetMemoryClock; //In 10Khz unit713COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;714}SET_MEMORY_CLOCK_PS_ALLOCATION;715716/****************************************************************************/717// Structures used by ASIC_Init.ctb718/****************************************************************************/719typedef struct _ASIC_INIT_PARAMETERS720{721ULONG ulDefaultEngineClock; //In 10Khz unit722ULONG ulDefaultMemoryClock; //In 10Khz unit723}ASIC_INIT_PARAMETERS;724725typedef struct _ASIC_INIT_PS_ALLOCATION726{727ASIC_INIT_PARAMETERS sASICInitClocks;728SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure729}ASIC_INIT_PS_ALLOCATION;730731typedef struct _ASIC_INIT_CLOCK_PARAMETERS732{733ULONG ulClkFreqIn10Khz:24;734ULONG ucClkFlag:8;735}ASIC_INIT_CLOCK_PARAMETERS;736737typedef struct _ASIC_INIT_PARAMETERS_V1_2738{739ASIC_INIT_CLOCK_PARAMETERS asSclkClock; //In 10Khz unit740ASIC_INIT_CLOCK_PARAMETERS asMemClock; //In 10Khz unit741}ASIC_INIT_PARAMETERS_V1_2;742743typedef struct _ASIC_INIT_PS_ALLOCATION_V1_2744{745ASIC_INIT_PARAMETERS_V1_2 sASICInitClocks;746ULONG ulReserved[8];747}ASIC_INIT_PS_ALLOCATION_V1_2;748749/****************************************************************************/750// Structure used by DynamicClockGatingTable.ctb751/****************************************************************************/752typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS753{754UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE755UCHAR ucPadding[3];756}DYNAMIC_CLOCK_GATING_PARAMETERS;757#define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS758759/****************************************************************************/760// Structure used by EnableDispPowerGatingTable.ctb761/****************************************************************************/762typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1763{764UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ...765UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE766UCHAR ucPadding[2];767}ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1;768769typedef struct _ENABLE_DISP_POWER_GATING_PS_ALLOCATION770{771UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ...772UCHAR ucEnable; // ATOM_ENABLE/ATOM_DISABLE/ATOM_INIT773UCHAR ucPadding[2];774ULONG ulReserved[4];775}ENABLE_DISP_POWER_GATING_PS_ALLOCATION;776777/****************************************************************************/778// Structure used by EnableASIC_StaticPwrMgtTable.ctb779/****************************************************************************/780typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS781{782UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE783UCHAR ucPadding[3];784}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;785#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS786787/****************************************************************************/788// Structures used by DAC_LoadDetectionTable.ctb789/****************************************************************************/790typedef struct _DAC_LOAD_DETECTION_PARAMETERS791{792USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}793UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}794UCHAR ucMisc; //Valid only when table revision =1.3 and above795}DAC_LOAD_DETECTION_PARAMETERS;796797// DAC_LOAD_DETECTION_PARAMETERS.ucMisc798#define DAC_LOAD_MISC_YPrPb 0x01799800typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION801{802DAC_LOAD_DETECTION_PARAMETERS sDacload;803ULONG Reserved[2];// Don't set this one, allocation for EXT DAC804}DAC_LOAD_DETECTION_PS_ALLOCATION;805806/****************************************************************************/807// Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb808/****************************************************************************/809typedef struct _DAC_ENCODER_CONTROL_PARAMETERS810{811USHORT usPixelClock; // in 10KHz; for bios convenient812UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)813UCHAR ucAction; // 0: turn off encoder814// 1: setup and turn on encoder815// 7: ATOM_ENCODER_INIT Initialize DAC816}DAC_ENCODER_CONTROL_PARAMETERS;817818#define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS819820/****************************************************************************/821// Structures used by DIG1EncoderControlTable822// DIG2EncoderControlTable823// ExternalEncoderControlTable824/****************************************************************************/825typedef struct _DIG_ENCODER_CONTROL_PARAMETERS826{827USHORT usPixelClock; // in 10KHz; for bios convenient828UCHAR ucConfig;829// [2] Link Select:830// =0: PHY linkA if bfLane<3831// =1: PHY linkB if bfLanes<3832// =0: PHY linkA+B if bfLanes=3833// [3] Transmitter Sel834// =0: UNIPHY or PCIEPHY835// =1: LVTMA836UCHAR ucAction; // =0: turn off encoder837// =1: turn on encoder838UCHAR ucEncoderMode;839// =0: DP encoder840// =1: LVDS encoder841// =2: DVI encoder842// =3: HDMI encoder843// =4: SDVO encoder844UCHAR ucLaneNum; // how many lanes to enable845UCHAR ucReserved[2];846}DIG_ENCODER_CONTROL_PARAMETERS;847#define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS848#define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS849850//ucConfig851#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01852#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00853#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01854#define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02855#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04856#define ATOM_ENCODER_CONFIG_LINKA 0x00857#define ATOM_ENCODER_CONFIG_LINKB 0x04858#define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA859#define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB860#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08861#define ATOM_ENCODER_CONFIG_UNIPHY 0x00862#define ATOM_ENCODER_CONFIG_LVTMA 0x08863#define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00864#define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08865#define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0866// ucAction867// ATOM_ENABLE: Enable Encoder868// ATOM_DISABLE: Disable Encoder869870//ucEncoderMode871#define ATOM_ENCODER_MODE_DP 0872#define ATOM_ENCODER_MODE_LVDS 1873#define ATOM_ENCODER_MODE_DVI 2874#define ATOM_ENCODER_MODE_HDMI 3875#define ATOM_ENCODER_MODE_SDVO 4876#define ATOM_ENCODER_MODE_DP_AUDIO 5877#define ATOM_ENCODER_MODE_TV 13878#define ATOM_ENCODER_MODE_CV 14879#define ATOM_ENCODER_MODE_CRT 15880#define ATOM_ENCODER_MODE_DVO 16881#define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2882#define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2883884885typedef struct _ATOM_DIG_ENCODER_CONFIG_V2886{887#if ATOM_BIG_ENDIAN888UCHAR ucReserved1:2;889UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF890UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F891UCHAR ucReserved:1;892UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz893#else894UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz895UCHAR ucReserved:1;896UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F897UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF898UCHAR ucReserved1:2;899#endif900}ATOM_DIG_ENCODER_CONFIG_V2;901902903typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2904{905USHORT usPixelClock; // in 10KHz; for bios convenient906ATOM_DIG_ENCODER_CONFIG_V2 acConfig;907UCHAR ucAction;908UCHAR ucEncoderMode;909// =0: DP encoder910// =1: LVDS encoder911// =2: DVI encoder912// =3: HDMI encoder913// =4: SDVO encoder914UCHAR ucLaneNum; // how many lanes to enable915UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS916UCHAR ucReserved;917}DIG_ENCODER_CONTROL_PARAMETERS_V2;918919//ucConfig920#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01921#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00922#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01923#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04924#define ATOM_ENCODER_CONFIG_V2_LINKA 0x00925#define ATOM_ENCODER_CONFIG_V2_LINKB 0x04926#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18927#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00928#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08929#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10930931// ucAction:932// ATOM_DISABLE933// ATOM_ENABLE934#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08935#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09936#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a937#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13938#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b939#define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c940#define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d941#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e942#define ATOM_ENCODER_CMD_SETUP 0x0f943#define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10944945// New Command for DIGxEncoderControlTable v1.5946#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 0x14947#define ATOM_ENCODER_CMD_STREAM_SETUP 0x0F //change name ATOM_ENCODER_CMD_SETUP948#define ATOM_ENCODER_CMD_LINK_SETUP 0x11 //internal use, called by other Command Table949#define ATOM_ENCODER_CMD_ENCODER_BLANK 0x12 //internal use, called by other Command Table950951// ucStatus952#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10953#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00954955//ucTableFormatRevision=1956//ucTableContentRevision=3957// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver958typedef struct _ATOM_DIG_ENCODER_CONFIG_V3959{960#if ATOM_BIG_ENDIAN961UCHAR ucReserved1:1;962UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)963UCHAR ucReserved:3;964UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz965#else966UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz967UCHAR ucReserved:3;968UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)969UCHAR ucReserved1:1;970#endif971}ATOM_DIG_ENCODER_CONFIG_V3;972973#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03974#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00975#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01976#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70977#define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00978#define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10979#define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20980#define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30981#define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40982#define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50983984typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3985{986USHORT usPixelClock; // in 10KHz; for bios convenient987ATOM_DIG_ENCODER_CONFIG_V3 acConfig;988UCHAR ucAction;989union{990UCHAR ucEncoderMode;991// =0: DP encoder992// =1: LVDS encoder993// =2: DVI encoder994// =3: HDMI encoder995// =4: SDVO encoder996// =5: DP audio997UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE998// =0: external DP999// =0x1: internal DP21000// =0x11: internal DP1 for NutMeg/Travis DP translator1001};1002UCHAR ucLaneNum; // how many lanes to enable1003UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP1004UCHAR ucReserved;1005}DIG_ENCODER_CONTROL_PARAMETERS_V3;10061007//ucTableFormatRevision=11008//ucTableContentRevision=41009// start from NI1010// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver1011typedef struct _ATOM_DIG_ENCODER_CONFIG_V41012{1013#if ATOM_BIG_ENDIAN1014UCHAR ucReserved1:1;1015UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)1016UCHAR ucReserved:2;1017UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version1018#else1019UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version1020UCHAR ucReserved:2;1021UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)1022UCHAR ucReserved1:1;1023#endif1024}ATOM_DIG_ENCODER_CONFIG_V4;10251026#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x031027#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x001028#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x011029#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x021030#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x031031#define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x701032#define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x001033#define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x101034#define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x201035#define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x301036#define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x401037#define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x501038#define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x6010391040typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V41041{1042USHORT usPixelClock; // in 10KHz; for bios convenient1043union{1044ATOM_DIG_ENCODER_CONFIG_V4 acConfig;1045UCHAR ucConfig;1046};1047UCHAR ucAction;1048union{1049UCHAR ucEncoderMode;1050// =0: DP encoder1051// =1: LVDS encoder1052// =2: DVI encoder1053// =3: HDMI encoder1054// =4: SDVO encoder1055// =5: DP audio1056UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE1057// =0: external DP1058// =0x1: internal DP21059// =0x11: internal DP1 for NutMeg/Travis DP translator1060};1061UCHAR ucLaneNum; // how many lanes to enable1062UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP1063UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version1064}DIG_ENCODER_CONTROL_PARAMETERS_V4;10651066// define ucBitPerColor:1067#define PANEL_BPC_UNDEFINE 0x001068#define PANEL_6BIT_PER_COLOR 0x011069#define PANEL_8BIT_PER_COLOR 0x021070#define PANEL_10BIT_PER_COLOR 0x031071#define PANEL_12BIT_PER_COLOR 0x041072#define PANEL_16BIT_PER_COLOR 0x0510731074//define ucPanelMode1075#define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x001076#define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x011077#define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11107810791080typedef struct _ENCODER_STREAM_SETUP_PARAMETERS_V51081{1082UCHAR ucDigId; // 0~6 map to DIG0~DIG61083UCHAR ucAction; // = ATOM_ENOCODER_CMD_STREAM_SETUP1084UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI1085UCHAR ucLaneNum; // Lane number1086ULONG ulPixelClock; // Pixel Clock in 10Khz1087UCHAR ucBitPerColor;1088UCHAR ucLinkRateIn270Mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc1089UCHAR ucReserved[2];1090}ENCODER_STREAM_SETUP_PARAMETERS_V5;10911092typedef struct _ENCODER_LINK_SETUP_PARAMETERS_V51093{1094UCHAR ucDigId; // 0~6 map to DIG0~DIG61095UCHAR ucAction; // = ATOM_ENOCODER_CMD_LINK_SETUP1096UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI1097UCHAR ucLaneNum; // Lane number1098ULONG ulSymClock; // Symbol Clock in 10Khz1099UCHAR ucHPDSel;1100UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,1101UCHAR ucReserved[2];1102}ENCODER_LINK_SETUP_PARAMETERS_V5;11031104typedef struct _DP_PANEL_MODE_SETUP_PARAMETERS_V51105{1106UCHAR ucDigId; // 0~6 map to DIG0~DIG61107UCHAR ucAction; // = ATOM_ENCODER_CMD_DPLINK_SETUP1108UCHAR ucPanelMode; // =0: external DP1109// =0x1: internal DP21110// =0x11: internal DP1 NutMeg/Travis DP Translator1111UCHAR ucReserved;1112ULONG ulReserved[2];1113}DP_PANEL_MODE_SETUP_PARAMETERS_V5;11141115typedef struct _ENCODER_GENERIC_CMD_PARAMETERS_V51116{1117UCHAR ucDigId; // 0~6 map to DIG0~DIG61118UCHAR ucAction; // = rest of generic encoder command which does not carry any parameters1119UCHAR ucReserved[2];1120ULONG ulReserved[2];1121}ENCODER_GENERIC_CMD_PARAMETERS_V5;11221123//ucDigId1124#define ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER 0x001125#define ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER 0x011126#define ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER 0x021127#define ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER 0x031128#define ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER 0x041129#define ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER 0x051130#define ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER 0x06113111321133typedef union _DIG_ENCODER_CONTROL_PARAMETERS_V51134{1135ENCODER_GENERIC_CMD_PARAMETERS_V5 asCmdParam;1136ENCODER_STREAM_SETUP_PARAMETERS_V5 asStreamParam;1137ENCODER_LINK_SETUP_PARAMETERS_V5 asLinkParam;1138DP_PANEL_MODE_SETUP_PARAMETERS_V5 asDPPanelModeParam;1139}DIG_ENCODER_CONTROL_PARAMETERS_V5;114011411142/****************************************************************************/1143// Structures used by UNIPHYTransmitterControlTable1144// LVTMATransmitterControlTable1145// DVOOutputControlTable1146/****************************************************************************/1147typedef struct _ATOM_DP_VS_MODE1148{1149UCHAR ucLaneSel;1150UCHAR ucLaneSet;1151}ATOM_DP_VS_MODE;11521153typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS1154{1155union1156{1157USHORT usPixelClock; // in 10KHz; for bios convenient1158USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h1159ATOM_DP_VS_MODE asMode; // DP Voltage swing mode1160};1161UCHAR ucConfig;1162// [0]=0: 4 lane Link,1163// =1: 8 lane Link ( Dual Links TMDS )1164// [1]=0: InCoherent mode1165// =1: Coherent Mode1166// [2] Link Select:1167// =0: PHY linkA if bfLane<31168// =1: PHY linkB if bfLanes<31169// =0: PHY linkA+B if bfLanes=31170// [5:4]PCIE lane Sel1171// =0: lane 0~3 or 0~71172// =1: lane 4~71173// =2: lane 8~11 or 8~151174// =3: lane 12~151175UCHAR ucAction; // =0: turn off encoder1176// =1: turn on encoder1177UCHAR ucReserved[4];1178}DIG_TRANSMITTER_CONTROL_PARAMETERS;11791180#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS11811182//ucInitInfo1183#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff11841185//ucConfig1186#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x011187#define ATOM_TRANSMITTER_CONFIG_COHERENT 0x021188#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x041189#define ATOM_TRANSMITTER_CONFIG_LINKA 0x001190#define ATOM_TRANSMITTER_CONFIG_LINKB 0x041191#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x001192#define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x0411931194#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE1195#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE1196#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE11971198#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x301199#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x001200#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x201201#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x301202#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc01203#define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x001204#define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x001205#define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x401206#define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x801207#define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x801208#define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc012091210//ucAction1211#define ATOM_TRANSMITTER_ACTION_DISABLE 01212#define ATOM_TRANSMITTER_ACTION_ENABLE 11213#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 21214#define ATOM_TRANSMITTER_ACTION_LCD_BLON 31215#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 41216#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 51217#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 61218#define ATOM_TRANSMITTER_ACTION_INIT 71219#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 81220#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 91221#define ATOM_TRANSMITTER_ACTION_SETUP 101222#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 111223#define ATOM_TRANSMITTER_ACTION_POWER_ON 121224#define ATOM_TRANSMITTER_ACTION_POWER_OFF 1312251226// Following are used for DigTransmitterControlTable ver1.21227typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V21228{1229#if ATOM_BIG_ENDIAN1230UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )1231// =1 Dig Transmitter 2 ( Uniphy CD )1232// =2 Dig Transmitter 3 ( Uniphy EF )1233UCHAR ucReserved:1;1234UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector1235UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )1236UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E1237// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F12381239UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )1240UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector1241#else1242UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector1243UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )1244UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E1245// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F1246UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )1247UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector1248UCHAR ucReserved:1;1249UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )1250// =1 Dig Transmitter 2 ( Uniphy CD )1251// =2 Dig Transmitter 3 ( Uniphy EF )1252#endif1253}ATOM_DIG_TRANSMITTER_CONFIG_V2;12541255//ucConfig1256//Bit01257#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x0112581259//Bit11260#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x0212611262//Bit21263#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x041264#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x001265#define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x0412661267// Bit31268#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x081269#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP1270#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP12711272// Bit41273#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x1012741275// Bit7:61276#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC01277#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB1278#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD1279#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF12801281typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V21282{1283union1284{1285USHORT usPixelClock; // in 10KHz; for bios convenient1286USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h1287ATOM_DP_VS_MODE asMode; // DP Voltage swing mode1288};1289ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig;1290UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX1291UCHAR ucReserved[4];1292}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2;12931294typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V31295{1296#if ATOM_BIG_ENDIAN1297UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )1298// =1 Dig Transmitter 2 ( Uniphy CD )1299// =2 Dig Transmitter 3 ( Uniphy EF )1300UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=21301UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F1302UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E1303// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F1304UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )1305UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector1306#else1307UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector1308UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )1309UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E1310// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F1311UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F1312UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=21313UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )1314// =1 Dig Transmitter 2 ( Uniphy CD )1315// =2 Dig Transmitter 3 ( Uniphy EF )1316#endif1317}ATOM_DIG_TRANSMITTER_CONFIG_V3;131813191320typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V31321{1322union1323{1324USHORT usPixelClock; // in 10KHz; for bios convenient1325USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h1326ATOM_DP_VS_MODE asMode; // DP Voltage swing mode1327};1328ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig;1329UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX1330UCHAR ucLaneNum;1331UCHAR ucReserved[3];1332}DIG_TRANSMITTER_CONTROL_PARAMETERS_V3;13331334//ucConfig1335//Bit01336#define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x0113371338//Bit11339#define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x0213401341//Bit21342#define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x041343#define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x001344#define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x0413451346// Bit31347#define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x081348#define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x001349#define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x0813501351// Bit5:41352#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x301353#define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x001354#define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x101355#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x2013561357// Bit7:61358#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC01359#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB1360#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD1361#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF136213631364/****************************************************************************/1365// Structures used by UNIPHYTransmitterControlTable V1.41366// ASIC Families: NI1367// ucTableFormatRevision=11368// ucTableContentRevision=41369/****************************************************************************/1370typedef struct _ATOM_DP_VS_MODE_V41371{1372UCHAR ucLaneSel;1373union1374{1375UCHAR ucLaneSet;1376struct {1377#if ATOM_BIG_ENDIAN1378UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V41379UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level1380UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level1381#else1382UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level1383UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level1384UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V41385#endif1386};1387};1388}ATOM_DP_VS_MODE_V4;13891390typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V41391{1392#if ATOM_BIG_ENDIAN1393UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )1394// =1 Dig Transmitter 2 ( Uniphy CD )1395// =2 Dig Transmitter 3 ( Uniphy EF )1396UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New1397UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F1398UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E1399// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F1400UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )1401UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector1402#else1403UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector1404UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )1405UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E1406// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F1407UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F1408UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New1409UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )1410// =1 Dig Transmitter 2 ( Uniphy CD )1411// =2 Dig Transmitter 3 ( Uniphy EF )1412#endif1413}ATOM_DIG_TRANSMITTER_CONFIG_V4;14141415typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V41416{1417union1418{1419USHORT usPixelClock; // in 10KHz; for bios convenient1420USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h1421ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version1422};1423union1424{1425ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig;1426UCHAR ucConfig;1427};1428UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX1429UCHAR ucLaneNum;1430UCHAR ucReserved[3];1431}DIG_TRANSMITTER_CONTROL_PARAMETERS_V4;14321433//ucConfig1434//Bit01435#define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x011436//Bit11437#define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x021438//Bit21439#define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x041440#define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x001441#define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x041442// Bit31443#define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x081444#define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x001445#define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x081446// Bit5:41447#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x301448#define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x001449#define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x101450#define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V41451#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V31452// Bit7:61453#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC01454#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB1455#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD1456#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF145714581459typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V51460{1461#if ATOM_BIG_ENDIAN1462UCHAR ucReservd1:1;1463UCHAR ucHPDSel:3;1464UCHAR ucPhyClkSrcId:2;1465UCHAR ucCoherentMode:1;1466UCHAR ucReserved:1;1467#else1468UCHAR ucReserved:1;1469UCHAR ucCoherentMode:1;1470UCHAR ucPhyClkSrcId:2;1471UCHAR ucHPDSel:3;1472UCHAR ucReservd1:1;1473#endif1474}ATOM_DIG_TRANSMITTER_CONFIG_V5;14751476typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_51477{1478USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio1479UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF1480UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx1481UCHAR ucLaneNum; // indicate lane number 1-81482UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h1483UCHAR ucDigMode; // indicate DIG mode1484union{1485ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;1486UCHAR ucConfig;1487};1488UCHAR ucDigEncoderSel; // indicate DIG front end encoder1489UCHAR ucDPLaneSet;1490UCHAR ucReserved;1491UCHAR ucReserved1;1492}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5;14931494//ucPhyId1495#define ATOM_PHY_ID_UNIPHYA 01496#define ATOM_PHY_ID_UNIPHYB 11497#define ATOM_PHY_ID_UNIPHYC 21498#define ATOM_PHY_ID_UNIPHYD 31499#define ATOM_PHY_ID_UNIPHYE 41500#define ATOM_PHY_ID_UNIPHYF 51501#define ATOM_PHY_ID_UNIPHYG 615021503// ucDigEncoderSel1504#define ATOM_TRANMSITTER_V5__DIGA_SEL 0x011505#define ATOM_TRANMSITTER_V5__DIGB_SEL 0x021506#define ATOM_TRANMSITTER_V5__DIGC_SEL 0x041507#define ATOM_TRANMSITTER_V5__DIGD_SEL 0x081508#define ATOM_TRANMSITTER_V5__DIGE_SEL 0x101509#define ATOM_TRANMSITTER_V5__DIGF_SEL 0x201510#define ATOM_TRANMSITTER_V5__DIGG_SEL 0x4015111512// ucDigMode1513#define ATOM_TRANSMITTER_DIGMODE_V5_DP 01514#define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 11515#define ATOM_TRANSMITTER_DIGMODE_V5_DVI 21516#define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 31517#define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 41518#define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 515191520// ucDPLaneSet1521#define DP_LANE_SET__0DB_0_4V 0x001522#define DP_LANE_SET__0DB_0_6V 0x011523#define DP_LANE_SET__0DB_0_8V 0x021524#define DP_LANE_SET__0DB_1_2V 0x031525#define DP_LANE_SET__3_5DB_0_4V 0x081526#define DP_LANE_SET__3_5DB_0_6V 0x091527#define DP_LANE_SET__3_5DB_0_8V 0x0a1528#define DP_LANE_SET__6DB_0_4V 0x101529#define DP_LANE_SET__6DB_0_6V 0x111530#define DP_LANE_SET__9_5DB_0_4V 0x1815311532// ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;1533// Bit11534#define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x0215351536// Bit3:21537#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c1538#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x0215391540#define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x001541#define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x041542#define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x081543#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c1544// Bit6:41545#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x701546#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x0415471548#define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x001549#define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x101550#define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x201551#define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x301552#define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x401553#define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x501554#define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x6015551556#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_515571558typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_61559{1560UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF1561UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx1562union1563{1564UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI1565UCHAR ucDPLaneSet; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"1566};1567UCHAR ucLaneNum; // Lane number1568ULONG ulSymClock; // Symbol Clock in 10Khz1569UCHAR ucHPDSel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned1570UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,1571UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h1572UCHAR ucReserved;1573ULONG ulReserved;1574}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6;157515761577// ucDigEncoderSel1578#define ATOM_TRANMSITTER_V6__DIGA_SEL 0x011579#define ATOM_TRANMSITTER_V6__DIGB_SEL 0x021580#define ATOM_TRANMSITTER_V6__DIGC_SEL 0x041581#define ATOM_TRANMSITTER_V6__DIGD_SEL 0x081582#define ATOM_TRANMSITTER_V6__DIGE_SEL 0x101583#define ATOM_TRANMSITTER_V6__DIGF_SEL 0x201584#define ATOM_TRANMSITTER_V6__DIGG_SEL 0x4015851586// ucDigMode1587#define ATOM_TRANSMITTER_DIGMODE_V6_DP 01588#define ATOM_TRANSMITTER_DIGMODE_V6_DVI 21589#define ATOM_TRANSMITTER_DIGMODE_V6_HDMI 31590#define ATOM_TRANSMITTER_DIGMODE_V6_DP_MST 515911592//ucHPDSel1593#define ATOM_TRANSMITTER_V6_NO_HPD_SEL 0x001594#define ATOM_TRANSMITTER_V6_HPD1_SEL 0x011595#define ATOM_TRANSMITTER_V6_HPD2_SEL 0x021596#define ATOM_TRANSMITTER_V6_HPD3_SEL 0x031597#define ATOM_TRANSMITTER_V6_HPD4_SEL 0x041598#define ATOM_TRANSMITTER_V6_HPD5_SEL 0x051599#define ATOM_TRANSMITTER_V6_HPD6_SEL 0x06160016011602/****************************************************************************/1603// Structures used by ExternalEncoderControlTable V1.31604// ASIC Families: Evergreen, Llano, NI1605// ucTableFormatRevision=11606// ucTableContentRevision=31607/****************************************************************************/16081609typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V31610{1611union{1612USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT1613USHORT usConnectorId; // connector id, valid when ucAction = INIT1614};1615UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT1616UCHAR ucAction; //1617UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT1618UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT1619UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP1620UCHAR ucReserved;1621}EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3;16221623// ucAction1624#define EXTERANL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x001625#define EXTERANL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x011626#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x071627#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f1628#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x101629#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x111630#define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x121631#define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x1416321633// ucConfig1634#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x031635#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x001636#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x011637#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x021638#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS 0x701639#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x001640#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x101641#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x2016421643typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V31644{1645EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder;1646ULONG ulReserved[2];1647}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3;164816491650/****************************************************************************/1651// Structures used by DAC1OuputControlTable1652// DAC2OuputControlTable1653// LVTMAOutputControlTable (Before DEC30)1654// TMDSAOutputControlTable (Before DEC30)1655/****************************************************************************/1656typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS1657{1658UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE1659// When the display is LCD, in addition to above:1660// ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START||1661// ATOM_LCD_SELFTEST_STOP16621663UCHAR aucPadding[3]; // padding to DWORD aligned1664}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS;16651666#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS166716681669#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS1670#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION16711672#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS1673#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION16741675#define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS1676#define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION16771678#define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS1679#define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION16801681#define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS1682#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION16831684#define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS1685#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION16861687#define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS1688#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION16891690#define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS1691#define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION1692#define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS169316941695typedef struct _LVTMA_OUTPUT_CONTROL_PARAMETERS_V21696{1697// Possible value of ucAction1698// ATOM_TRANSMITTER_ACTION_LCD_BLON1699// ATOM_TRANSMITTER_ACTION_LCD_BLOFF1700// ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL1701// ATOM_TRANSMITTER_ACTION_POWER_ON1702// ATOM_TRANSMITTER_ACTION_POWER_OFF1703UCHAR ucAction;1704UCHAR ucBriLevel;1705USHORT usPwmFreq; // in unit of Hz, 200 means 200Hz1706}LVTMA_OUTPUT_CONTROL_PARAMETERS_V2;1707170817091710/****************************************************************************/1711// Structures used by BlankCRTCTable1712/****************************************************************************/1713typedef struct _BLANK_CRTC_PARAMETERS1714{1715UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC21716UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF1717USHORT usBlackColorRCr;1718USHORT usBlackColorGY;1719USHORT usBlackColorBCb;1720}BLANK_CRTC_PARAMETERS;1721#define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS17221723/****************************************************************************/1724// Structures used by EnableCRTCTable1725// EnableCRTCMemReqTable1726// UpdateCRTC_DoubleBufferRegistersTable1727/****************************************************************************/1728typedef struct _ENABLE_CRTC_PARAMETERS1729{1730UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC21731UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE1732UCHAR ucPadding[2];1733}ENABLE_CRTC_PARAMETERS;1734#define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS17351736/****************************************************************************/1737// Structures used by SetCRTC_OverScanTable1738/****************************************************************************/1739typedef struct _SET_CRTC_OVERSCAN_PARAMETERS1740{1741USHORT usOverscanRight; // right1742USHORT usOverscanLeft; // left1743USHORT usOverscanBottom; // bottom1744USHORT usOverscanTop; // top1745UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC21746UCHAR ucPadding[3];1747}SET_CRTC_OVERSCAN_PARAMETERS;1748#define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS17491750/****************************************************************************/1751// Structures used by SetCRTC_ReplicationTable1752/****************************************************************************/1753typedef struct _SET_CRTC_REPLICATION_PARAMETERS1754{1755UCHAR ucH_Replication; // horizontal replication1756UCHAR ucV_Replication; // vertical replication1757UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC21758UCHAR ucPadding;1759}SET_CRTC_REPLICATION_PARAMETERS;1760#define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS17611762/****************************************************************************/1763// Structures used by SelectCRTC_SourceTable1764/****************************************************************************/1765typedef struct _SELECT_CRTC_SOURCE_PARAMETERS1766{1767UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC21768UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....1769UCHAR ucPadding[2];1770}SELECT_CRTC_SOURCE_PARAMETERS;1771#define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS17721773typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V21774{1775UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC21776UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO1777UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO1778UCHAR ucPadding;1779}SELECT_CRTC_SOURCE_PARAMETERS_V2;17801781//ucEncoderID1782//#define ASIC_INT_DAC1_ENCODER_ID 0x001783//#define ASIC_INT_TV_ENCODER_ID 0x021784//#define ASIC_INT_DIG1_ENCODER_ID 0x031785//#define ASIC_INT_DAC2_ENCODER_ID 0x041786//#define ASIC_EXT_TV_ENCODER_ID 0x061787//#define ASIC_INT_DVO_ENCODER_ID 0x071788//#define ASIC_INT_DIG2_ENCODER_ID 0x091789//#define ASIC_EXT_DIG_ENCODER_ID 0x0517901791//ucEncodeMode1792//#define ATOM_ENCODER_MODE_DP 01793//#define ATOM_ENCODER_MODE_LVDS 11794//#define ATOM_ENCODER_MODE_DVI 21795//#define ATOM_ENCODER_MODE_HDMI 31796//#define ATOM_ENCODER_MODE_SDVO 41797//#define ATOM_ENCODER_MODE_TV 131798//#define ATOM_ENCODER_MODE_CV 141799//#define ATOM_ENCODER_MODE_CRT 15180018011802typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V31803{1804UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC21805UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO1806UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO1807UCHAR ucDstBpc; // PANEL_6/8/10/12BIT_PER_COLOR1808}SELECT_CRTC_SOURCE_PARAMETERS_V3;180918101811/****************************************************************************/1812// Structures used by SetPixelClockTable1813// GetPixelClockTable1814/****************************************************************************/1815//Major revision=1., Minor revision=11816typedef struct _PIXEL_CLOCK_PARAMETERS1817{1818USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)1819// 0 means disable PPLL1820USHORT usRefDiv; // Reference divider1821USHORT usFbDiv; // feedback divider1822UCHAR ucPostDiv; // post divider1823UCHAR ucFracFbDiv; // fractional feedback divider1824UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL21825UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER1826UCHAR ucCRTC; // Which CRTC uses this Ppll1827UCHAR ucPadding;1828}PIXEL_CLOCK_PARAMETERS;18291830//Major revision=1., Minor revision=2, add ucMiscIfno1831//ucMiscInfo:1832#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x11833#define MISC_DEVICE_INDEX_MASK 0xF01834#define MISC_DEVICE_INDEX_SHIFT 418351836typedef struct _PIXEL_CLOCK_PARAMETERS_V21837{1838USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)1839// 0 means disable PPLL1840USHORT usRefDiv; // Reference divider1841USHORT usFbDiv; // feedback divider1842UCHAR ucPostDiv; // post divider1843UCHAR ucFracFbDiv; // fractional feedback divider1844UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL21845UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER1846UCHAR ucCRTC; // Which CRTC uses this Ppll1847UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog1848}PIXEL_CLOCK_PARAMETERS_V2;18491850//Major revision=1., Minor revision=3, structure/definition change1851//ucEncoderMode:1852//ATOM_ENCODER_MODE_DP1853//ATOM_ENOCDER_MODE_LVDS1854//ATOM_ENOCDER_MODE_DVI1855//ATOM_ENOCDER_MODE_HDMI1856//ATOM_ENOCDER_MODE_SDVO1857//ATOM_ENCODER_MODE_TV 131858//ATOM_ENCODER_MODE_CV 141859//ATOM_ENCODER_MODE_CRT 1518601861//ucDVOConfig1862//#define DVO_ENCODER_CONFIG_RATE_SEL 0x011863//#define DVO_ENCODER_CONFIG_DDR_SPEED 0x001864//#define DVO_ENCODER_CONFIG_SDR_SPEED 0x011865//#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c1866//#define DVO_ENCODER_CONFIG_LOW12BIT 0x001867//#define DVO_ENCODER_CONFIG_UPPER12BIT 0x041868//#define DVO_ENCODER_CONFIG_24BIT 0x0818691870//ucMiscInfo: also changed, see below1871#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x011872#define PIXEL_CLOCK_MISC_VGA_MODE 0x021873#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x041874#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x001875#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x041876#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x081877#define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x101878// V1.4 for RoadRunner1879#define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x101880#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20188118821883typedef struct _PIXEL_CLOCK_PARAMETERS_V31884{1885USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)1886// 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.1887USHORT usRefDiv; // Reference divider1888USHORT usFbDiv; // feedback divider1889UCHAR ucPostDiv; // post divider1890UCHAR ucFracFbDiv; // fractional feedback divider1891UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL21892UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h1893union1894{1895UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/1896UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit1897};1898UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel1899// bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source1900// bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider1901}PIXEL_CLOCK_PARAMETERS_V3;19021903#define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V21904#define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST190519061907typedef struct _PIXEL_CLOCK_PARAMETERS_V51908{1909UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to1910// drive the pixel clock. not used for DCPLL case.1911union{1912UCHAR ucReserved;1913UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed.1914};1915USHORT usPixelClock; // target the pixel clock to drive the CRTC timing1916// 0 means disable PPLL/DCPLL.1917USHORT usFbDiv; // feedback divider integer part.1918UCHAR ucPostDiv; // post divider.1919UCHAR ucRefDiv; // Reference divider1920UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL1921UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,1922// indicate which graphic encoder will be used.1923UCHAR ucEncoderMode; // Encoder mode:1924UCHAR ucMiscInfo; // bit[0]= Force program PPLL1925// bit[1]= when VGA timing is used.1926// bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp1927// bit[4]= RefClock source for PPLL.1928// =0: XTLAIN( default mode )1929// =1: other external clock source, which is pre-defined1930// by VBIOS depend on the feature required.1931// bit[7:5]: reserved.1932ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )19331934}PIXEL_CLOCK_PARAMETERS_V5;19351936#define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x011937#define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x021938#define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c1939#define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x001940#define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x041941#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x081942#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x1019431944typedef struct _CRTC_PIXEL_CLOCK_FREQ1945{1946#if ATOM_BIG_ENDIAN1947ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to1948// drive the pixel clock. not used for DCPLL case.1949ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.1950// 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.1951#else1952ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.1953// 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.1954ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to1955// drive the pixel clock. not used for DCPLL case.1956#endif1957}CRTC_PIXEL_CLOCK_FREQ;19581959typedef struct _PIXEL_CLOCK_PARAMETERS_V61960{1961union{1962CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency1963ULONG ulDispEngClkFreq; // dispclk frequency1964};1965USHORT usFbDiv; // feedback divider integer part.1966UCHAR ucPostDiv; // post divider.1967UCHAR ucRefDiv; // Reference divider1968UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL1969UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,1970// indicate which graphic encoder will be used.1971UCHAR ucEncoderMode; // Encoder mode:1972UCHAR ucMiscInfo; // bit[0]= Force program PPLL1973// bit[1]= when VGA timing is used.1974// bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp1975// bit[4]= RefClock source for PPLL.1976// =0: XTLAIN( default mode )1977// =1: other external clock source, which is pre-defined1978// by VBIOS depend on the feature required.1979// bit[7:5]: reserved.1980ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )19811982}PIXEL_CLOCK_PARAMETERS_V6;19831984#define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x011985#define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x021986#define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c1987#define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x001988#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x041989#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct definition for 36bpp should be 2 for 36bpp(2:1)1990#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x081991#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct definition for 30bpp should be 1 for 36bpp(5:4)1992#define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c1993#define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x101994#define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x401995#define PIXEL_CLOCK_V6_MISC_DPREFCLK_BYPASS 0x4019961997typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V21998{1999PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput;2000}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2;20012002typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V22003{2004UCHAR ucStatus;2005UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock2006UCHAR ucReserved[2];2007}GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2;20082009typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V32010{2011PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput;2012}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3;20132014typedef struct _PIXEL_CLOCK_PARAMETERS_V72015{2016ULONG ulPixelClock; // target the pixel clock to drive the CRTC timing in unit of 100Hz.20172018UCHAR ucPpll; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL02019UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,2020// indicate which graphic encoder will be used.2021UCHAR ucEncoderMode; // Encoder mode:2022UCHAR ucMiscInfo; // bit[0]= Force program PLL for pixclk2023// bit[1]= Force program PHY PLL only ( internally used by VBIOS only in DP case which PHYPLL is programmed for SYMCLK, not Pixclk )2024// bit[5:4]= RefClock source for PPLL.2025// =0: XTLAIN( default mode )2026// =1: pcie2027// =2: GENLK2028UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to2029UCHAR ucDeepColorRatio; // HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:36bpp2030UCHAR ucReserved[2];2031ULONG ulReserved;2032}PIXEL_CLOCK_PARAMETERS_V7;20332034//ucMiscInfo2035#define PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL 0x012036#define PIXEL_CLOCK_V7_MISC_PROG_PHYPLL 0x022037#define PIXEL_CLOCK_V7_MISC_YUV420_MODE 0x042038#define PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN 0x082039#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC 0x302040#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN 0x002041#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE 0x102042#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK 0x2020432044//ucDeepColorRatio2045#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO2046#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:42047#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:22048#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:120492050// SetDCEClockTable input parameter for DCE11.12051typedef struct _SET_DCE_CLOCK_PARAMETERS_V1_12052{2053ULONG ulDISPClkFreq; // target DISPCLK frquency in unit of 10kHz, return real DISPCLK frequency. when ucFlag[1]=1, in unit of 100Hz.2054UCHAR ucFlag; // bit0=1: DPREFCLK bypass DFS bit0=0: DPREFCLK not bypass DFS2055UCHAR ucCrtc; // use when enable DCCG pixel clock ucFlag[1]=12056UCHAR ucPpllId; // use when enable DCCG pixel clock ucFlag[1]=12057UCHAR ucDeepColorRatio; // use when enable DCCG pixel clock ucFlag[1]=12058}SET_DCE_CLOCK_PARAMETERS_V1_1;205920602061typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V1_12062{2063SET_DCE_CLOCK_PARAMETERS_V1_1 asParam;2064ULONG ulReserved[2];2065}SET_DCE_CLOCK_PS_ALLOCATION_V1_1;20662067//SET_DCE_CLOCK_PARAMETERS_V1_1.ucFlag2068#define SET_DCE_CLOCK_FLAG_GEN_DPREFCLK 0x012069#define SET_DCE_CLOCK_FLAG_DPREFCLK_BYPASS 0x012070#define SET_DCE_CLOCK_FLAG_ENABLE_PIXCLK 0x0220712072// SetDCEClockTable input parameter for DCE11.2( POLARIS10 and POLARIS11 ) and above2073typedef struct _SET_DCE_CLOCK_PARAMETERS_V2_12074{2075ULONG ulDCEClkFreq; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.2076UCHAR ucDCEClkType; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK2077UCHAR ucDCEClkSrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx2078UCHAR ucDCEClkFlag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )2079UCHAR ucCRTC; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK2080}SET_DCE_CLOCK_PARAMETERS_V2_1;20812082//ucDCEClkType2083#define DCE_CLOCK_TYPE_DISPCLK 02084#define DCE_CLOCK_TYPE_DPREFCLK 12085#define DCE_CLOCK_TYPE_PIXELCLK 2 // used by VBIOS internally, called by SetPixelClockTable20862087//ucDCEClkFlag when ucDCEClkType == DPREFCLK2088#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK 0x032089#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA 0x002090#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK 0x012091#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE 0x022092#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN 0x0320932094//ucDCEClkFlag when ucDCEClkType == PIXCLK2095#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK 0x032096#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO2097#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:42098#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:22099#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:12100#define DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE 0x0421012102typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V2_12103{2104SET_DCE_CLOCK_PARAMETERS_V2_1 asParam;2105ULONG ulReserved[2];2106}SET_DCE_CLOCK_PS_ALLOCATION_V2_1;2107210821092110/****************************************************************************/2111// Structures used by AdjustDisplayPllTable2112/****************************************************************************/2113typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS2114{2115USHORT usPixelClock;2116UCHAR ucTransmitterID;2117UCHAR ucEncodeMode;2118union2119{2120UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit2121UCHAR ucConfig; //if none DVO, not defined yet2122};2123UCHAR ucReserved[3];2124}ADJUST_DISPLAY_PLL_PARAMETERS;21252126#define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x102127#define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS21282129typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V32130{2131USHORT usPixelClock; // target pixel clock2132UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h2133UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI2134UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX2135UCHAR ucExtTransmitterID; // external encoder id.2136UCHAR ucReserved[2];2137}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3;21382139// usDispPllConfig v1.2 for RoadRunner2140#define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO2141#define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO2142#define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO2143#define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO2144#define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO2145#define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO2146#define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO2147#define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS2148#define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI2149#define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS215021512152typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V32153{2154ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc2155UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )2156UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider2157UCHAR ucReserved[2];2158}ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3;21592160typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V32161{2162union2163{2164ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput;2165ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput;2166};2167} ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3;21682169/****************************************************************************/2170// Structures used by EnableYUVTable2171/****************************************************************************/2172typedef struct _ENABLE_YUV_PARAMETERS2173{2174UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)2175UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format2176UCHAR ucPadding[2];2177}ENABLE_YUV_PARAMETERS;2178#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS21792180/****************************************************************************/2181// Structures used by GetMemoryClockTable2182/****************************************************************************/2183typedef struct _GET_MEMORY_CLOCK_PARAMETERS2184{2185ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit2186} GET_MEMORY_CLOCK_PARAMETERS;2187#define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS21882189/****************************************************************************/2190// Structures used by GetEngineClockTable2191/****************************************************************************/2192typedef struct _GET_ENGINE_CLOCK_PARAMETERS2193{2194ULONG ulReturnEngineClock; // current engine speed in 10KHz unit2195} GET_ENGINE_CLOCK_PARAMETERS;2196#define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS21972198/****************************************************************************/2199// Following Structures and constant may be obsolete2200/****************************************************************************/2201//Maxium 8 bytes,the data read in will be placed in the parameter space.2202//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed2203typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS2204{2205USHORT usPrescale; //Ratio between Engine clock and I2C clock2206USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID2207USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status2208//WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte2209UCHAR ucSlaveAddr; //Read from which slave2210UCHAR ucLineNumber; //Read from which HW assisted line2211}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS;2212#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS221322142215#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 02216#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 12217#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 22218#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 32219#define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 422202221typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS2222{2223USHORT usPrescale; //Ratio between Engine clock and I2C clock2224USHORT usByteOffset; //Write to which byte2225//Upper portion of usByteOffset is Format of data2226//1bytePS+offsetPS2227//2bytesPS+offsetPS2228//blockID+offsetPS2229//blockID+offsetID2230//blockID+counterID+offsetID2231UCHAR ucData; //PS data12232UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data22233UCHAR ucSlaveAddr; //Write to which slave2234UCHAR ucLineNumber; //Write from which HW assisted line2235}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;22362237#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS22382239typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS2240{2241USHORT usPrescale; //Ratio between Engine clock and I2C clock2242UCHAR ucSlaveAddr; //Write to which slave2243UCHAR ucLineNumber; //Write from which HW assisted line2244}SET_UP_HW_I2C_DATA_PARAMETERS;22452246/**************************************************************************/2247#define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS224822492250/****************************************************************************/2251// Structures used by PowerConnectorDetectionTable2252/****************************************************************************/2253typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS2254{2255UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected2256UCHAR ucPwrBehaviorId;2257USHORT usPwrBudget; //how much power currently boot to in unit of watt2258}POWER_CONNECTOR_DETECTION_PARAMETERS;22592260typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION2261{2262UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected2263UCHAR ucReserved;2264USHORT usPwrBudget; //how much power currently boot to in unit of watt2265WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;2266}POWER_CONNECTOR_DETECTION_PS_ALLOCATION;226722682269/****************************LVDS SS Command Table Definitions**********************/22702271/****************************************************************************/2272// Structures used by EnableSpreadSpectrumOnPPLLTable2273/****************************************************************************/2274typedef struct _ENABLE_LVDS_SS_PARAMETERS2275{2276USHORT usSpreadSpectrumPercentage;2277UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD2278UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY2279UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE2280UCHAR ucPadding[3];2281}ENABLE_LVDS_SS_PARAMETERS;22822283//ucTableFormatRevision=1,ucTableContentRevision=22284typedef struct _ENABLE_LVDS_SS_PARAMETERS_V22285{2286USHORT usSpreadSpectrumPercentage;2287UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD2288UCHAR ucSpreadSpectrumStep; //2289UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE2290UCHAR ucSpreadSpectrumDelay;2291UCHAR ucSpreadSpectrumRange;2292UCHAR ucPadding;2293}ENABLE_LVDS_SS_PARAMETERS_V2;22942295//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.2296typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL2297{2298USHORT usSpreadSpectrumPercentage;2299UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD2300UCHAR ucSpreadSpectrumStep; //2301UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE2302UCHAR ucSpreadSpectrumDelay;2303UCHAR ucSpreadSpectrumRange;2304UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL22305}ENABLE_SPREAD_SPECTRUM_ON_PPLL;23062307typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V22308{2309USHORT usSpreadSpectrumPercentage;2310UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.2311// Bit[1]: 1-Ext. 0-Int.2312// Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL2313// Bits[7:4] reserved2314UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE2315USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]2316USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC2317}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2;23182319#define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x002320#define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x012321#define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x022322#define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c2323#define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x002324#define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x042325#define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x082326#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF2327#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 02328#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F002329#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 823302331// Used by DCE5.02332typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V32333{2334USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.02335UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.2336// Bit[1]: 1-Ext. 0-Int.2337// Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL2338// Bits[7:4] reserved2339UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE2340USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]2341USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC2342}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3;234323442345#define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x002346#define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x012347#define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x022348#define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c2349#define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x002350#define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x042351#define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x082352#define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL2353#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF2354#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 02355#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F002356#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 823572358#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL23592360typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION2361{2362PIXEL_CLOCK_PARAMETERS sPCLKInput;2363ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion2364}SET_PIXEL_CLOCK_PS_ALLOCATION;2365236623672368#define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION23692370/****************************************************************************/2371// Structures used by ###2372/****************************************************************************/2373typedef struct _MEMORY_TRAINING_PARAMETERS2374{2375ULONG ulTargetMemoryClock; //In 10Khz unit2376}MEMORY_TRAINING_PARAMETERS;2377#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS237823792380typedef struct _MEMORY_TRAINING_PARAMETERS_V1_22381{2382USHORT usMemTrainingMode;2383USHORT usReserved;2384}MEMORY_TRAINING_PARAMETERS_V1_2;23852386//usMemTrainingMode2387#define NORMAL_MEMORY_TRAINING_MODE 02388#define ENTER_DRAM_SELFREFRESH_MODE 12389#define EXIT_DRAM_SELFRESH_MODE 223902391/****************************LVDS and other encoder command table definitions **********************/239223932394/****************************************************************************/2395// Structures used by LVDSEncoderControlTable (Before DEC30)2396// LVTMAEncoderControlTable (Before DEC30)2397// TMDSAEncoderControlTable (Before DEC30)2398/****************************************************************************/2399typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS2400{2401USHORT usPixelClock; // in 10KHz; for bios convenient2402UCHAR ucMisc; // bit0=0: Enable single link2403// =1: Enable dual link2404// Bit1=0: 666RGB2405// =1: 888RGB2406UCHAR ucAction; // 0: turn off encoder2407// 1: setup and turn on encoder2408}LVDS_ENCODER_CONTROL_PARAMETERS;24092410#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS24112412#define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS2413#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS24142415#define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS2416#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS24172418//ucTableFormatRevision=1,ucTableContentRevision=22419typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V22420{2421USHORT usPixelClock; // in 10KHz; for bios convenient2422UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below2423UCHAR ucAction; // 0: turn off encoder2424// 1: setup and turn on encoder2425UCHAR ucTruncate; // bit0=0: Disable truncate2426// =1: Enable truncate2427// bit4=0: 666RGB2428// =1: 888RGB2429UCHAR ucSpatial; // bit0=0: Disable spatial dithering2430// =1: Enable spatial dithering2431// bit4=0: 666RGB2432// =1: 888RGB2433UCHAR ucTemporal; // bit0=0: Disable temporal dithering2434// =1: Enable temporal dithering2435// bit4=0: 666RGB2436// =1: 888RGB2437// bit5=0: Gray level 22438// =1: Gray level 42439UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E2440// =1: 25FRC_SEL pattern F2441// bit6:5=0: 50FRC_SEL pattern A2442// =1: 50FRC_SEL pattern B2443// =2: 50FRC_SEL pattern C2444// =3: 50FRC_SEL pattern D2445// bit7=0: 75FRC_SEL pattern E2446// =1: 75FRC_SEL pattern F2447}LVDS_ENCODER_CONTROL_PARAMETERS_V2;24482449#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V224502451#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V22452#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V224532454#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V22455#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2245624572458#define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V22459#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V324602461#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V32462#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V324632464#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V32465#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V324662467/****************************************************************************/2468// Structures used by ###2469/****************************************************************************/2470typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS2471{2472UCHAR ucEnable; // Enable or Disable External TMDS encoder2473UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}2474UCHAR ucPadding[2];2475}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;24762477typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION2478{2479ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder;2480WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion2481}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;24822483#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V22484typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V22485{2486ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder;2487WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion2488}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;24892490typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION2491{2492DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder;2493WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;2494}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION;24952496/****************************************************************************/2497// Structures used by DVOEncoderControlTable2498/****************************************************************************/2499//ucTableFormatRevision=1,ucTableContentRevision=32500//ucDVOConfig:2501#define DVO_ENCODER_CONFIG_RATE_SEL 0x012502#define DVO_ENCODER_CONFIG_DDR_SPEED 0x002503#define DVO_ENCODER_CONFIG_SDR_SPEED 0x012504#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c2505#define DVO_ENCODER_CONFIG_LOW12BIT 0x002506#define DVO_ENCODER_CONFIG_UPPER12BIT 0x042507#define DVO_ENCODER_CONFIG_24BIT 0x0825082509typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V32510{2511USHORT usPixelClock;2512UCHAR ucDVOConfig;2513UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT2514UCHAR ucReseved[4];2515}DVO_ENCODER_CONTROL_PARAMETERS_V3;2516#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V325172518typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_42519{2520USHORT usPixelClock;2521UCHAR ucDVOConfig;2522UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT2523UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR2524UCHAR ucReseved[3];2525}DVO_ENCODER_CONTROL_PARAMETERS_V1_4;2526#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 DVO_ENCODER_CONTROL_PARAMETERS_V1_4252725282529//ucTableFormatRevision=12530//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for2531// bit1=0: non-coherent mode2532// =1: coherent mode25332534//==========================================================================================2535//Only change is here next time when changing encoder parameter definitions again!2536#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V32537#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST25382539#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V32540#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST25412542#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V32543#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST25442545#define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS2546#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION25472548//==========================================================================================2549#define PANEL_ENCODER_MISC_DUAL 0x012550#define PANEL_ENCODER_MISC_COHERENT 0x022551#define PANEL_ENCODER_MISC_TMDS_LINKB 0x042552#define PANEL_ENCODER_MISC_HDMI_TYPE 0x0825532554#define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE2555#define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE2556#define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1)25572558#define PANEL_ENCODER_TRUNCATE_EN 0x012559#define PANEL_ENCODER_TRUNCATE_DEPTH 0x102560#define PANEL_ENCODER_SPATIAL_DITHER_EN 0x012561#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x102562#define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x012563#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x102564#define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x202565#define PANEL_ENCODER_25FRC_MASK 0x102566#define PANEL_ENCODER_25FRC_E 0x002567#define PANEL_ENCODER_25FRC_F 0x102568#define PANEL_ENCODER_50FRC_MASK 0x602569#define PANEL_ENCODER_50FRC_A 0x002570#define PANEL_ENCODER_50FRC_B 0x202571#define PANEL_ENCODER_50FRC_C 0x402572#define PANEL_ENCODER_50FRC_D 0x602573#define PANEL_ENCODER_75FRC_MASK 0x802574#define PANEL_ENCODER_75FRC_E 0x002575#define PANEL_ENCODER_75FRC_F 0x8025762577/****************************************************************************/2578// Structures used by SetVoltageTable2579/****************************************************************************/2580#define SET_VOLTAGE_TYPE_ASIC_VDDC 12581#define SET_VOLTAGE_TYPE_ASIC_MVDDC 22582#define SET_VOLTAGE_TYPE_ASIC_MVDDQ 32583#define SET_VOLTAGE_TYPE_ASIC_VDDCI 42584#define SET_VOLTAGE_INIT_MODE 52585#define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic25862587#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x12588#define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x22589#define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x425902591#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x02592#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x12593#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x225942595typedef struct _SET_VOLTAGE_PARAMETERS2596{2597UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ2598UCHAR ucVoltageMode; // To set all, to set source A or source B or ...2599UCHAR ucVoltageIndex; // An index to tell which voltage level2600UCHAR ucReserved;2601}SET_VOLTAGE_PARAMETERS;26022603typedef struct _SET_VOLTAGE_PARAMETERS_V22604{2605UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ2606UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode2607USHORT usVoltageLevel; // real voltage level2608}SET_VOLTAGE_PARAMETERS_V2;26092610// used by both SetVoltageTable v1.3 and v1.42611typedef struct _SET_VOLTAGE_PARAMETERS_V1_32612{2613UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI2614UCHAR ucVoltageMode; // Indicate action: Set voltage level2615USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. )2616}SET_VOLTAGE_PARAMETERS_V1_3;26172618//ucVoltageType2619#define VOLTAGE_TYPE_VDDC 12620#define VOLTAGE_TYPE_MVDDC 22621#define VOLTAGE_TYPE_MVDDQ 32622#define VOLTAGE_TYPE_VDDCI 42623#define VOLTAGE_TYPE_VDDGFX 52624#define VOLTAGE_TYPE_PCC 62625#define VOLTAGE_TYPE_MVPP 72626#define VOLTAGE_TYPE_LEDDPM 82627#define VOLTAGE_TYPE_PCC_MVDD 92628#define VOLTAGE_TYPE_PCIE_VDDC 102629#define VOLTAGE_TYPE_PCIE_VDDR 1126302631#define VOLTAGE_TYPE_GENERIC_I2C_1 0x112632#define VOLTAGE_TYPE_GENERIC_I2C_2 0x122633#define VOLTAGE_TYPE_GENERIC_I2C_3 0x132634#define VOLTAGE_TYPE_GENERIC_I2C_4 0x142635#define VOLTAGE_TYPE_GENERIC_I2C_5 0x152636#define VOLTAGE_TYPE_GENERIC_I2C_6 0x162637#define VOLTAGE_TYPE_GENERIC_I2C_7 0x172638#define VOLTAGE_TYPE_GENERIC_I2C_8 0x182639#define VOLTAGE_TYPE_GENERIC_I2C_9 0x192640#define VOLTAGE_TYPE_GENERIC_I2C_10 0x1A26412642//SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode2643#define ATOM_SET_VOLTAGE 0 //Set voltage Level2644#define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator2645#define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase, only for SVID/PVID regulator2646#define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used from SetVoltageTable v1.32647#define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.42648#define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.426492650// define vitual voltage id in usVoltageLevel2651#define ATOM_VIRTUAL_VOLTAGE_ID0 0xff012652#define ATOM_VIRTUAL_VOLTAGE_ID1 0xff022653#define ATOM_VIRTUAL_VOLTAGE_ID2 0xff032654#define ATOM_VIRTUAL_VOLTAGE_ID3 0xff042655#define ATOM_VIRTUAL_VOLTAGE_ID4 0xff052656#define ATOM_VIRTUAL_VOLTAGE_ID5 0xff062657#define ATOM_VIRTUAL_VOLTAGE_ID6 0xff072658#define ATOM_VIRTUAL_VOLTAGE_ID7 0xff0826592660typedef struct _SET_VOLTAGE_PS_ALLOCATION2661{2662SET_VOLTAGE_PARAMETERS sASICSetVoltage;2663WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;2664}SET_VOLTAGE_PS_ALLOCATION;26652666// New Added from SI for GetVoltageInfoTable, input parameter structure2667typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_12668{2669UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI2670UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info2671USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id2672ULONG ulReserved;2673}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1;26742675// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID2676typedef struct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_12677{2678ULONG ulVotlageGpioState;2679ULONG ulVoltageGPioMask;2680}GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;26812682// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID2683typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_12684{2685USHORT usVoltageLevel;2686USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator2687ULONG ulReseved;2688}GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;26892690// GetVoltageInfo v1.1 ucVoltageMode2691#define ATOM_GET_VOLTAGE_VID 0x002692#define ATOM_GET_VOTLAGE_INIT_SEQ 0x032693#define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x042694#define ATOM_GET_VOLTAGE_SVID2 0x07 //Get SVI2 Regulator Info26952696// for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state2697#define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x102698// for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state2699#define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x1127002701#define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x122702#define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13270327042705// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure2706typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_22707{2708UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI2709UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info2710USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id2711ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table2712}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2;27132714// New in GetVoltageInfo v1.2 ucVoltageMode2715#define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x0927162717// New Added from CI Hawaii for EVV feature2718typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_22719{2720USHORT usVoltageLevel; // real voltage level in unit of mv2721USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator2722USHORT usTDP_Current; // TDP_Current in unit of 0.01A2723USHORT usTDP_Power; // TDP_Current in unit of 0.1W2724}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2;272527262727// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure2728typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_32729{2730UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI2731UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info2732USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id2733ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table2734ULONG ulReserved[3];2735}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3;27362737// New Added from CI Hawaii for EVV feature2738typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_32739{2740ULONG ulVoltageLevel; // real voltage level in unit of 0.01mv2741ULONG ulReserved[4];2742}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3;274327442745/****************************************************************************/2746// Structures used by GetSMUClockInfo2747/****************************************************************************/2748typedef struct _GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_12749{2750ULONG ulDfsPllOutputFreq:24;2751ULONG ucDfsDivider:8;2752}GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1;27532754typedef struct _GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_12755{2756ULONG ulDfsOutputFreq;2757}GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1;27582759/****************************************************************************/2760// Structures used by TVEncoderControlTable2761/****************************************************************************/2762typedef struct _TV_ENCODER_CONTROL_PARAMETERS2763{2764USHORT usPixelClock; // in 10KHz; for bios convenient2765UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..."2766UCHAR ucAction; // 0: turn off encoder2767// 1: setup and turn on encoder2768}TV_ENCODER_CONTROL_PARAMETERS;27692770typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION2771{2772TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;2773WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one2774}TV_ENCODER_CONTROL_PS_ALLOCATION;27752776//==============================Data Table Portion====================================277727782779/****************************************************************************/2780// Structure used in Data.mtb2781/****************************************************************************/2782typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES2783{2784USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position!2785USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios2786USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios2787USHORT StandardVESA_Timing; // Only used by Bios2788USHORT FirmwareInfo; // Shared by various SW components,latest version 1.42789USHORT PaletteData; // Only used by BIOS2790USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info2791USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.12792USHORT SMU_Info; // Shared by various SW components,latest version 1.12793USHORT SupportedDevicesInfo; // Will be obsolete from R6002794USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R6002795USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R6002796USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.12797USHORT VESA_ToInternalModeLUT; // Only used by Bios2798USHORT GFX_Info; // Shared by various SW components,latest version 2.1 will be used from R6002799USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R6002800USHORT GPUVirtualizationInfo; // Will be obsolete from R6002801USHORT SaveRestoreInfo; // Only used by Bios2802USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info2803USHORT OemInfo; // Defined and used by external SW, should be obsolete soon2804USHORT XTMDS_Info; // Will be obsolete from R6002805USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used2806USHORT Object_Header; // Shared by various SW components,latest version 1.12807USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!!2808USHORT MC_InitParameter; // Only used by command table2809USHORT ASIC_VDDC_Info; // Will be obsolete from R6002810USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info"2811USHORT TV_VideoMode; // Only used by command table2812USHORT VRAM_Info; // Only used by command table, latest version 1.32813USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.12814USHORT IntegratedSystemInfo; // Shared by various SW components2815USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R6002816USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.12817USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.12818USHORT ServiceInfo;2819}ATOM_MASTER_LIST_OF_DATA_TABLES;28202821typedef struct _ATOM_MASTER_DATA_TABLE2822{2823ATOM_COMMON_TABLE_HEADER sHeader;2824ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables;2825}ATOM_MASTER_DATA_TABLE;28262827// For backward compatible2828#define LVDS_Info LCD_Info2829#define DAC_Info PaletteData2830#define TMDS_Info DIGTransmitterInfo2831#define CompassionateData GPUVirtualizationInfo2832#define AnalogTV_Info SMU_Info2833#define ComponentVideoInfo GFX_Info28342835/****************************************************************************/2836// Structure used in MultimediaCapabilityInfoTable2837/****************************************************************************/2838typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO2839{2840ATOM_COMMON_TABLE_HEADER sHeader;2841ULONG ulSignature; // HW info table signature string "$ATI"2842UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)2843UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)2844UCHAR ucVideoPortInfo; // Provides the video port capabilities2845UCHAR ucHostPortInfo; // Provides host port configuration information2846}ATOM_MULTIMEDIA_CAPABILITY_INFO;284728482849/****************************************************************************/2850// Structure used in MultimediaConfigInfoTable2851/****************************************************************************/2852typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO2853{2854ATOM_COMMON_TABLE_HEADER sHeader;2855ULONG ulSignature; // MM info table signature sting "$MMT"2856UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)2857UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5)2858UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting2859UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)2860UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)2861UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)2862UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3)2863UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)2864UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)2865UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)2866UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)2867UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)2868}ATOM_MULTIMEDIA_CONFIG_INFO;286928702871/****************************************************************************/2872// Structures used in FirmwareInfoTable2873/****************************************************************************/28742875// usBIOSCapability Defintion:2876// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;2877// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;2878// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;2879// Others: Reserved2880#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x00012881#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x00022882#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x00042883#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable.2884#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable.2885#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x00202886#define ATOM_BIOS_INFO_WMI_SUPPORT 0x00402887#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x00802888#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x01002889#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E002890#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x20002891#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x40002892#define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip2893#define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip289428952896#ifndef _H2INC28972898//Please don't add or expand this bitfield structure below, this one will retire soon.!2899typedef struct _ATOM_FIRMWARE_CAPABILITY2900{2901#if ATOM_BIG_ENDIAN2902USHORT Reserved:1;2903USHORT SCL2Redefined:1;2904USHORT PostWithoutModeSet:1;2905USHORT HyperMemory_Size:4;2906USHORT HyperMemory_Support:1;2907USHORT PPMode_Assigned:1;2908USHORT WMI_SUPPORT:1;2909USHORT GPUControlsBL:1;2910USHORT EngineClockSS_Support:1;2911USHORT MemoryClockSS_Support:1;2912USHORT ExtendedDesktopSupport:1;2913USHORT DualCRTC_Support:1;2914USHORT FirmwarePosted:1;2915#else2916USHORT FirmwarePosted:1;2917USHORT DualCRTC_Support:1;2918USHORT ExtendedDesktopSupport:1;2919USHORT MemoryClockSS_Support:1;2920USHORT EngineClockSS_Support:1;2921USHORT GPUControlsBL:1;2922USHORT WMI_SUPPORT:1;2923USHORT PPMode_Assigned:1;2924USHORT HyperMemory_Support:1;2925USHORT HyperMemory_Size:4;2926USHORT PostWithoutModeSet:1;2927USHORT SCL2Redefined:1;2928USHORT Reserved:1;2929#endif2930}ATOM_FIRMWARE_CAPABILITY;29312932typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS2933{2934ATOM_FIRMWARE_CAPABILITY sbfAccess;2935USHORT susAccess;2936}ATOM_FIRMWARE_CAPABILITY_ACCESS;29372938#else29392940typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS2941{2942USHORT susAccess;2943}ATOM_FIRMWARE_CAPABILITY_ACCESS;29442945#endif29462947typedef struct _ATOM_FIRMWARE_INFO2948{2949ATOM_COMMON_TABLE_HEADER sHeader;2950ULONG ulFirmwareRevision;2951ULONG ulDefaultEngineClock; //In 10Khz unit2952ULONG ulDefaultMemoryClock; //In 10Khz unit2953ULONG ulDriverTargetEngineClock; //In 10Khz unit2954ULONG ulDriverTargetMemoryClock; //In 10Khz unit2955ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit2956ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit2957ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit2958ULONG ulASICMaxEngineClock; //In 10Khz unit2959ULONG ulASICMaxMemoryClock; //In 10Khz unit2960UCHAR ucASICMaxTemperature;2961UCHAR ucPadding[3]; //Don't use them2962ULONG aulReservedForBIOS[3]; //Don't use them2963USHORT usMinEngineClockPLL_Input; //In 10Khz unit2964USHORT usMaxEngineClockPLL_Input; //In 10Khz unit2965USHORT usMinEngineClockPLL_Output; //In 10Khz unit2966USHORT usMinMemoryClockPLL_Input; //In 10Khz unit2967USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit2968USHORT usMinMemoryClockPLL_Output; //In 10Khz unit2969USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk2970USHORT usMinPixelClockPLL_Input; //In 10Khz unit2971USHORT usMaxPixelClockPLL_Input; //In 10Khz unit2972USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!!2973ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;2974USHORT usReferenceClock; //In 10Khz unit2975USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit2976UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit2977UCHAR ucDesign_ID; //Indicate what is the board design2978UCHAR ucMemoryModule_ID; //Indicate what is the board design2979}ATOM_FIRMWARE_INFO;29802981typedef struct _ATOM_FIRMWARE_INFO_V1_22982{2983ATOM_COMMON_TABLE_HEADER sHeader;2984ULONG ulFirmwareRevision;2985ULONG ulDefaultEngineClock; //In 10Khz unit2986ULONG ulDefaultMemoryClock; //In 10Khz unit2987ULONG ulDriverTargetEngineClock; //In 10Khz unit2988ULONG ulDriverTargetMemoryClock; //In 10Khz unit2989ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit2990ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit2991ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit2992ULONG ulASICMaxEngineClock; //In 10Khz unit2993ULONG ulASICMaxMemoryClock; //In 10Khz unit2994UCHAR ucASICMaxTemperature;2995UCHAR ucMinAllowedBL_Level;2996UCHAR ucPadding[2]; //Don't use them2997ULONG aulReservedForBIOS[2]; //Don't use them2998ULONG ulMinPixelClockPLL_Output; //In 10Khz unit2999USHORT usMinEngineClockPLL_Input; //In 10Khz unit3000USHORT usMaxEngineClockPLL_Input; //In 10Khz unit3001USHORT usMinEngineClockPLL_Output; //In 10Khz unit3002USHORT usMinMemoryClockPLL_Input; //In 10Khz unit3003USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit3004USHORT usMinMemoryClockPLL_Output; //In 10Khz unit3005USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk3006USHORT usMinPixelClockPLL_Input; //In 10Khz unit3007USHORT usMaxPixelClockPLL_Input; //In 10Khz unit3008USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output3009ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;3010USHORT usReferenceClock; //In 10Khz unit3011USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit3012UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit3013UCHAR ucDesign_ID; //Indicate what is the board design3014UCHAR ucMemoryModule_ID; //Indicate what is the board design3015}ATOM_FIRMWARE_INFO_V1_2;30163017typedef struct _ATOM_FIRMWARE_INFO_V1_33018{3019ATOM_COMMON_TABLE_HEADER sHeader;3020ULONG ulFirmwareRevision;3021ULONG ulDefaultEngineClock; //In 10Khz unit3022ULONG ulDefaultMemoryClock; //In 10Khz unit3023ULONG ulDriverTargetEngineClock; //In 10Khz unit3024ULONG ulDriverTargetMemoryClock; //In 10Khz unit3025ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit3026ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit3027ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit3028ULONG ulASICMaxEngineClock; //In 10Khz unit3029ULONG ulASICMaxMemoryClock; //In 10Khz unit3030UCHAR ucASICMaxTemperature;3031UCHAR ucMinAllowedBL_Level;3032UCHAR ucPadding[2]; //Don't use them3033ULONG aulReservedForBIOS; //Don't use them3034ULONG ul3DAccelerationEngineClock;//In 10Khz unit3035ULONG ulMinPixelClockPLL_Output; //In 10Khz unit3036USHORT usMinEngineClockPLL_Input; //In 10Khz unit3037USHORT usMaxEngineClockPLL_Input; //In 10Khz unit3038USHORT usMinEngineClockPLL_Output; //In 10Khz unit3039USHORT usMinMemoryClockPLL_Input; //In 10Khz unit3040USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit3041USHORT usMinMemoryClockPLL_Output; //In 10Khz unit3042USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk3043USHORT usMinPixelClockPLL_Input; //In 10Khz unit3044USHORT usMaxPixelClockPLL_Input; //In 10Khz unit3045USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output3046ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;3047USHORT usReferenceClock; //In 10Khz unit3048USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit3049UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit3050UCHAR ucDesign_ID; //Indicate what is the board design3051UCHAR ucMemoryModule_ID; //Indicate what is the board design3052}ATOM_FIRMWARE_INFO_V1_3;30533054typedef struct _ATOM_FIRMWARE_INFO_V1_43055{3056ATOM_COMMON_TABLE_HEADER sHeader;3057ULONG ulFirmwareRevision;3058ULONG ulDefaultEngineClock; //In 10Khz unit3059ULONG ulDefaultMemoryClock; //In 10Khz unit3060ULONG ulDriverTargetEngineClock; //In 10Khz unit3061ULONG ulDriverTargetMemoryClock; //In 10Khz unit3062ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit3063ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit3064ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit3065ULONG ulASICMaxEngineClock; //In 10Khz unit3066ULONG ulASICMaxMemoryClock; //In 10Khz unit3067UCHAR ucASICMaxTemperature;3068UCHAR ucMinAllowedBL_Level;3069USHORT usBootUpVDDCVoltage; //In MV unit3070USHORT usLcdMinPixelClockPLL_Output; // In MHz unit3071USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit3072ULONG ul3DAccelerationEngineClock;//In 10Khz unit3073ULONG ulMinPixelClockPLL_Output; //In 10Khz unit3074USHORT usMinEngineClockPLL_Input; //In 10Khz unit3075USHORT usMaxEngineClockPLL_Input; //In 10Khz unit3076USHORT usMinEngineClockPLL_Output; //In 10Khz unit3077USHORT usMinMemoryClockPLL_Input; //In 10Khz unit3078USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit3079USHORT usMinMemoryClockPLL_Output; //In 10Khz unit3080USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk3081USHORT usMinPixelClockPLL_Input; //In 10Khz unit3082USHORT usMaxPixelClockPLL_Input; //In 10Khz unit3083USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output3084ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;3085USHORT usReferenceClock; //In 10Khz unit3086USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit3087UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit3088UCHAR ucDesign_ID; //Indicate what is the board design3089UCHAR ucMemoryModule_ID; //Indicate what is the board design3090}ATOM_FIRMWARE_INFO_V1_4;30913092//the structure below to be used from Cypress3093typedef struct _ATOM_FIRMWARE_INFO_V2_13094{3095ATOM_COMMON_TABLE_HEADER sHeader;3096ULONG ulFirmwareRevision;3097ULONG ulDefaultEngineClock; //In 10Khz unit3098ULONG ulDefaultMemoryClock; //In 10Khz unit3099ULONG ulReserved1;3100ULONG ulReserved2;3101ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit3102ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit3103ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit3104ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock3105ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit3106UCHAR ucReserved1; //Was ucASICMaxTemperature;3107UCHAR ucMinAllowedBL_Level;3108USHORT usBootUpVDDCVoltage; //In MV unit3109USHORT usLcdMinPixelClockPLL_Output; // In MHz unit3110USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit3111ULONG ulReserved4; //Was ulAsicMaximumVoltage3112ULONG ulMinPixelClockPLL_Output; //In 10Khz unit3113USHORT usMinEngineClockPLL_Input; //In 10Khz unit3114USHORT usMaxEngineClockPLL_Input; //In 10Khz unit3115USHORT usMinEngineClockPLL_Output; //In 10Khz unit3116USHORT usMinMemoryClockPLL_Input; //In 10Khz unit3117USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit3118USHORT usMinMemoryClockPLL_Output; //In 10Khz unit3119USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk3120USHORT usMinPixelClockPLL_Input; //In 10Khz unit3121USHORT usMaxPixelClockPLL_Input; //In 10Khz unit3122USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output3123ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;3124USHORT usCoreReferenceClock; //In 10Khz unit3125USHORT usMemoryReferenceClock; //In 10Khz unit3126USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock3127UCHAR ucMemoryModule_ID; //Indicate what is the board design3128UCHAR ucReserved4[3];31293130}ATOM_FIRMWARE_INFO_V2_1;31313132//the structure below to be used from NI3133//ucTableFormatRevision=23134//ucTableContentRevision=231353136typedef struct _PRODUCT_BRANDING3137{3138UCHAR ucEMBEDDED_CAP:2; // Bit[1:0] Embedded feature level3139UCHAR ucReserved:2; // Bit[3:2] Reserved3140UCHAR ucBRANDING_ID:4; // Bit[7:4] Branding ID3141}PRODUCT_BRANDING;31423143typedef struct _ATOM_FIRMWARE_INFO_V2_23144{3145ATOM_COMMON_TABLE_HEADER sHeader;3146ULONG ulFirmwareRevision;3147ULONG ulDefaultEngineClock; //In 10Khz unit3148ULONG ulDefaultMemoryClock; //In 10Khz unit3149ULONG ulSPLL_OutputFreq; //In 10Khz unit3150ULONG ulGPUPLL_OutputFreq; //In 10Khz unit3151ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*3152ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*3153ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit3154ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ?3155ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage.3156UCHAR ucReserved3; //Was ucASICMaxTemperature;3157UCHAR ucMinAllowedBL_Level;3158USHORT usBootUpVDDCVoltage; //In MV unit3159USHORT usLcdMinPixelClockPLL_Output; // In MHz unit3160USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit3161ULONG ulReserved4; //Was ulAsicMaximumVoltage3162ULONG ulMinPixelClockPLL_Output; //In 10Khz unit3163UCHAR ucRemoteDisplayConfig;3164UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input3165ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input3166ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output3167USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC3168USHORT usMinPixelClockPLL_Input; //In 10Khz unit3169USHORT usMaxPixelClockPLL_Input; //In 10Khz unit3170USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output;3171ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;3172USHORT usCoreReferenceClock; //In 10Khz unit3173USHORT usMemoryReferenceClock; //In 10Khz unit3174USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock3175UCHAR ucMemoryModule_ID; //Indicate what is the board design3176UCHAR ucCoolingSolution_ID; //0: Air cooling; 1: Liquid cooling ... [COOLING_SOLUTION]3177PRODUCT_BRANDING ucProductBranding; // Bit[7:4]ucBRANDING_ID: Branding ID, Bit[3:2]ucReserved: Reserved, Bit[1:0]ucEMBEDDED_CAP: Embedded feature level.3178UCHAR ucReserved9;3179USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output;3180USHORT usBootUpVDDGFXVoltage; //In unit of mv;3181ULONG ulReserved10[3]; // New added comparing to previous version3182}ATOM_FIRMWARE_INFO_V2_2;31833184#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2318531863187// definition of ucRemoteDisplayConfig3188#define REMOTE_DISPLAY_DISABLE 0x003189#define REMOTE_DISPLAY_ENABLE 0x0131903191/****************************************************************************/3192// Structures used in IntegratedSystemInfoTable3193/****************************************************************************/3194#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x23195#define IGP_CAP_FLAG_AC_CARD 0x43196#define IGP_CAP_FLAG_SDVO_CARD 0x83197#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x1031983199typedef struct _ATOM_INTEGRATED_SYSTEM_INFO3200{3201ATOM_COMMON_TABLE_HEADER sHeader;3202ULONG ulBootUpEngineClock; //in 10kHz unit3203ULONG ulBootUpMemoryClock; //in 10kHz unit3204ULONG ulMaxSystemMemoryClock; //in 10kHz unit3205ULONG ulMinSystemMemoryClock; //in 10kHz unit3206UCHAR ucNumberOfCyclesInPeriodHi;3207UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID.3208USHORT usReserved1;3209USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage3210USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage3211ULONG ulReserved[2];32123213USHORT usFSBClock; //In MHz unit3214USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable3215//Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card3216//Bit[4]==1: P/2 mode, ==0: P/1 mode3217USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal3218USHORT usK8MemoryClock; //in MHz unit3219USHORT usK8SyncStartDelay; //in 0.01 us unit3220USHORT usK8DataReturnTime; //in 0.01 us unit3221UCHAR ucMaxNBVoltage;3222UCHAR ucMinNBVoltage;3223UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved3224UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod3225UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime3226UCHAR ucHTLinkWidth; //16 bit vs. 8 bit3227UCHAR ucMaxNBVoltageHigh;3228UCHAR ucMinNBVoltageHigh;3229}ATOM_INTEGRATED_SYSTEM_INFO;32303231/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO3232ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock3233For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock3234ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 03235For AMD IGP,for now this can be 03236ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 03237For AMD IGP,for now this can be 032383239usFSBClock: For Intel IGP,it's FSB Freq3240For AMD IGP,it's HT Link Speed32413242usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 2003243usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation3244usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation32453246VC:Voltage Control3247ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.3248ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.32493250ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.3251ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 032523253ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.3254ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.325532563257usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.3258usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.3259*/326032613262/*3263The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST;3264Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need.3265The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.32663267SW components can access the IGP system infor structure in the same way as before3268*/326932703271typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V23272{3273ATOM_COMMON_TABLE_HEADER sHeader;3274ULONG ulBootUpEngineClock; //in 10kHz unit3275ULONG ulReserved1[2]; //must be 0x0 for the reserved3276ULONG ulBootUpUMAClock; //in 10kHz unit3277ULONG ulBootUpSidePortClock; //in 10kHz unit3278ULONG ulMinSidePortClock; //in 10kHz unit3279ULONG ulReserved2[6]; //must be 0x0 for the reserved3280ULONG ulSystemConfig; //see explanation below3281ULONG ulBootUpReqDisplayVector;3282ULONG ulOtherDisplayMisc;3283ULONG ulDDISlot1Config;3284ULONG ulDDISlot2Config;3285UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved3286UCHAR ucUMAChannelNumber;3287UCHAR ucDockingPinBit;3288UCHAR ucDockingPinPolarity;3289ULONG ulDockingPinCFGInfo;3290ULONG ulCPUCapInfo;3291USHORT usNumberOfCyclesInPeriod;3292USHORT usMaxNBVoltage;3293USHORT usMinNBVoltage;3294USHORT usBootUpNBVoltage;3295ULONG ulHTLinkFreq; //in 10Khz3296USHORT usMinHTLinkWidth;3297USHORT usMaxHTLinkWidth;3298USHORT usUMASyncStartDelay;3299USHORT usUMADataReturnTime;3300USHORT usLinkStatusZeroTime;3301USHORT usDACEfuse; //for storing badgap value (for RS880 only)3302ULONG ulHighVoltageHTLinkFreq; // in 10Khz3303ULONG ulLowVoltageHTLinkFreq; // in 10Khz3304USHORT usMaxUpStreamHTLinkWidth;3305USHORT usMaxDownStreamHTLinkWidth;3306USHORT usMinUpStreamHTLinkWidth;3307USHORT usMinDownStreamHTLinkWidth;3308USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW.3309USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.3310ULONG ulReserved3[96]; //must be 0x03311}ATOM_INTEGRATED_SYSTEM_INFO_V2;33123313/*3314ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;3315ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present3316ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock33173318ulSystemConfig:3319Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;3320Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state3321=0: system boots up at driver control state. Power state depends on PowerPlay table.3322Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.3323Bit[3]=1: Only one power state(Performance) will be supported.3324=0: Multiple power states supported from PowerPlay table.3325Bit[4]=1: CLMC is supported and enabled on current system.3326=0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface.3327Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement.3328=0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied.3329Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored.3330=0: Voltage settings is determined by powerplay table.3331Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue.3332=0: Enable CLMC as regular mode, CDLD and CILR will be enabled.3333Bit[8]=1: CDLF is supported and enabled on current system.3334=0: CDLF is not supported or enabled on current system.3335Bit[9]=1: DLL Shut Down feature is enabled on current system.3336=0: DLL Shut Down feature is not enabled or supported on current system.33373338ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.33393340ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;3341[7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition;33423343ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).3344[3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)3345[7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12)3346When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time.3347in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example:3348one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2.33493350[15:8] - Lane configuration attribute;3351[23:16]- Connector type, possible value:3352CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D3353CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D3354CONNECTOR_OBJECT_ID_HDMI_TYPE_A3355CONNECTOR_OBJECT_ID_DISPLAYPORT3356CONNECTOR_OBJECT_ID_eDP3357[31:24]- Reserved33583359ulDDISlot2Config: Same as Slot1.3360ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC.3361For IGP, Hypermemory is the only memory type showed in CCC.33623363ucUMAChannelNumber: how many channels for the UMA;33643365ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin3366ucDockingPinBit: which bit in this register to read the pin status;3367ucDockingPinPolarity:Polarity of the pin when docked;33683369ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x033703371usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.33723373usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.3374usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.3375GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=03376PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=13377GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE33783379usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.338033813382ulHTLinkFreq: Bootup HT link Frequency in 10Khz.3383usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth.3384If CDLW enabled, both upstream and downstream width should be the same during bootup.3385usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth.3386If CDLW enabled, both upstream and downstream width should be the same during bootup.33873388usUMASyncStartDelay: Memory access latency, required for watermark calculation3389usUMADataReturnTime: Memory access latency, required for watermark calculation3390usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us3391for Griffin or Greyhound. SBIOS needs to convert to actual time by:3392if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)3393if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)3394if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)3395if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us)33963397ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0.3398This must be less than or equal to ulHTLinkFreq(bootup frequency).3399ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0.3400This must be less than or equal to ulHighVoltageHTLinkFreq.34013402usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now.3403usMaxDownStreamHTLinkWidth: same as above.3404usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now.3405usMinDownStreamHTLinkWidth: same as above.3406*/34073408// ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition3409#define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 03410#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 13411#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 23412#define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 33413#define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 43414#define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI 534153416#define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code34173418#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x000000013419#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x000000023420#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x000000043421#define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x000000083422#define SYSTEM_CONFIG_CLMC_ENABLED 0x000000103423#define SYSTEM_CONFIG_CDLW_ENABLED 0x000000203424#define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x000000403425#define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x000000803426#define SYSTEM_CONFIG_CDLF_ENABLED 0x000001003427#define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x0000020034283429#define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF34303431#define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F3432#define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF03433#define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x013434#define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x023435#define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x043436#define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x0834373438#define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF003439#define IGP_DDI_SLOT_CONFIG_REVERSED 0x000001003440#define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x0134413442#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF000034433444// IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR3445typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V53446{3447ATOM_COMMON_TABLE_HEADER sHeader;3448ULONG ulBootUpEngineClock; //in 10kHz unit3449ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK.3450ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge3451ULONG ulBootUpUMAClock; //in 10kHz unit3452ULONG ulReserved1[8]; //must be 0x0 for the reserved3453ULONG ulBootUpReqDisplayVector;3454ULONG ulOtherDisplayMisc;3455ULONG ulReserved2[4]; //must be 0x0 for the reserved3456ULONG ulSystemConfig; //TBD3457ULONG ulCPUCapInfo; //TBD3458USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;3459USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;3460USHORT usBootUpNBVoltage; //boot up NB voltage3461UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD3462UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD3463ULONG ulReserved3[4]; //must be 0x0 for the reserved3464ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition3465ULONG ulDDISlot2Config;3466ULONG ulDDISlot3Config;3467ULONG ulDDISlot4Config;3468ULONG ulReserved4[4]; //must be 0x0 for the reserved3469UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved3470UCHAR ucUMAChannelNumber;3471USHORT usReserved;3472ULONG ulReserved5[4]; //must be 0x0 for the reserved3473ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default3474ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback3475ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications3476ULONG ulReserved6[61]; //must be 0x03477}ATOM_INTEGRATED_SYSTEM_INFO_V5;3478347934803481/****************************************************************************/3482// Structure used in GPUVirtualizationInfoTable3483/****************************************************************************/3484typedef struct _ATOM_GPU_VIRTUALIZATION_INFO_V2_13485{3486ATOM_COMMON_TABLE_HEADER sHeader;3487ULONG ulMCUcodeRomStartAddr;3488ULONG ulMCUcodeLength;3489ULONG ulSMCUcodeRomStartAddr;3490ULONG ulSMCUcodeLength;3491ULONG ulRLCVUcodeRomStartAddr;3492ULONG ulRLCVUcodeLength;3493ULONG ulTOCUcodeStartAddr;3494ULONG ulTOCUcodeLength;3495ULONG ulSMCPatchTableStartAddr;3496ULONG ulSmcPatchTableLength;3497ULONG ulSystemFlag;3498}ATOM_GPU_VIRTUALIZATION_INFO_V2_1;349935003501#define ATOM_CRT_INT_ENCODER1_INDEX 0x000000003502#define ATOM_LCD_INT_ENCODER1_INDEX 0x000000013503#define ATOM_TV_INT_ENCODER1_INDEX 0x000000023504#define ATOM_DFP_INT_ENCODER1_INDEX 0x000000033505#define ATOM_CRT_INT_ENCODER2_INDEX 0x000000043506#define ATOM_LCD_EXT_ENCODER1_INDEX 0x000000053507#define ATOM_TV_EXT_ENCODER1_INDEX 0x000000063508#define ATOM_DFP_EXT_ENCODER1_INDEX 0x000000073509#define ATOM_CV_INT_ENCODER1_INDEX 0x000000083510#define ATOM_DFP_INT_ENCODER2_INDEX 0x000000093511#define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A3512#define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B3513#define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C3514#define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D35153516// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable3517#define ASIC_INT_DAC1_ENCODER_ID 0x003518#define ASIC_INT_TV_ENCODER_ID 0x023519#define ASIC_INT_DIG1_ENCODER_ID 0x033520#define ASIC_INT_DAC2_ENCODER_ID 0x043521#define ASIC_EXT_TV_ENCODER_ID 0x063522#define ASIC_INT_DVO_ENCODER_ID 0x073523#define ASIC_INT_DIG2_ENCODER_ID 0x093524#define ASIC_EXT_DIG_ENCODER_ID 0x053525#define ASIC_EXT_DIG2_ENCODER_ID 0x083526#define ASIC_INT_DIG3_ENCODER_ID 0x0a3527#define ASIC_INT_DIG4_ENCODER_ID 0x0b3528#define ASIC_INT_DIG5_ENCODER_ID 0x0c3529#define ASIC_INT_DIG6_ENCODER_ID 0x0d3530#define ASIC_INT_DIG7_ENCODER_ID 0x0e35313532//define Encoder attribute3533#define ATOM_ANALOG_ENCODER 03534#define ATOM_DIGITAL_ENCODER 13535#define ATOM_DP_ENCODER 235363537#define ATOM_ENCODER_ENUM_MASK 0x703538#define ATOM_ENCODER_ENUM_ID1 0x003539#define ATOM_ENCODER_ENUM_ID2 0x103540#define ATOM_ENCODER_ENUM_ID3 0x203541#define ATOM_ENCODER_ENUM_ID4 0x303542#define ATOM_ENCODER_ENUM_ID5 0x403543#define ATOM_ENCODER_ENUM_ID6 0x5035443545#define ATOM_DEVICE_CRT1_INDEX 0x000000003546#define ATOM_DEVICE_LCD1_INDEX 0x000000013547#define ATOM_DEVICE_TV1_INDEX 0x000000023548#define ATOM_DEVICE_DFP1_INDEX 0x000000033549#define ATOM_DEVICE_CRT2_INDEX 0x000000043550#define ATOM_DEVICE_LCD2_INDEX 0x000000053551#define ATOM_DEVICE_DFP6_INDEX 0x000000063552#define ATOM_DEVICE_DFP2_INDEX 0x000000073553#define ATOM_DEVICE_CV_INDEX 0x000000083554#define ATOM_DEVICE_DFP3_INDEX 0x000000093555#define ATOM_DEVICE_DFP4_INDEX 0x0000000A3556#define ATOM_DEVICE_DFP5_INDEX 0x0000000B35573558#define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C3559#define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D3560#define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E3561#define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F3562#define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1)3563#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO3564#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 )35653566#define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1)35673568#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX )3569#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX )3570#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX )3571#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX )3572#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX )3573#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX )3574#define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX )3575#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX )3576#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX )3577#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX )3578#define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX )3579#define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX )358035813582#define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT)3583#define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT)3584#define ATOM_DEVICE_TV_SUPPORT ATOM_DEVICE_TV1_SUPPORT3585#define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT)35863587#define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F03588#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x000000043589#define ATOM_DEVICE_CONNECTOR_VGA 0x000000013590#define ATOM_DEVICE_CONNECTOR_DVI_I 0x000000023591#define ATOM_DEVICE_CONNECTOR_DVI_D 0x000000033592#define ATOM_DEVICE_CONNECTOR_DVI_A 0x000000043593#define ATOM_DEVICE_CONNECTOR_SVIDEO 0x000000053594#define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x000000063595#define ATOM_DEVICE_CONNECTOR_LVDS 0x000000073596#define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x000000083597#define ATOM_DEVICE_CONNECTOR_SCART 0x000000093598#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A3599#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B3600#define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E3601#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F360236033604#define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F3605#define ATOM_DEVICE_DAC_INFO_SHIFT 0x000000003606#define ATOM_DEVICE_DAC_INFO_NODAC 0x000000003607#define ATOM_DEVICE_DAC_INFO_DACA 0x000000013608#define ATOM_DEVICE_DAC_INFO_DACB 0x000000023609#define ATOM_DEVICE_DAC_INFO_EXDAC 0x0000000336103611#define ATOM_DEVICE_I2C_ID_NOI2C 0x0000000036123613#define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F3614#define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x0000000036153616#define ATOM_DEVICE_I2C_ID_MASK 0x000000703617#define ATOM_DEVICE_I2C_ID_SHIFT 0x000000043618#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x000000013619#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x000000023620#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS6003621#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS69036223623#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x000000803624#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x000000073625#define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x000000003626#define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x0000000136273628// usDeviceSupport:3629// Bits0 = 0 - no CRT1 support= 1- CRT1 is supported3630// Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported3631// Bit 2 = 0 - no TV1 support= 1- TV1 is supported3632// Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported3633// Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported3634// Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported3635// Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported3636// Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported3637// Bit 8 = 0 - no CV support= 1- CV is supported3638// Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported3639// Bit 10= 0 - no DFP4 support= 1- DFP4 is supported3640// Bit 11= 0 - no DFP5 support= 1- DFP5 is supported3641//3642//36433644/****************************************************************************/3645// Structure used in MclkSS_InfoTable3646/****************************************************************************/3647// ucI2C_ConfigID3648// [7:0] - I2C LINE Associate ID3649// = 0 - no I2C3650// [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)3651// = 0, [6:0]=SW assisted I2C ID3652// [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use3653// = 2, HW engine for Multimedia use3654// = 3-7 Reserved for future I2C engines3655// [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C36563657typedef struct _ATOM_I2C_ID_CONFIG3658{3659#if ATOM_BIG_ENDIAN3660UCHAR bfHW_Capable:1;3661UCHAR bfHW_EngineID:3;3662UCHAR bfI2C_LineMux:4;3663#else3664UCHAR bfI2C_LineMux:4;3665UCHAR bfHW_EngineID:3;3666UCHAR bfHW_Capable:1;3667#endif3668}ATOM_I2C_ID_CONFIG;36693670typedef union _ATOM_I2C_ID_CONFIG_ACCESS3671{3672ATOM_I2C_ID_CONFIG sbfAccess;3673UCHAR ucAccess;3674}ATOM_I2C_ID_CONFIG_ACCESS;367536763677/****************************************************************************/3678// Structure used in GPIO_I2C_InfoTable3679/****************************************************************************/3680typedef struct _ATOM_GPIO_I2C_ASSIGMENT3681{3682USHORT usClkMaskRegisterIndex;3683USHORT usClkEnRegisterIndex;3684USHORT usClkY_RegisterIndex;3685USHORT usClkA_RegisterIndex;3686USHORT usDataMaskRegisterIndex;3687USHORT usDataEnRegisterIndex;3688USHORT usDataY_RegisterIndex;3689USHORT usDataA_RegisterIndex;3690ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;3691UCHAR ucClkMaskShift;3692UCHAR ucClkEnShift;3693UCHAR ucClkY_Shift;3694UCHAR ucClkA_Shift;3695UCHAR ucDataMaskShift;3696UCHAR ucDataEnShift;3697UCHAR ucDataY_Shift;3698UCHAR ucDataA_Shift;3699UCHAR ucReserved1;3700UCHAR ucReserved2;3701}ATOM_GPIO_I2C_ASSIGMENT;37023703typedef struct _ATOM_GPIO_I2C_INFO3704{3705ATOM_COMMON_TABLE_HEADER sHeader;3706ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE];3707}ATOM_GPIO_I2C_INFO;37083709/****************************************************************************/3710// Common Structure used in other structures3711/****************************************************************************/37123713#ifndef _H2INC37143715//Please don't add or expand this bitfield structure below, this one will retire soon.!3716typedef struct _ATOM_MODE_MISC_INFO3717{3718#if ATOM_BIG_ENDIAN3719USHORT Reserved:6;3720USHORT RGB888:1;3721USHORT DoubleClock:1;3722USHORT Interlace:1;3723USHORT CompositeSync:1;3724USHORT V_ReplicationBy2:1;3725USHORT H_ReplicationBy2:1;3726USHORT VerticalCutOff:1;3727USHORT VSyncPolarity:1; //0=Active High, 1=Active Low3728USHORT HSyncPolarity:1; //0=Active High, 1=Active Low3729USHORT HorizontalCutOff:1;3730#else3731USHORT HorizontalCutOff:1;3732USHORT HSyncPolarity:1; //0=Active High, 1=Active Low3733USHORT VSyncPolarity:1; //0=Active High, 1=Active Low3734USHORT VerticalCutOff:1;3735USHORT H_ReplicationBy2:1;3736USHORT V_ReplicationBy2:1;3737USHORT CompositeSync:1;3738USHORT Interlace:1;3739USHORT DoubleClock:1;3740USHORT RGB888:1;3741USHORT Reserved:6;3742#endif3743}ATOM_MODE_MISC_INFO;37443745typedef union _ATOM_MODE_MISC_INFO_ACCESS3746{3747ATOM_MODE_MISC_INFO sbfAccess;3748USHORT usAccess;3749}ATOM_MODE_MISC_INFO_ACCESS;37503751#else37523753typedef union _ATOM_MODE_MISC_INFO_ACCESS3754{3755USHORT usAccess;3756}ATOM_MODE_MISC_INFO_ACCESS;37573758#endif37593760// usModeMiscInfo-3761#define ATOM_H_CUTOFF 0x013762#define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low3763#define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low3764#define ATOM_V_CUTOFF 0x083765#define ATOM_H_REPLICATIONBY2 0x103766#define ATOM_V_REPLICATIONBY2 0x203767#define ATOM_COMPOSITESYNC 0x403768#define ATOM_INTERLACE 0x803769#define ATOM_DOUBLE_CLOCK_MODE 0x1003770#define ATOM_RGB888_MODE 0x20037713772//usRefreshRate-3773#define ATOM_REFRESH_43 433774#define ATOM_REFRESH_47 473775#define ATOM_REFRESH_56 563776#define ATOM_REFRESH_60 603777#define ATOM_REFRESH_65 653778#define ATOM_REFRESH_70 703779#define ATOM_REFRESH_72 723780#define ATOM_REFRESH_75 753781#define ATOM_REFRESH_85 8537823783// ATOM_MODE_TIMING data are exactly the same as VESA timing data.3784// Translation from EDID to ATOM_MODE_TIMING, use the following formula.3785//3786// VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK3787// = EDID_HA + EDID_HBL3788// VESA_HDISP = VESA_ACTIVE = EDID_HA3789// VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH3790// = EDID_HA + EDID_HSO3791// VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW3792// VESA_BORDER = EDID_BORDER379337943795/****************************************************************************/3796// Structure used in SetCRTC_UsingDTDTimingTable3797/****************************************************************************/3798typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS3799{3800USHORT usH_Size;3801USHORT usH_Blanking_Time;3802USHORT usV_Size;3803USHORT usV_Blanking_Time;3804USHORT usH_SyncOffset;3805USHORT usH_SyncWidth;3806USHORT usV_SyncOffset;3807USHORT usV_SyncWidth;3808ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;3809UCHAR ucH_Border; // From DFP EDID3810UCHAR ucV_Border;3811UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC23812UCHAR ucPadding[3];3813}SET_CRTC_USING_DTD_TIMING_PARAMETERS;38143815/****************************************************************************/3816// Structure used in SetCRTC_TimingTable3817/****************************************************************************/3818typedef struct _SET_CRTC_TIMING_PARAMETERS3819{3820USHORT usH_Total; // horizontal total3821USHORT usH_Disp; // horizontal display3822USHORT usH_SyncStart; // horozontal Sync start3823USHORT usH_SyncWidth; // horizontal Sync width3824USHORT usV_Total; // vertical total3825USHORT usV_Disp; // vertical display3826USHORT usV_SyncStart; // vertical Sync start3827USHORT usV_SyncWidth; // vertical Sync width3828ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;3829UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC23830UCHAR ucOverscanRight; // right3831UCHAR ucOverscanLeft; // left3832UCHAR ucOverscanBottom; // bottom3833UCHAR ucOverscanTop; // top3834UCHAR ucReserved;3835}SET_CRTC_TIMING_PARAMETERS;3836#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS383738383839/****************************************************************************/3840// Structure used in StandardVESA_TimingTable3841// AnalogTV_InfoTable3842// ComponentVideoInfoTable3843/****************************************************************************/3844typedef struct _ATOM_MODE_TIMING3845{3846USHORT usCRTC_H_Total;3847USHORT usCRTC_H_Disp;3848USHORT usCRTC_H_SyncStart;3849USHORT usCRTC_H_SyncWidth;3850USHORT usCRTC_V_Total;3851USHORT usCRTC_V_Disp;3852USHORT usCRTC_V_SyncStart;3853USHORT usCRTC_V_SyncWidth;3854USHORT usPixelClock; //in 10Khz unit3855ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;3856USHORT usCRTC_OverscanRight;3857USHORT usCRTC_OverscanLeft;3858USHORT usCRTC_OverscanBottom;3859USHORT usCRTC_OverscanTop;3860USHORT usReserve;3861UCHAR ucInternalModeNumber;3862UCHAR ucRefreshRate;3863}ATOM_MODE_TIMING;38643865typedef struct _ATOM_DTD_FORMAT3866{3867USHORT usPixClk;3868USHORT usHActive;3869USHORT usHBlanking_Time;3870USHORT usVActive;3871USHORT usVBlanking_Time;3872USHORT usHSyncOffset;3873USHORT usHSyncWidth;3874USHORT usVSyncOffset;3875USHORT usVSyncWidth;3876USHORT usImageHSize;3877USHORT usImageVSize;3878UCHAR ucHBorder;3879UCHAR ucVBorder;3880ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;3881UCHAR ucInternalModeNumber;3882UCHAR ucRefreshRate;3883}ATOM_DTD_FORMAT;38843885/****************************************************************************/3886// Structure used in LVDS_InfoTable3887// * Need a document to describe this table3888/****************************************************************************/3889#define SUPPORTED_LCD_REFRESHRATE_30Hz 0x00043890#define SUPPORTED_LCD_REFRESHRATE_40Hz 0x00083891#define SUPPORTED_LCD_REFRESHRATE_50Hz 0x00103892#define SUPPORTED_LCD_REFRESHRATE_60Hz 0x00203893#define SUPPORTED_LCD_REFRESHRATE_48Hz 0x004038943895//ucTableFormatRevision=13896//ucTableContentRevision=13897typedef struct _ATOM_LVDS_INFO3898{3899ATOM_COMMON_TABLE_HEADER sHeader;3900ATOM_DTD_FORMAT sLCDTiming;3901USHORT usModePatchTableOffset;3902USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.3903USHORT usOffDelayInMs;3904UCHAR ucPowerSequenceDigOntoDEin10Ms;3905UCHAR ucPowerSequenceDEtoBLOnin10Ms;3906UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}3907// Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}3908// Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}3909// Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}3910UCHAR ucPanelDefaultRefreshRate;3911UCHAR ucPanelIdentification;3912UCHAR ucSS_Id;3913}ATOM_LVDS_INFO;39143915//ucTableFormatRevision=13916//ucTableContentRevision=23917typedef struct _ATOM_LVDS_INFO_V123918{3919ATOM_COMMON_TABLE_HEADER sHeader;3920ATOM_DTD_FORMAT sLCDTiming;3921USHORT usExtInfoTableOffset;3922USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.3923USHORT usOffDelayInMs;3924UCHAR ucPowerSequenceDigOntoDEin10Ms;3925UCHAR ucPowerSequenceDEtoBLOnin10Ms;3926UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}3927// Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}3928// Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}3929// Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}3930UCHAR ucPanelDefaultRefreshRate;3931UCHAR ucPanelIdentification;3932UCHAR ucSS_Id;3933USHORT usLCDVenderID;3934USHORT usLCDProductID;3935UCHAR ucLCDPanel_SpecialHandlingCap;3936UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable3937UCHAR ucReserved[2];3938}ATOM_LVDS_INFO_V12;39393940//Definitions for ucLCDPanel_SpecialHandlingCap:39413942//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.3943//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL3944#define LCDPANEL_CAP_READ_EDID 0x139453946//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together3947//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static3948//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V123949#define LCDPANEL_CAP_DRR_SUPPORTED 0x239503951//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.3952#define LCDPANEL_CAP_eDP 0x4395339543955//Color Bit Depth definition in EDID V1.4 @BYTE 14h3956//Bit 6 5 43957// 0 0 0 - Color bit depth is undefined3958// 0 0 1 - 6 Bits per Primary Color3959// 0 1 0 - 8 Bits per Primary Color3960// 0 1 1 - 10 Bits per Primary Color3961// 1 0 0 - 12 Bits per Primary Color3962// 1 0 1 - 14 Bits per Primary Color3963// 1 1 0 - 16 Bits per Primary Color3964// 1 1 1 - Reserved39653966#define PANEL_COLOR_BIT_DEPTH_MASK 0x7039673968// Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled}3969#define PANEL_RANDOM_DITHER 0x803970#define PANEL_RANDOM_DITHER_MASK 0x8039713972#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this397339743975typedef struct _ATOM_LCD_REFRESH_RATE_SUPPORT3976{3977UCHAR ucSupportedRefreshRate;3978UCHAR ucMinRefreshRateForDRR;3979}ATOM_LCD_REFRESH_RATE_SUPPORT;39803981/****************************************************************************/3982// Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V123983// ASIC Families: NI3984// ucTableFormatRevision=13985// ucTableContentRevision=33986/****************************************************************************/3987typedef struct _ATOM_LCD_INFO_V133988{3989ATOM_COMMON_TABLE_HEADER sHeader;3990ATOM_DTD_FORMAT sLCDTiming;3991USHORT usExtInfoTableOffset;3992union3993{3994USHORT usSupportedRefreshRate;3995ATOM_LCD_REFRESH_RATE_SUPPORT sRefreshRateSupport;3996};3997ULONG ulReserved0;3998UCHAR ucLCD_Misc; // Reorganized in V133999// Bit0: {=0:single, =1:dual},4000// Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB},4001// Bit3:2: {Grey level}4002// Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h)4003// Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it?4004UCHAR ucPanelDefaultRefreshRate;4005UCHAR ucPanelIdentification;4006UCHAR ucSS_Id;4007USHORT usLCDVenderID;4008USHORT usLCDProductID;4009UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V134010// Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own4011// Bit1: See LCDPANEL_CAP_DRR_SUPPORTED4012// Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1)4013// Bit7-3: Reserved4014UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable4015USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V1340164017UCHAR ucPowerSequenceDIGONtoDE_in4Ms;4018UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms;4019UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms;4020UCHAR ucPowerSequenceDEtoDIGON_in4Ms;40214022UCHAR ucOffDelay_in4Ms;4023UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms;4024UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms;4025UCHAR ucReserved1;40264027UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh4028UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h4029UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h4030UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h40314032USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode.4033UCHAR uceDPToLVDSRxId;4034UCHAR ucLcdReservd;4035ULONG ulReserved[2];4036}ATOM_LCD_INFO_V13;40374038#define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V1340394040//Definitions for ucLCD_Misc4041#define ATOM_PANEL_MISC_V13_DUAL 0x000000014042#define ATOM_PANEL_MISC_V13_FPDI 0x000000024043#define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C4044#define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 24045#define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x704046#define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x104047#define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x2040484049//Color Bit Depth definition in EDID V1.4 @BYTE 14h4050//Bit 6 5 44051// 0 0 0 - Color bit depth is undefined4052// 0 0 1 - 6 Bits per Primary Color4053// 0 1 0 - 8 Bits per Primary Color4054// 0 1 1 - 10 Bits per Primary Color4055// 1 0 0 - 12 Bits per Primary Color4056// 1 0 1 - 14 Bits per Primary Color4057// 1 1 0 - 16 Bits per Primary Color4058// 1 1 1 - Reserved40594060//Definitions for ucLCDPanel_SpecialHandlingCap:40614062//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.4063//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL4064#define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version40654066//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together4067//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static4068//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V124069#define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version40704071//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.4072#define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version40734074//uceDPToLVDSRxId4075#define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip4076#define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init4077#define eDP_TO_LVDS_RT_ID 0x02 // RT tansaltor which require AMD SW init40784079typedef struct _ATOM_PATCH_RECORD_MODE4080{4081UCHAR ucRecordType;4082USHORT usHDisp;4083USHORT usVDisp;4084}ATOM_PATCH_RECORD_MODE;40854086typedef struct _ATOM_LCD_RTS_RECORD4087{4088UCHAR ucRecordType;4089UCHAR ucRTSValue;4090}ATOM_LCD_RTS_RECORD;40914092//!! If the record below exits, it shoud always be the first record for easy use in command table!!!4093// The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead.4094typedef struct _ATOM_LCD_MODE_CONTROL_CAP4095{4096UCHAR ucRecordType;4097USHORT usLCDCap;4098}ATOM_LCD_MODE_CONTROL_CAP;40994100#define LCD_MODE_CAP_BL_OFF 14101#define LCD_MODE_CAP_CRTC_OFF 24102#define LCD_MODE_CAP_PANEL_OFF 4410341044105typedef struct _ATOM_FAKE_EDID_PATCH_RECORD4106{4107UCHAR ucRecordType;4108UCHAR ucFakeEDIDLength; // = 128 means EDID length is 128 bytes, otherwise the EDID length = ucFakeEDIDLength*1284109UCHAR ucFakeEDIDString[]; // This actually has ucFakeEdidLength elements.4110} ATOM_FAKE_EDID_PATCH_RECORD;41114112typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD4113{4114UCHAR ucRecordType;4115USHORT usHSize;4116USHORT usVSize;4117}ATOM_PANEL_RESOLUTION_PATCH_RECORD;41184119#define LCD_MODE_PATCH_RECORD_MODE_TYPE 14120#define LCD_RTS_RECORD_TYPE 24121#define LCD_CAP_RECORD_TYPE 34122#define LCD_FAKE_EDID_PATCH_RECORD_TYPE 44123#define LCD_PANEL_RESOLUTION_RECORD_TYPE 54124#define LCD_EDID_OFFSET_PATCH_RECORD_TYPE 64125#define ATOM_RECORD_END_TYPE 0xFF41264127/****************************Spread Spectrum Info Table Definitions **********************/41284129//ucTableFormatRevision=14130//ucTableContentRevision=24131typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT4132{4133USHORT usSpreadSpectrumPercentage;4134UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD4135UCHAR ucSS_Step;4136UCHAR ucSS_Delay;4137UCHAR ucSS_Id;4138UCHAR ucRecommendedRef_Div;4139UCHAR ucSS_Range; //it was reserved for V114140}ATOM_SPREAD_SPECTRUM_ASSIGNMENT;41414142#define ATOM_MAX_SS_ENTRY 164143#define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well.4144#define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable.4145#define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz4146#define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz4147414841494150#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x000000004151#define ATOM_SS_DOWN_SPREAD_MODE 0x000000004152#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x000000014153#define ATOM_SS_CENTRE_SPREAD_MODE 0x000000014154#define ATOM_INTERNAL_SS_MASK 0x000000004155#define ATOM_EXTERNAL_SS_MASK 0x000000024156#define EXEC_SS_STEP_SIZE_SHIFT 24157#define EXEC_SS_DELAY_SHIFT 44158#define ACTIVEDATA_TO_BLON_DELAY_SHIFT 441594160typedef struct _ATOM_SPREAD_SPECTRUM_INFO4161{4162ATOM_COMMON_TABLE_HEADER sHeader;4163ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY];4164}ATOM_SPREAD_SPECTRUM_INFO;416541664167/****************************************************************************/4168// Structure used in AnalogTV_InfoTable (Top level)4169/****************************************************************************/4170//ucTVBootUpDefaultStd definiton:41714172//ATOM_TV_NTSC 14173//ATOM_TV_NTSCJ 24174//ATOM_TV_PAL 34175//ATOM_TV_PALM 44176//ATOM_TV_PALCN 54177//ATOM_TV_PALN 64178//ATOM_TV_PAL60 74179//ATOM_TV_SECAM 841804181//ucTVSuppportedStd definition:4182#define NTSC_SUPPORT 0x14183#define NTSCJ_SUPPORT 0x241844185#define PAL_SUPPORT 0x44186#define PALM_SUPPORT 0x84187#define PALCN_SUPPORT 0x104188#define PALN_SUPPORT 0x204189#define PAL60_SUPPORT 0x404190#define SECAM_SUPPORT 0x8041914192#define MAX_SUPPORTED_TV_TIMING 241934194typedef struct _ATOM_ANALOG_TV_INFO4195{4196ATOM_COMMON_TABLE_HEADER sHeader;4197UCHAR ucTV_SuppportedStandard;4198UCHAR ucTV_BootUpDefaultStandard;4199UCHAR ucExt_TV_ASIC_ID;4200UCHAR ucExt_TV_ASIC_SlaveAddr;4201ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];4202}ATOM_ANALOG_TV_INFO;42034204typedef struct _ATOM_DPCD_INFO4205{4206UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.14207UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane4208UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP4209UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec)4210}ATOM_DPCD_INFO;42114212#define ATOM_DPCD_MAX_LANE_MASK 0x1F42134214/**************************************************************************/4215// VRAM usage and their defintions42164217// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data.4218// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below.4219// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned!4220// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR4221// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX42224223// Moved VESA_MEMORY_IN_64K_BLOCK definition to "AtomConfig.h" so that it can be redefined in design (SKU).4224//#ifndef VESA_MEMORY_IN_64K_BLOCK4225//#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!)4226//#endif42274228#define ATOM_EDID_RAW_DATASIZE 256 //In Bytes4229#define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes4230#define ATOM_HWICON_INFOTABLE_SIZE 324231#define MAX_DTD_MODE_IN_VRAM 64232#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT)4233#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT)4234//20 bytes for Encoder Type and DPCD in STD EDID area4235#define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)4236#define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 )42374238#define ATOM_HWICON1_SURFACE_ADDR 04239#define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)4240#define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)4241#define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE)4242#define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)4243#define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)42444245#define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)4246#define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)4247#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)42484249#define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)42504251#define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)4252#define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)4253#define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)42544255#define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)4256#define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)4257#define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)42584259#define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)4260#define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)4261#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)42624263#define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)4264#define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)4265#define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)42664267#define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)4268#define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)4269#define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)42704271#define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)4272#define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)4273#define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)42744275#define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)4276#define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)4277#define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)42784279#define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)4280#define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)4281#define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)42824283#define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)4284#define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)4285#define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)42864287#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)42884289#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024)4290#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 51242914292//The size below is in Kb!4293#define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC)42944295#define ATOM_VRAM_RESERVE_V2_SIZE 3242964297#define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L4298#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 304299#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x14300#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x04301#define ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION 0x243024303/***********************************************************************************/4304// Structure used in VRAM_UsageByFirmwareTable4305// Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm4306// at running time.4307// note2: From RV770, the memory is more than 32bit addressable, so we will change4308// ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains4309// exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware4310// (in offset to start of memory address) is KB aligned instead of byte aligned.4311// Note3:4312/* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged4313constant across VGA or non VGA adapter,4314for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have:43154316If (ulStartAddrUsedByFirmware!=0)4317FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;4318Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose4319else //Non VGA case4320if (FB_Size<=2Gb)4321FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;4322else4323FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB43244325CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/43264327/***********************************************************************************/4328#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 143294330typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO4331{4332ULONG ulStartAddrUsedByFirmware;4333USHORT usFirmwareUseInKb;4334USHORT usReserved;4335}ATOM_FIRMWARE_VRAM_RESERVE_INFO;43364337typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE4338{4339ATOM_COMMON_TABLE_HEADER sHeader;4340ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];4341}ATOM_VRAM_USAGE_BY_FIRMWARE;43424343// change verion to 1.5, when allow driver to allocate the vram area for command table access.4344typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_54345{4346ULONG ulStartAddrUsedByFirmware;4347USHORT usFirmwareUseInKb;4348USHORT usFBUsedByDrvInKb;4349}ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5;43504351typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_54352{4353ATOM_COMMON_TABLE_HEADER sHeader;4354ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];4355}ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5;43564357/****************************************************************************/4358// Structure used in GPIO_Pin_LUTTable4359/****************************************************************************/4360typedef struct _ATOM_GPIO_PIN_ASSIGNMENT4361{4362USHORT usGpioPin_AIndex;4363UCHAR ucGpioPinBitShift;4364UCHAR ucGPIO_ID;4365}ATOM_GPIO_PIN_ASSIGNMENT;43664367//ucGPIO_ID pre-define id for multiple usage4368// GPIO use to control PCIE_VDDC in certain SLT board4369#define PCIE_VDDC_CONTROL_GPIO_PINID 5643704371//from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC switching feature is enable4372#define PP_AC_DC_SWITCH_GPIO_PINID 604373//from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable4374#define VDDC_VRHOT_GPIO_PINID 614375//if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled4376#define VDDC_PCC_GPIO_PINID 624377// Only used on certain SLT/PA board to allow utility to cut Efuse.4378#define EFUSE_CUT_ENABLE_GPIO_PINID 634379// ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO=4380#define DRAM_SELF_REFRESH_GPIO_PINID 644381// Thermal interrupt output->system thermal chip GPIO pin4382#define THERMAL_INT_OUTPUT_GPIO_PINID 65438343844385typedef struct _ATOM_GPIO_PIN_LUT4386{4387ATOM_COMMON_TABLE_HEADER sHeader;4388ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[];4389}ATOM_GPIO_PIN_LUT;43904391/****************************************************************************/4392// Structure used in ComponentVideoInfoTable4393/****************************************************************************/4394#define GPIO_PIN_ACTIVE_HIGH 0x14395#define MAX_SUPPORTED_CV_STANDARDS 543964397// definitions for ATOM_D_INFO.ucSettings4398#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0]4399#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out4400#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7]44014402typedef struct _ATOM_GPIO_INFO4403{4404USHORT usAOffset;4405UCHAR ucSettings;4406UCHAR ucReserved;4407}ATOM_GPIO_INFO;44084409// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector)4410#define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x244114412// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i4413#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7];4414#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0]44154416// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode4417//Line 3 out put 5V.4418#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:94419#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:94420#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x044214422//Line 3 out put 2.2V4423#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box4424#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box4425#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x244264427//Line 3 out put 0V4428#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:34429#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:34430#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x444314432#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0]44334434#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 744354436//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks.4437#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.4438#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.443944404441typedef struct _ATOM_COMPONENT_VIDEO_INFO4442{4443ATOM_COMMON_TABLE_HEADER sHeader;4444USHORT usMask_PinRegisterIndex;4445USHORT usEN_PinRegisterIndex;4446USHORT usY_PinRegisterIndex;4447USHORT usA_PinRegisterIndex;4448UCHAR ucBitShift;4449UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low4450ATOM_DTD_FORMAT sReserved; // must be zeroed out4451UCHAR ucMiscInfo;4452UCHAR uc480i;4453UCHAR uc480p;4454UCHAR uc720p;4455UCHAR uc1080i;4456UCHAR ucLetterBoxMode;4457UCHAR ucReserved[3];4458UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector4459ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];4460ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];4461}ATOM_COMPONENT_VIDEO_INFO;44624463//ucTableFormatRevision=24464//ucTableContentRevision=14465typedef struct _ATOM_COMPONENT_VIDEO_INFO_V214466{4467ATOM_COMMON_TABLE_HEADER sHeader;4468UCHAR ucMiscInfo;4469UCHAR uc480i;4470UCHAR uc480p;4471UCHAR uc720p;4472UCHAR uc1080i;4473UCHAR ucReserved;4474UCHAR ucLetterBoxMode;4475UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector4476ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];4477ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];4478}ATOM_COMPONENT_VIDEO_INFO_V21;44794480#define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V2144814482/****************************************************************************/4483// Structure used in object_InfoTable4484/****************************************************************************/4485typedef struct _ATOM_OBJECT_HEADER4486{4487ATOM_COMMON_TABLE_HEADER sHeader;4488USHORT usDeviceSupport;4489USHORT usConnectorObjectTableOffset;4490USHORT usRouterObjectTableOffset;4491USHORT usEncoderObjectTableOffset;4492USHORT usProtectionObjectTableOffset; //only available when Protection block is independent.4493USHORT usDisplayPathTableOffset;4494}ATOM_OBJECT_HEADER;44954496typedef struct _ATOM_OBJECT_HEADER_V34497{4498ATOM_COMMON_TABLE_HEADER sHeader;4499USHORT usDeviceSupport;4500USHORT usConnectorObjectTableOffset;4501USHORT usRouterObjectTableOffset;4502USHORT usEncoderObjectTableOffset;4503USHORT usProtectionObjectTableOffset; //only available when Protection block is independent.4504USHORT usDisplayPathTableOffset;4505USHORT usMiscObjectTableOffset;4506}ATOM_OBJECT_HEADER_V3;450745084509typedef struct _ATOM_DISPLAY_OBJECT_PATH4510{4511USHORT usDeviceTag; //supported device4512USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH4513USHORT usConnObjectId; //Connector Object ID4514USHORT usGPUObjectId; //GPU ID4515USHORT usGraphicObjIds[]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector.4516}ATOM_DISPLAY_OBJECT_PATH;45174518typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH4519{4520USHORT usDeviceTag; //supported device4521USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH4522USHORT usConnObjectId; //Connector Object ID4523USHORT usGPUObjectId; //GPU ID4524USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder4525}ATOM_DISPLAY_EXTERNAL_OBJECT_PATH;45264527typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE4528{4529UCHAR ucNumOfDispPath;4530UCHAR ucVersion;4531UCHAR ucPadding[2];4532ATOM_DISPLAY_OBJECT_PATH asDispPath[];4533}ATOM_DISPLAY_OBJECT_PATH_TABLE;45344535typedef struct _ATOM_OBJECT //each object has this structure4536{4537USHORT usObjectID;4538USHORT usSrcDstTableOffset;4539USHORT usRecordOffset; //this pointing to a bunch of records defined below4540USHORT usReserved;4541}ATOM_OBJECT;45424543typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure4544{4545UCHAR ucNumberOfObjects;4546UCHAR ucPadding[3];4547ATOM_OBJECT asObjects[];4548}ATOM_OBJECT_TABLE;45494550typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure4551{4552UCHAR ucNumberOfSrc;4553USHORT usSrcObjectID[1];4554UCHAR ucNumberOfDst;4555USHORT usDstObjectID[1];4556}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT;455745584559//Two definitions below are for OPM on MXM module designs45604561#define EXT_HPDPIN_LUTINDEX_0 04562#define EXT_HPDPIN_LUTINDEX_1 14563#define EXT_HPDPIN_LUTINDEX_2 24564#define EXT_HPDPIN_LUTINDEX_3 34565#define EXT_HPDPIN_LUTINDEX_4 44566#define EXT_HPDPIN_LUTINDEX_5 54567#define EXT_HPDPIN_LUTINDEX_6 64568#define EXT_HPDPIN_LUTINDEX_7 74569#define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1)45704571#define EXT_AUXDDC_LUTINDEX_0 04572#define EXT_AUXDDC_LUTINDEX_1 14573#define EXT_AUXDDC_LUTINDEX_2 24574#define EXT_AUXDDC_LUTINDEX_3 34575#define EXT_AUXDDC_LUTINDEX_4 44576#define EXT_AUXDDC_LUTINDEX_5 54577#define EXT_AUXDDC_LUTINDEX_6 64578#define EXT_AUXDDC_LUTINDEX_7 74579#define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1)45804581//ucChannelMapping are defined as following4582//for DP connector, eDP, DP to VGA/LVDS4583//Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX34584//Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX34585//Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX34586//Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX34587typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING4588{4589#if ATOM_BIG_ENDIAN4590UCHAR ucDP_Lane3_Source:2;4591UCHAR ucDP_Lane2_Source:2;4592UCHAR ucDP_Lane1_Source:2;4593UCHAR ucDP_Lane0_Source:2;4594#else4595UCHAR ucDP_Lane0_Source:2;4596UCHAR ucDP_Lane1_Source:2;4597UCHAR ucDP_Lane2_Source:2;4598UCHAR ucDP_Lane3_Source:2;4599#endif4600}ATOM_DP_CONN_CHANNEL_MAPPING;46014602//for DVI/HDMI, in dual link case, both links have to have same mapping.4603//Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX34604//Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX34605//Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX34606//Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX34607typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING4608{4609#if ATOM_BIG_ENDIAN4610UCHAR ucDVI_CLK_Source:2;4611UCHAR ucDVI_DATA0_Source:2;4612UCHAR ucDVI_DATA1_Source:2;4613UCHAR ucDVI_DATA2_Source:2;4614#else4615UCHAR ucDVI_DATA2_Source:2;4616UCHAR ucDVI_DATA1_Source:2;4617UCHAR ucDVI_DATA0_Source:2;4618UCHAR ucDVI_CLK_Source:2;4619#endif4620}ATOM_DVI_CONN_CHANNEL_MAPPING;46214622typedef struct _EXT_DISPLAY_PATH4623{4624USHORT usDeviceTag; //A bit vector to show what devices are supported4625USHORT usDeviceACPIEnum; //16bit device ACPI id.4626USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions4627UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT4628UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT4629USHORT usExtEncoderObjId; //external encoder object id4630union{4631UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping4632ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping;4633ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping;4634};4635UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted4636USHORT usCaps;4637USHORT usReserved;4638}EXT_DISPLAY_PATH;46394640#define NUMBER_OF_UCHAR_FOR_GUID 164641#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 746424643//usCaps4644#define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x00014645#define EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN 0x00024646#define EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK 0x007C4647#define EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 (0x01 << 2 ) //PI redriver chip4648#define EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT (0x02 << 2 ) //TI retimer chip4649#define EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 (0x03 << 2 ) //Parade DP->HDMI recoverter chip46504651465246534654typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO4655{4656ATOM_COMMON_TABLE_HEADER sHeader;4657UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string4658EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries.4659UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0.4660UCHAR uc3DStereoPinId; // use for eDP panel4661UCHAR ucRemoteDisplayConfig;4662UCHAR uceDPToLVDSRxId;4663UCHAR ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_LANE_SET value4664UCHAR Reserved[3]; // for potential expansion4665}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO;46664667//Related definitions, all records are different but they have a common header4668typedef struct _ATOM_COMMON_RECORD_HEADER4669{4670UCHAR ucRecordType; //An emun to indicate the record type4671UCHAR ucRecordSize; //The size of the whole record in byte4672}ATOM_COMMON_RECORD_HEADER;467346744675#define ATOM_I2C_RECORD_TYPE 14676#define ATOM_HPD_INT_RECORD_TYPE 24677#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 34678#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 44679#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE4680#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE4681#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 74682#define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE4683#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 94684#define ATOM_ENCODER_DVO_CF_RECORD_TYPE 104685#define ATOM_CONNECTOR_CF_RECORD_TYPE 114686#define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 124687#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 134688#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 144689#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 154690#define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table4691#define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table4692#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record4693#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 194694#define ATOM_ENCODER_CAP_RECORD_TYPE 204695#define ATOM_BRACKET_LAYOUT_RECORD_TYPE 214696#define ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE 2246974698//Must be updated when new record type is added,equal to that record definition!4699#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE47004701typedef struct _ATOM_I2C_RECORD4702{4703ATOM_COMMON_RECORD_HEADER sheader;4704ATOM_I2C_ID_CONFIG sucI2cId;4705UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC4706}ATOM_I2C_RECORD;47074708typedef struct _ATOM_HPD_INT_RECORD4709{4710ATOM_COMMON_RECORD_HEADER sheader;4711UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info4712UCHAR ucPlugged_PinState;4713}ATOM_HPD_INT_RECORD;471447154716typedef struct _ATOM_OUTPUT_PROTECTION_RECORD4717{4718ATOM_COMMON_RECORD_HEADER sheader;4719UCHAR ucProtectionFlag;4720UCHAR ucReserved;4721}ATOM_OUTPUT_PROTECTION_RECORD;47224723typedef struct _ATOM_CONNECTOR_DEVICE_TAG4724{4725ULONG ulACPIDeviceEnum; //Reserved for now4726USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT"4727USHORT usPadding;4728}ATOM_CONNECTOR_DEVICE_TAG;47294730typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD4731{4732ATOM_COMMON_RECORD_HEADER sheader;4733UCHAR ucNumberOfDevice;4734UCHAR ucReserved;4735ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT"4736}ATOM_CONNECTOR_DEVICE_TAG_RECORD;473747384739typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD4740{4741ATOM_COMMON_RECORD_HEADER sheader;4742UCHAR ucConfigGPIOID;4743UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in4744UCHAR ucFlowinGPIPID;4745UCHAR ucExtInGPIPID;4746}ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD;47474748typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD4749{4750ATOM_COMMON_RECORD_HEADER sheader;4751UCHAR ucCTL1GPIO_ID;4752UCHAR ucCTL1GPIOState; //Set to 1 when it's active high4753UCHAR ucCTL2GPIO_ID;4754UCHAR ucCTL2GPIOState; //Set to 1 when it's active high4755UCHAR ucCTL3GPIO_ID;4756UCHAR ucCTL3GPIOState; //Set to 1 when it's active high4757UCHAR ucCTLFPGA_IN_ID;4758UCHAR ucPadding[3];4759}ATOM_ENCODER_FPGA_CONTROL_RECORD;47604761typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD4762{4763ATOM_COMMON_RECORD_HEADER sheader;4764UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info4765UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected4766}ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD;47674768typedef struct _ATOM_JTAG_RECORD4769{4770ATOM_COMMON_RECORD_HEADER sheader;4771UCHAR ucTMSGPIO_ID;4772UCHAR ucTMSGPIOState; //Set to 1 when it's active high4773UCHAR ucTCKGPIO_ID;4774UCHAR ucTCKGPIOState; //Set to 1 when it's active high4775UCHAR ucTDOGPIO_ID;4776UCHAR ucTDOGPIOState; //Set to 1 when it's active high4777UCHAR ucTDIGPIO_ID;4778UCHAR ucTDIGPIOState; //Set to 1 when it's active high4779UCHAR ucPadding[2];4780}ATOM_JTAG_RECORD;478147824783//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually4784typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR4785{4786UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table4787UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin4788}ATOM_GPIO_PIN_CONTROL_PAIR;47894790typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD4791{4792ATOM_COMMON_RECORD_HEADER sheader;4793UCHAR ucFlags; // Future expnadibility4794UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object4795ATOM_GPIO_PIN_CONTROL_PAIR asGpio[]; // the real gpio pin pair determined by number of pins ucNumberOfPins4796}ATOM_OBJECT_GPIO_CNTL_RECORD;47974798//Definitions for GPIO pin state4799#define GPIO_PIN_TYPE_INPUT 0x004800#define GPIO_PIN_TYPE_OUTPUT 0x104801#define GPIO_PIN_TYPE_HW_CONTROL 0x2048024803//For GPIO_PIN_TYPE_OUTPUT the following is defined4804#define GPIO_PIN_OUTPUT_STATE_MASK 0x014805#define GPIO_PIN_OUTPUT_STATE_SHIFT 04806#define GPIO_PIN_STATE_ACTIVE_LOW 0x04807#define GPIO_PIN_STATE_ACTIVE_HIGH 0x148084809// Indexes to GPIO array in GLSync record4810// GLSync record is for Frame Lock/Gen Lock feature.4811#define ATOM_GPIO_INDEX_GLSYNC_REFCLK 04812#define ATOM_GPIO_INDEX_GLSYNC_HSYNC 14813#define ATOM_GPIO_INDEX_GLSYNC_VSYNC 24814#define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 34815#define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 44816#define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 54817#define ATOM_GPIO_INDEX_GLSYNC_V_RESET 64818#define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 74819#define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 84820#define ATOM_GPIO_INDEX_GLSYNC_MAX 948214822typedef struct _ATOM_ENCODER_DVO_CF_RECORD4823{4824ATOM_COMMON_RECORD_HEADER sheader;4825ULONG ulStrengthControl; // DVOA strength control for CF4826UCHAR ucPadding[2];4827}ATOM_ENCODER_DVO_CF_RECORD;48284829// Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap4830#define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN4831#define ATOM_ENCODER_CAP_RECORD_MST_EN 0x01 // from SI, this bit means DP MST is enable or not.4832#define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled4833#define ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN 0x04 // HDMI2.0 6Gbps enable or not.4834#define ATOM_ENCODER_CAP_RECORD_HBR3_EN 0x08 // DP1.3 HBR3 is supported by board.48354836typedef struct _ATOM_ENCODER_CAP_RECORD4837{4838ATOM_COMMON_RECORD_HEADER sheader;4839union {4840USHORT usEncoderCap;4841struct {4842#if ATOM_BIG_ENDIAN4843USHORT usReserved:14; // Bit1-15 may be defined for other capability in future4844USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable4845USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.4846#else4847USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.4848USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable4849USHORT usReserved:14; // Bit1-15 may be defined for other capability in future4850#endif4851};4852};4853}ATOM_ENCODER_CAP_RECORD;48544855// Used after SI4856typedef struct _ATOM_ENCODER_CAP_RECORD_V24857{4858ATOM_COMMON_RECORD_HEADER sheader;4859union {4860USHORT usEncoderCap;4861struct {4862#if ATOM_BIG_ENDIAN4863USHORT usReserved:12; // Bit4-15 may be defined for other capability in future4864USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable4865USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used starting from CZ( APU) Ellemere (dGPU)4866USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable4867USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable4868#else4869USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable4870USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable4871USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used starting from CZ( APU) Ellemere (dGPU)4872USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable4873USHORT usReserved:12; // Bit4-15 may be defined for other capability in future4874#endif4875};4876};4877}ATOM_ENCODER_CAP_RECORD_V2;487848794880// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle4881#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 14882#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 248834884typedef struct _ATOM_CONNECTOR_CF_RECORD4885{4886ATOM_COMMON_RECORD_HEADER sheader;4887USHORT usMaxPixClk;4888UCHAR ucFlowCntlGpioId;4889UCHAR ucSwapCntlGpioId;4890UCHAR ucConnectedDvoBundle;4891UCHAR ucPadding;4892}ATOM_CONNECTOR_CF_RECORD;48934894typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD4895{4896ATOM_COMMON_RECORD_HEADER sheader;4897ATOM_DTD_FORMAT asTiming;4898}ATOM_CONNECTOR_HARDCODE_DTD_RECORD;48994900typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD4901{4902ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE4903UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A4904UCHAR ucReserved;4905}ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD;490649074908typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD4909{4910ATOM_COMMON_RECORD_HEADER sheader;4911UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state4912UCHAR ucMuxControlPin;4913UCHAR ucMuxState[2]; //for alligment purpose4914}ATOM_ROUTER_DDC_PATH_SELECT_RECORD;49154916typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD4917{4918ATOM_COMMON_RECORD_HEADER sheader;4919UCHAR ucMuxType;4920UCHAR ucMuxControlPin;4921UCHAR ucMuxState[2]; //for alligment purpose4922}ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD;49234924// define ucMuxType4925#define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f4926#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x0149274928typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE4929{4930ATOM_COMMON_RECORD_HEADER sheader;4931UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table4932}ATOM_CONNECTOR_HPDPIN_LUT_RECORD;49334934typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE4935{4936ATOM_COMMON_RECORD_HEADER sheader;4937ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID4938}ATOM_CONNECTOR_AUXDDC_LUT_RECORD;49394940typedef struct _ATOM_OBJECT_LINK_RECORD4941{4942ATOM_COMMON_RECORD_HEADER sheader;4943USHORT usObjectID; //could be connector, encorder or other object in object.h4944}ATOM_OBJECT_LINK_RECORD;49454946typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD4947{4948ATOM_COMMON_RECORD_HEADER sheader;4949USHORT usReserved;4950}ATOM_CONNECTOR_REMOTE_CAP_RECORD;495149524953typedef struct _ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD4954{4955ATOM_COMMON_RECORD_HEADER sheader;4956// override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.54957UCHAR ucMaxTmdsClkRateIn2_5Mhz;4958UCHAR ucReserved;4959} ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD;496049614962typedef struct _ATOM_CONNECTOR_LAYOUT_INFO4963{4964USHORT usConnectorObjectId;4965UCHAR ucConnectorType;4966UCHAR ucPosition;4967}ATOM_CONNECTOR_LAYOUT_INFO;49684969// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size4970#define CONNECTOR_TYPE_DVI_D 14971#define CONNECTOR_TYPE_DVI_I 24972#define CONNECTOR_TYPE_VGA 34973#define CONNECTOR_TYPE_HDMI 44974#define CONNECTOR_TYPE_DISPLAY_PORT 54975#define CONNECTOR_TYPE_MINI_DISPLAY_PORT 649764977typedef struct _ATOM_BRACKET_LAYOUT_RECORD4978{4979ATOM_COMMON_RECORD_HEADER sheader;4980UCHAR ucLength;4981UCHAR ucWidth;4982UCHAR ucConnNum;4983UCHAR ucReserved;4984ATOM_CONNECTOR_LAYOUT_INFO asConnInfo[];4985}ATOM_BRACKET_LAYOUT_RECORD;498649874988/****************************************************************************/4989// Structure used in XXXX4990/****************************************************************************/4991typedef struct _ATOM_VOLTAGE_INFO_HEADER4992{4993USHORT usVDDCBaseLevel; //In number of 50mv unit4994USHORT usReserved; //For possible extension table offset4995UCHAR ucNumOfVoltageEntries;4996UCHAR ucBytesPerVoltageEntry;4997UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit4998UCHAR ucDefaultVoltageEntry;4999UCHAR ucVoltageControlI2cLine;5000UCHAR ucVoltageControlAddress;5001UCHAR ucVoltageControlOffset;5002}ATOM_VOLTAGE_INFO_HEADER;50035004typedef struct _ATOM_VOLTAGE_INFO5005{5006ATOM_COMMON_TABLE_HEADER sHeader;5007ATOM_VOLTAGE_INFO_HEADER viHeader;5008UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry5009}ATOM_VOLTAGE_INFO;501050115012typedef struct _ATOM_VOLTAGE_FORMULA5013{5014USHORT usVoltageBaseLevel; // In number of 1mv unit5015USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit5016UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage5017UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv5018UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep5019UCHAR ucReserved;5020UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries5021}ATOM_VOLTAGE_FORMULA;50225023typedef struct _VOLTAGE_LUT_ENTRY5024{5025USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code5026USHORT usVoltageValue; // The corresponding Voltage Value, in mV5027}VOLTAGE_LUT_ENTRY;50285029typedef struct _ATOM_VOLTAGE_FORMULA_V25030{5031UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage5032UCHAR ucReserved[3];5033VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries5034}ATOM_VOLTAGE_FORMULA_V2;50355036typedef struct _ATOM_VOLTAGE_CONTROL5037{5038UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine5039UCHAR ucVoltageControlI2cLine;5040UCHAR ucVoltageControlAddress;5041UCHAR ucVoltageControlOffset;5042USHORT usGpioPin_AIndex; //GPIO_PAD register index5043UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff5044UCHAR ucReserved;5045}ATOM_VOLTAGE_CONTROL;50465047// Define ucVoltageControlId5048#define VOLTAGE_CONTROLLED_BY_HW 0x005049#define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F5050#define VOLTAGE_CONTROLLED_BY_GPIO 0x805051#define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage5052#define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI5053#define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage5054#define VOLTAGE_CONTROL_ID_DS4402 0x045055#define VOLTAGE_CONTROL_ID_UP6266 0x055056#define VOLTAGE_CONTROL_ID_SCORPIO 0x065057#define VOLTAGE_CONTROL_ID_VT1556M 0x075058#define VOLTAGE_CONTROL_ID_CHL822x 0x085059#define VOLTAGE_CONTROL_ID_VT1586M 0x095060#define VOLTAGE_CONTROL_ID_UP1637 0x0A5061#define VOLTAGE_CONTROL_ID_CHL8214 0x0B5062#define VOLTAGE_CONTROL_ID_UP1801 0x0C5063#define VOLTAGE_CONTROL_ID_ST6788A 0x0D5064#define VOLTAGE_CONTROL_ID_CHLIR3564SVI2 0x0E5065#define VOLTAGE_CONTROL_ID_AD527x 0x0F5066#define VOLTAGE_CONTROL_ID_NCP81022 0x105067#define VOLTAGE_CONTROL_ID_LTC2635 0x115068#define VOLTAGE_CONTROL_ID_NCP4208 0x125069#define VOLTAGE_CONTROL_ID_IR35xx 0x135070#define VOLTAGE_CONTROL_ID_RT9403 0x1450715072#define VOLTAGE_CONTROL_ID_GENERIC_I2C 0x4050735074typedef struct _ATOM_VOLTAGE_OBJECT5075{5076UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI5077UCHAR ucSize; //Size of Object5078ATOM_VOLTAGE_CONTROL asControl; //describ how to control5079ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID5080}ATOM_VOLTAGE_OBJECT;50815082typedef struct _ATOM_VOLTAGE_OBJECT_V25083{5084UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI5085UCHAR ucSize; //Size of Object5086ATOM_VOLTAGE_CONTROL asControl; //describ how to control5087ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID5088}ATOM_VOLTAGE_OBJECT_V2;50895090typedef struct _ATOM_VOLTAGE_OBJECT_INFO5091{5092ATOM_COMMON_TABLE_HEADER sHeader;5093ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control5094}ATOM_VOLTAGE_OBJECT_INFO;50955096typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V25097{5098ATOM_COMMON_TABLE_HEADER sHeader;5099ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control5100}ATOM_VOLTAGE_OBJECT_INFO_V2;51015102typedef struct _ATOM_LEAKID_VOLTAGE5103{5104UCHAR ucLeakageId;5105UCHAR ucReserved;5106USHORT usVoltage;5107}ATOM_LEAKID_VOLTAGE;51085109typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{5110UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI5111UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase5112USHORT usSize; //Size of Object5113}ATOM_VOLTAGE_OBJECT_HEADER_V3;51145115// ATOM_VOLTAGE_OBJECT_HEADER_V3.ucVoltageMode5116#define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V35117#define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V35118#define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V35119#define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V35120#define VOLTAGE_OBJ_EVV 85121#define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V35122#define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V35123#define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V351245125typedef struct _VOLTAGE_LUT_ENTRY_V25126{5127ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register5128USHORT usVoltageValue; // The corresponding Voltage Value, in mV5129}VOLTAGE_LUT_ENTRY_V2;51305131typedef struct _LEAKAGE_VOLTAGE_LUT_ENTRY_V25132{5133USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register5134USHORT usVoltageId;5135USHORT usLeakageId; // The corresponding Voltage Value, in mV5136}LEAKAGE_VOLTAGE_LUT_ENTRY_V2;513751385139typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V35140{5141ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ5142UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id5143UCHAR ucVoltageControlI2cLine;5144UCHAR ucVoltageControlAddress;5145UCHAR ucVoltageControlOffset;5146UCHAR ucVoltageControlFlag; // Bit0: 0 - One byte data; 1 - Two byte data5147UCHAR ulReserved[3];5148VOLTAGE_LUT_ENTRY asVolI2cLut[]; // end with 0xff5149}ATOM_I2C_VOLTAGE_OBJECT_V3;51505151// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag5152#define VOLTAGE_DATA_ONE_BYTE 05153#define VOLTAGE_DATA_TWO_BYTE 151545155typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V35156{5157ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT5158UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode5159UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table5160UCHAR ucPhaseDelay; // phase delay in unit of micro second5161UCHAR ucReserved;5162ULONG ulGpioMaskVal; // GPIO Mask value5163VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[];5164}ATOM_GPIO_VOLTAGE_OBJECT_V3;51655166typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V35167{5168ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = 0x10/0x11/0x125169UCHAR ucLeakageCntlId; // default is 05170UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table5171UCHAR ucReserved[2];5172ULONG ulMaxVoltageLevel;5173LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[];5174}ATOM_LEAKAGE_VOLTAGE_OBJECT_V3;517551765177typedef struct _ATOM_SVID2_VOLTAGE_OBJECT_V35178{5179ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID25180// 14:7 - PSI0_VID5181// 6 - PSI0_EN5182// 5 - PSI15183// 4:2 - load line slope trim.5184// 1:0 - offset trim,5185USHORT usLoadLine_PSI;5186// GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO315187UCHAR ucSVDGpioId; //0~31 indicate GPIO0~315188UCHAR ucSVCGpioId; //0~31 indicate GPIO0~315189ULONG ulReserved;5190}ATOM_SVID2_VOLTAGE_OBJECT_V3;5191519251935194typedef struct _ATOM_MERGED_VOLTAGE_OBJECT_V35195{5196ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_MERGED_POWER5197UCHAR ucMergedVType; // VDDC/VDCCI/....5198UCHAR ucReserved[3];5199}ATOM_MERGED_VOLTAGE_OBJECT_V3;520052015202typedef struct _ATOM_EVV_DPM_INFO5203{5204ULONG ulDPMSclk; // DPM state SCLK5205USHORT usVAdjOffset; // Adjust Voltage offset in unit of mv5206UCHAR ucDPMTblVIndex; // Voltage Index in SMC_DPM_Table structure VddcTable/VddGfxTable5207UCHAR ucDPMState; // DPMState0~75208} ATOM_EVV_DPM_INFO;52095210// ucVoltageMode = VOLTAGE_OBJ_EVV5211typedef struct _ATOM_EVV_VOLTAGE_OBJECT_V35212{5213ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID25214ATOM_EVV_DPM_INFO asEvvDpmList[8];5215}ATOM_EVV_VOLTAGE_OBJECT_V3;521652175218typedef union _ATOM_VOLTAGE_OBJECT_V3{5219ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj;5220ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj;5221ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj;5222ATOM_SVID2_VOLTAGE_OBJECT_V3 asSVID2Obj;5223ATOM_EVV_VOLTAGE_OBJECT_V3 asEvvObj;5224}ATOM_VOLTAGE_OBJECT_V3;52255226typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_15227{5228ATOM_COMMON_TABLE_HEADER sHeader;5229ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control5230}ATOM_VOLTAGE_OBJECT_INFO_V3_1;523152325233typedef struct _ATOM_ASIC_PROFILE_VOLTAGE5234{5235UCHAR ucProfileId;5236UCHAR ucReserved;5237USHORT usSize;5238USHORT usEfuseSpareStartAddr;5239USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id,5240ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage5241}ATOM_ASIC_PROFILE_VOLTAGE;52425243//ucProfileId5244#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 15245#define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 15246#define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 252475248typedef struct _ATOM_ASIC_PROFILING_INFO5249{5250ATOM_COMMON_TABLE_HEADER asHeader;5251ATOM_ASIC_PROFILE_VOLTAGE asVoltage;5252}ATOM_ASIC_PROFILING_INFO;52535254typedef struct _ATOM_ASIC_PROFILING_INFO_V2_15255{5256ATOM_COMMON_TABLE_HEADER asHeader;5257UCHAR ucLeakageBinNum; // indicate the entry number of LeakageId/Voltage Lut table5258USHORT usLeakageBinArrayOffset; // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher)52595260UCHAR ucElbVDDC_Num;5261USHORT usElbVDDC_IdArrayOffset; // offset of USHORT virtual VDDC voltage id ( 0xff01~0xff08 )5262USHORT usElbVDDC_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array52635264UCHAR ucElbVDDCI_Num;5265USHORT usElbVDDCI_IdArrayOffset; // offset of USHORT virtual VDDCI voltage id ( 0xff01~0xff08 )5266USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array5267}ATOM_ASIC_PROFILING_INFO_V2_1;526852695270//Here is parameter to convert Efuse value to Measure value5271//Measured = LN((2^Bitsize-1)/EFUSE-1)*(Range)/(-alpha)+(Max+Min)/25272typedef struct _EFUSE_LOGISTIC_FUNC_PARAM5273{5274USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=1125275UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=155276UCHAR ucEfuseLength; // Efuse bits length,5277ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number5278ULONG ulEfuseEncodeAverage; // Average = ( Max + Min )/25279}EFUSE_LOGISTIC_FUNC_PARAM;52805281//Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min )5282typedef struct _EFUSE_LINEAR_FUNC_PARAM5283{5284USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=1125285UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=155286UCHAR ucEfuseLength; // Efuse bits length,5287ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number5288ULONG ulEfuseMin; // Min5289}EFUSE_LINEAR_FUNC_PARAM;529052915292typedef struct _ATOM_ASIC_PROFILING_INFO_V3_15293{5294ATOM_COMMON_TABLE_HEADER asHeader;5295ULONG ulEvvDerateTdp;5296ULONG ulEvvDerateTdc;5297ULONG ulBoardCoreTemp;5298ULONG ulMaxVddc;5299ULONG ulMinVddc;5300ULONG ulLoadLineSlop;5301ULONG ulLeakageTemp;5302ULONG ulLeakageVoltage;5303EFUSE_LINEAR_FUNC_PARAM sCACm;5304EFUSE_LINEAR_FUNC_PARAM sCACb;5305EFUSE_LOGISTIC_FUNC_PARAM sKt_b;5306EFUSE_LOGISTIC_FUNC_PARAM sKv_m;5307EFUSE_LOGISTIC_FUNC_PARAM sKv_b;5308USHORT usLkgEuseIndex;5309UCHAR ucLkgEfuseBitLSB;5310UCHAR ucLkgEfuseLength;5311ULONG ulLkgEncodeLn_MaxDivMin;5312ULONG ulLkgEncodeMax;5313ULONG ulLkgEncodeMin;5314ULONG ulEfuseLogisticAlpha;5315USHORT usPowerDpm0;5316USHORT usCurrentDpm0;5317USHORT usPowerDpm1;5318USHORT usCurrentDpm1;5319USHORT usPowerDpm2;5320USHORT usCurrentDpm2;5321USHORT usPowerDpm3;5322USHORT usCurrentDpm3;5323USHORT usPowerDpm4;5324USHORT usCurrentDpm4;5325USHORT usPowerDpm5;5326USHORT usCurrentDpm5;5327USHORT usPowerDpm6;5328USHORT usCurrentDpm6;5329USHORT usPowerDpm7;5330USHORT usCurrentDpm7;5331}ATOM_ASIC_PROFILING_INFO_V3_1;533253335334typedef struct _ATOM_ASIC_PROFILING_INFO_V3_25335{5336ATOM_COMMON_TABLE_HEADER asHeader;5337ULONG ulEvvLkgFactor;5338ULONG ulBoardCoreTemp;5339ULONG ulMaxVddc;5340ULONG ulMinVddc;5341ULONG ulLoadLineSlop;5342ULONG ulLeakageTemp;5343ULONG ulLeakageVoltage;5344EFUSE_LINEAR_FUNC_PARAM sCACm;5345EFUSE_LINEAR_FUNC_PARAM sCACb;5346EFUSE_LOGISTIC_FUNC_PARAM sKt_b;5347EFUSE_LOGISTIC_FUNC_PARAM sKv_m;5348EFUSE_LOGISTIC_FUNC_PARAM sKv_b;5349USHORT usLkgEuseIndex;5350UCHAR ucLkgEfuseBitLSB;5351UCHAR ucLkgEfuseLength;5352ULONG ulLkgEncodeLn_MaxDivMin;5353ULONG ulLkgEncodeMax;5354ULONG ulLkgEncodeMin;5355ULONG ulEfuseLogisticAlpha;5356USHORT usPowerDpm0;5357USHORT usPowerDpm1;5358USHORT usPowerDpm2;5359USHORT usPowerDpm3;5360USHORT usPowerDpm4;5361USHORT usPowerDpm5;5362USHORT usPowerDpm6;5363USHORT usPowerDpm7;5364ULONG ulTdpDerateDPM0;5365ULONG ulTdpDerateDPM1;5366ULONG ulTdpDerateDPM2;5367ULONG ulTdpDerateDPM3;5368ULONG ulTdpDerateDPM4;5369ULONG ulTdpDerateDPM5;5370ULONG ulTdpDerateDPM6;5371ULONG ulTdpDerateDPM7;5372}ATOM_ASIC_PROFILING_INFO_V3_2;537353745375// for Tonga/Fiji speed EVV algorithm5376typedef struct _ATOM_ASIC_PROFILING_INFO_V3_35377{5378ATOM_COMMON_TABLE_HEADER asHeader;5379ULONG ulEvvLkgFactor;5380ULONG ulBoardCoreTemp;5381ULONG ulMaxVddc;5382ULONG ulMinVddc;5383ULONG ulLoadLineSlop;5384ULONG ulLeakageTemp;5385ULONG ulLeakageVoltage;5386EFUSE_LINEAR_FUNC_PARAM sCACm;5387EFUSE_LINEAR_FUNC_PARAM sCACb;5388EFUSE_LOGISTIC_FUNC_PARAM sKt_b;5389EFUSE_LOGISTIC_FUNC_PARAM sKv_m;5390EFUSE_LOGISTIC_FUNC_PARAM sKv_b;5391USHORT usLkgEuseIndex;5392UCHAR ucLkgEfuseBitLSB;5393UCHAR ucLkgEfuseLength;5394ULONG ulLkgEncodeLn_MaxDivMin;5395ULONG ulLkgEncodeMax;5396ULONG ulLkgEncodeMin;5397ULONG ulEfuseLogisticAlpha;53985399union{5400USHORT usPowerDpm0;5401USHORT usParamNegFlag; //bit0 =1 :indicate ulRoBeta is Negative, bit1=1 indicate Kv_m max is postive5402};5403USHORT usPowerDpm1;5404USHORT usPowerDpm2;5405USHORT usPowerDpm3;5406USHORT usPowerDpm4;5407USHORT usPowerDpm5;5408USHORT usPowerDpm6;5409USHORT usPowerDpm7;5410ULONG ulTdpDerateDPM0;5411ULONG ulTdpDerateDPM1;5412ULONG ulTdpDerateDPM2;5413ULONG ulTdpDerateDPM3;5414ULONG ulTdpDerateDPM4;5415ULONG ulTdpDerateDPM5;5416ULONG ulTdpDerateDPM6;5417ULONG ulTdpDerateDPM7;5418EFUSE_LINEAR_FUNC_PARAM sRoFuse;5419ULONG ulRoAlpha;5420ULONG ulRoBeta;5421ULONG ulRoGamma;5422ULONG ulRoEpsilon;5423ULONG ulATermRo;5424ULONG ulBTermRo;5425ULONG ulCTermRo;5426ULONG ulSclkMargin;5427ULONG ulFmaxPercent;5428ULONG ulCRPercent;5429ULONG ulSFmaxPercent;5430ULONG ulSCRPercent;5431ULONG ulSDCMargine;5432}ATOM_ASIC_PROFILING_INFO_V3_3;54335434// for Fiji speed EVV algorithm5435typedef struct _ATOM_ASIC_PROFILING_INFO_V3_45436{5437ATOM_COMMON_TABLE_HEADER asHeader;5438ULONG ulEvvLkgFactor;5439ULONG ulBoardCoreTemp;5440ULONG ulMaxVddc;5441ULONG ulMinVddc;5442ULONG ulLoadLineSlop;5443ULONG ulLeakageTemp;5444ULONG ulLeakageVoltage;5445EFUSE_LINEAR_FUNC_PARAM sCACm;5446EFUSE_LINEAR_FUNC_PARAM sCACb;5447EFUSE_LOGISTIC_FUNC_PARAM sKt_b;5448EFUSE_LOGISTIC_FUNC_PARAM sKv_m;5449EFUSE_LOGISTIC_FUNC_PARAM sKv_b;5450USHORT usLkgEuseIndex;5451UCHAR ucLkgEfuseBitLSB;5452UCHAR ucLkgEfuseLength;5453ULONG ulLkgEncodeLn_MaxDivMin;5454ULONG ulLkgEncodeMax;5455ULONG ulLkgEncodeMin;5456ULONG ulEfuseLogisticAlpha;5457USHORT usPowerDpm0;5458USHORT usPowerDpm1;5459USHORT usPowerDpm2;5460USHORT usPowerDpm3;5461USHORT usPowerDpm4;5462USHORT usPowerDpm5;5463USHORT usPowerDpm6;5464USHORT usPowerDpm7;5465ULONG ulTdpDerateDPM0;5466ULONG ulTdpDerateDPM1;5467ULONG ulTdpDerateDPM2;5468ULONG ulTdpDerateDPM3;5469ULONG ulTdpDerateDPM4;5470ULONG ulTdpDerateDPM5;5471ULONG ulTdpDerateDPM6;5472ULONG ulTdpDerateDPM7;5473EFUSE_LINEAR_FUNC_PARAM sRoFuse;5474ULONG ulEvvDefaultVddc;5475ULONG ulEvvNoCalcVddc;5476USHORT usParamNegFlag;5477USHORT usSpeed_Model;5478ULONG ulSM_A0;5479ULONG ulSM_A1;5480ULONG ulSM_A2;5481ULONG ulSM_A3;5482ULONG ulSM_A4;5483ULONG ulSM_A5;5484ULONG ulSM_A6;5485ULONG ulSM_A7;5486UCHAR ucSM_A0_sign;5487UCHAR ucSM_A1_sign;5488UCHAR ucSM_A2_sign;5489UCHAR ucSM_A3_sign;5490UCHAR ucSM_A4_sign;5491UCHAR ucSM_A5_sign;5492UCHAR ucSM_A6_sign;5493UCHAR ucSM_A7_sign;5494ULONG ulMargin_RO_a;5495ULONG ulMargin_RO_b;5496ULONG ulMargin_RO_c;5497ULONG ulMargin_fixed;5498ULONG ulMargin_Fmax_mean;5499ULONG ulMargin_plat_mean;5500ULONG ulMargin_Fmax_sigma;5501ULONG ulMargin_plat_sigma;5502ULONG ulMargin_DC_sigma;5503ULONG ulReserved[8]; // Reserved for future ASIC5504}ATOM_ASIC_PROFILING_INFO_V3_4;55055506// for Polaris10/Polaris11 speed EVV algorithm5507typedef struct _ATOM_ASIC_PROFILING_INFO_V3_55508{5509ATOM_COMMON_TABLE_HEADER asHeader;5510ULONG ulMaxVddc; //Maximum voltage for all parts, in unit of 0.01mv5511ULONG ulMinVddc; //Minimum voltage for all parts, in unit of 0.01mv5512USHORT usLkgEuseIndex; //Efuse Lkg_FT address ( BYTE address )5513UCHAR ucLkgEfuseBitLSB; //Efuse Lkg_FT bit shift in 32bit DWORD5514UCHAR ucLkgEfuseLength; //Efuse Lkg_FT length5515ULONG ulLkgEncodeLn_MaxDivMin; //value of ln(Max_Lkg_Ft/Min_Lkg_Ft ) in unit of 0.00001 ( unit=100000 )5516ULONG ulLkgEncodeMax; //Maximum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 )5517ULONG ulLkgEncodeMin; //Minimum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 )5518EFUSE_LINEAR_FUNC_PARAM sRoFuse;//Efuse RO info: DWORD address, bit shift, length, max/min measure value. in unit of 1.5519ULONG ulEvvDefaultVddc; //def="EVV_DEFAULT_VDDC" descr="return default VDDC(v) when Efuse not cut" unit="100000"/>5520ULONG ulEvvNoCalcVddc; //def="EVV_NOCALC_VDDC" descr="return VDDC(v) when Calculation is bad" unit="100000"/>5521ULONG ulSpeed_Model; //def="EVV_SPEED_MODEL" descr="0 = Greek model, 1 = multivariate model" unit="1"/>5522ULONG ulSM_A0; //def="EVV_SM_A0" descr="Leakage coeff(Multivariant Mode)." unit="100000"/>5523ULONG ulSM_A1; //def="EVV_SM_A1" descr="Leakage/SCLK coeff(Multivariant Mode)." unit="1000000"/>5524ULONG ulSM_A2; //def="EVV_SM_A2" descr="Alpha( Greek Mode ) or VDDC/SCLK coeff(Multivariant Mode)." unit="100000"/>5525ULONG ulSM_A3; //def="EVV_SM_A3" descr="Beta( Greek Mode ) or SCLK coeff(Multivariant Mode)." unit="100000"/>5526ULONG ulSM_A4; //def="EVV_SM_A4" descr="VDDC^2/SCLK coeff(Multivariant Mode)." unit="100000"/>5527ULONG ulSM_A5; //def="EVV_SM_A5" descr="VDDC^2 coeff(Multivariant Mode)." unit="100000"/>5528ULONG ulSM_A6; //def="EVV_SM_A6" descr="Gamma( Greek Mode ) or VDDC coeff(Multivariant Mode)." unit="100000"/>5529ULONG ulSM_A7; //def="EVV_SM_A7" descr="Epsilon( Greek Mode ) or constant(Multivariant Mode)." unit="100000"/>5530UCHAR ucSM_A0_sign; //def="EVV_SM_A0_SIGN" descr="=0 SM_A0 is postive. =1: SM_A0 is negative" unit="1"/>5531UCHAR ucSM_A1_sign; //def="EVV_SM_A1_SIGN" descr="=0 SM_A1 is postive. =1: SM_A1 is negative" unit="1"/>5532UCHAR ucSM_A2_sign; //def="EVV_SM_A2_SIGN" descr="=0 SM_A2 is postive. =1: SM_A2 is negative" unit="1"/>5533UCHAR ucSM_A3_sign; //def="EVV_SM_A3_SIGN" descr="=0 SM_A3 is postive. =1: SM_A3 is negative" unit="1"/>5534UCHAR ucSM_A4_sign; //def="EVV_SM_A4_SIGN" descr="=0 SM_A4 is postive. =1: SM_A4 is negative" unit="1"/>5535UCHAR ucSM_A5_sign; //def="EVV_SM_A5_SIGN" descr="=0 SM_A5 is postive. =1: SM_A5 is negative" unit="1"/>5536UCHAR ucSM_A6_sign; //def="EVV_SM_A6_SIGN" descr="=0 SM_A6 is postive. =1: SM_A6 is negative" unit="1"/>5537UCHAR ucSM_A7_sign; //def="EVV_SM_A7_SIGN" descr="=0 SM_A7 is postive. =1: SM_A7 is negative" unit="1"/>5538ULONG ulMargin_RO_a; //def="EVV_MARGIN_RO_A" descr="A Term to represent RO equation in Ax2+Bx+C, unit=1"5539ULONG ulMargin_RO_b; //def="EVV_MARGIN_RO_B" descr="B Term to represent RO equation in Ax2+Bx+C, unit=1"5540ULONG ulMargin_RO_c; //def="EVV_MARGIN_RO_C" descr="C Term to represent RO equation in Ax2+Bx+C, unit=1"5541ULONG ulMargin_fixed; //def="EVV_MARGIN_FIXED" descr="Fixed MHz to add to SCLK margin, unit=1" unit="1"/>5542ULONG ulMargin_Fmax_mean; //def="EVV_MARGIN_FMAX_MEAN" descr="Percentage to add for Fmas mean margin unit=10000" unit="10000"/>5543ULONG ulMargin_plat_mean; //def="EVV_MARGIN_PLAT_MEAN" descr="Percentage to add for platform mean margin unit=10000" unit="10000"/>5544ULONG ulMargin_Fmax_sigma; //def="EVV_MARGIN_FMAX_SIGMA" descr="Percentage to add for Fmax sigma margin unit=10000" unit="10000"/>5545ULONG ulMargin_plat_sigma; //def="EVV_MARGIN_PLAT_SIGMA" descr="Percentage to add for platform sigma margin unit=10000" unit="10000"/>5546ULONG ulMargin_DC_sigma; //def="EVV_MARGIN_DC_SIGMA" descr="Regulator DC tolerance margin (mV) unit=100" unit="100"/>5547ULONG ulReserved[12];5548}ATOM_ASIC_PROFILING_INFO_V3_5;55495550/* for Polars10/11 AVFS parameters */5551typedef struct _ATOM_ASIC_PROFILING_INFO_V3_65552{5553ATOM_COMMON_TABLE_HEADER asHeader;5554ULONG ulMaxVddc;5555ULONG ulMinVddc;5556USHORT usLkgEuseIndex;5557UCHAR ucLkgEfuseBitLSB;5558UCHAR ucLkgEfuseLength;5559ULONG ulLkgEncodeLn_MaxDivMin;5560ULONG ulLkgEncodeMax;5561ULONG ulLkgEncodeMin;5562EFUSE_LINEAR_FUNC_PARAM sRoFuse;5563ULONG ulEvvDefaultVddc;5564ULONG ulEvvNoCalcVddc;5565ULONG ulSpeed_Model;5566ULONG ulSM_A0;5567ULONG ulSM_A1;5568ULONG ulSM_A2;5569ULONG ulSM_A3;5570ULONG ulSM_A4;5571ULONG ulSM_A5;5572ULONG ulSM_A6;5573ULONG ulSM_A7;5574UCHAR ucSM_A0_sign;5575UCHAR ucSM_A1_sign;5576UCHAR ucSM_A2_sign;5577UCHAR ucSM_A3_sign;5578UCHAR ucSM_A4_sign;5579UCHAR ucSM_A5_sign;5580UCHAR ucSM_A6_sign;5581UCHAR ucSM_A7_sign;5582ULONG ulMargin_RO_a;5583ULONG ulMargin_RO_b;5584ULONG ulMargin_RO_c;5585ULONG ulMargin_fixed;5586ULONG ulMargin_Fmax_mean;5587ULONG ulMargin_plat_mean;5588ULONG ulMargin_Fmax_sigma;5589ULONG ulMargin_plat_sigma;5590ULONG ulMargin_DC_sigma;5591ULONG ulLoadLineSlop;5592ULONG ulaTDClimitPerDPM[8];5593ULONG ulaNoCalcVddcPerDPM[8];5594ULONG ulAVFS_meanNsigma_Acontant0;5595ULONG ulAVFS_meanNsigma_Acontant1;5596ULONG ulAVFS_meanNsigma_Acontant2;5597USHORT usAVFS_meanNsigma_DC_tol_sigma;5598USHORT usAVFS_meanNsigma_Platform_mean;5599USHORT usAVFS_meanNsigma_Platform_sigma;5600ULONG ulGB_VDROOP_TABLE_CKSOFF_a0;5601ULONG ulGB_VDROOP_TABLE_CKSOFF_a1;5602ULONG ulGB_VDROOP_TABLE_CKSOFF_a2;5603ULONG ulGB_VDROOP_TABLE_CKSON_a0;5604ULONG ulGB_VDROOP_TABLE_CKSON_a1;5605ULONG ulGB_VDROOP_TABLE_CKSON_a2;5606ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_m1;5607USHORT usAVFSGB_FUSE_TABLE_CKSOFF_m2;5608ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_b;5609ULONG ulAVFSGB_FUSE_TABLE_CKSON_m1;5610USHORT usAVFSGB_FUSE_TABLE_CKSON_m2;5611ULONG ulAVFSGB_FUSE_TABLE_CKSON_b;5612USHORT usMaxVoltage_0_25mv;5613UCHAR ucEnableGB_VDROOP_TABLE_CKSOFF;5614UCHAR ucEnableGB_VDROOP_TABLE_CKSON;5615UCHAR ucEnableGB_FUSE_TABLE_CKSOFF;5616UCHAR ucEnableGB_FUSE_TABLE_CKSON;5617USHORT usPSM_Age_ComFactor;5618UCHAR ucEnableApplyAVFS_CKS_OFF_Voltage;5619UCHAR ucReserved;5620}ATOM_ASIC_PROFILING_INFO_V3_6;562156225623typedef struct _ATOM_SCLK_FCW_RANGE_ENTRY_V1{5624ULONG ulMaxSclkFreq;5625UCHAR ucVco_setting; // 1: 3-6GHz, 3: 2-4GHz5626UCHAR ucPostdiv; // divide by 2^n5627USHORT ucFcw_pcc;5628USHORT ucFcw_trans_upper;5629USHORT ucRcw_trans_lower;5630}ATOM_SCLK_FCW_RANGE_ENTRY_V1;563156325633// SMU_InfoTable for Polaris10/Polaris115634typedef struct _ATOM_SMU_INFO_V2_15635{5636ATOM_COMMON_TABLE_HEADER asHeader;5637UCHAR ucSclkEntryNum; // for potential future extend, indicate the number of ATOM_SCLK_FCW_RANGE_ENTRY_V15638UCHAR ucSMUVer;5639UCHAR ucSharePowerSource;5640UCHAR ucReserved;5641ATOM_SCLK_FCW_RANGE_ENTRY_V1 asSclkFcwRangeEntry[8];5642}ATOM_SMU_INFO_V2_1;564356445645// GFX_InfoTable for Polaris10/Polaris115646typedef struct _ATOM_GFX_INFO_V2_15647{5648ATOM_COMMON_TABLE_HEADER asHeader;5649UCHAR GfxIpMinVer;5650UCHAR GfxIpMajVer;5651UCHAR max_shader_engines;5652UCHAR max_tile_pipes;5653UCHAR max_cu_per_sh;5654UCHAR max_sh_per_se;5655UCHAR max_backends_per_se;5656UCHAR max_texture_channel_caches;5657}ATOM_GFX_INFO_V2_1;56585659typedef struct _ATOM_GFX_INFO_V2_35660{5661ATOM_COMMON_TABLE_HEADER asHeader;5662UCHAR GfxIpMinVer;5663UCHAR GfxIpMajVer;5664UCHAR max_shader_engines;5665UCHAR max_tile_pipes;5666UCHAR max_cu_per_sh;5667UCHAR max_sh_per_se;5668UCHAR max_backends_per_se;5669UCHAR max_texture_channel_caches;5670USHORT usHiLoLeakageThreshold;5671USHORT usEdcDidtLoDpm7TableOffset; //offset of DPM7 low leakage table _ATOM_EDC_DIDT_TABLE_V15672USHORT usEdcDidtHiDpm7TableOffset; //offset of DPM7 high leakage table _ATOM_EDC_DIDT_TABLE_V15673USHORT usReserverd[3];5674}ATOM_GFX_INFO_V2_3;56755676typedef struct _ATOM_POWER_SOURCE_OBJECT5677{5678UCHAR ucPwrSrcId; // Power source5679UCHAR ucPwrSensorType; // GPIO, I2C or none5680UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id5681UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect5682UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect5683UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect5684UCHAR ucPwrSensActiveState; // high active or low active5685UCHAR ucReserve[3]; // reserve5686USHORT usSensPwr; // in unit of watt5687}ATOM_POWER_SOURCE_OBJECT;56885689typedef struct _ATOM_POWER_SOURCE_INFO5690{5691ATOM_COMMON_TABLE_HEADER asHeader;5692UCHAR asPwrbehave[16];5693ATOM_POWER_SOURCE_OBJECT asPwrObj[1];5694}ATOM_POWER_SOURCE_INFO;569556965697//Define ucPwrSrcId5698#define POWERSOURCE_PCIE_ID1 0x005699#define POWERSOURCE_6PIN_CONNECTOR_ID1 0x015700#define POWERSOURCE_8PIN_CONNECTOR_ID1 0x025701#define POWERSOURCE_6PIN_CONNECTOR_ID2 0x045702#define POWERSOURCE_8PIN_CONNECTOR_ID2 0x0857035704//define ucPwrSensorId5705#define POWER_SENSOR_ALWAYS 0x005706#define POWER_SENSOR_GPIO 0x015707#define POWER_SENSOR_I2C 0x0257085709typedef struct _ATOM_CLK_VOLT_CAPABILITY5710{5711ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table5712ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz5713}ATOM_CLK_VOLT_CAPABILITY;571457155716typedef struct _ATOM_CLK_VOLT_CAPABILITY_V25717{5718USHORT usVoltageLevel; // The real Voltage Level round up value in unit of mv,5719ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz5720}ATOM_CLK_VOLT_CAPABILITY_V2;57215722typedef struct _ATOM_AVAILABLE_SCLK_LIST5723{5724ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz5725USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK5726USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK5727}ATOM_AVAILABLE_SCLK_LIST;57285729// ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition5730#define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0]57315732// this IntegrateSystemInfoTable is used for Liano/Ontario APU5733typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V65734{5735ATOM_COMMON_TABLE_HEADER sHeader;5736ULONG ulBootUpEngineClock;5737ULONG ulDentistVCOFreq;5738ULONG ulBootUpUMAClock;5739ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];5740ULONG ulBootUpReqDisplayVector;5741ULONG ulOtherDisplayMisc;5742ULONG ulGPUCapInfo;5743ULONG ulSB_MMIO_Base_Addr;5744USHORT usRequestedPWMFreqInHz;5745UCHAR ucHtcTmpLmt;5746UCHAR ucHtcHystLmt;5747ULONG ulMinEngineClock;5748ULONG ulSystemConfig;5749ULONG ulCPUCapInfo;5750USHORT usNBP0Voltage;5751USHORT usNBP1Voltage;5752USHORT usBootUpNBVoltage;5753USHORT usExtDispConnInfoOffset;5754USHORT usPanelRefreshRateRange;5755UCHAR ucMemoryType;5756UCHAR ucUMAChannelNumber;5757ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];5758ULONG ulCSR_M3_ARB_CNTL_UVD[10];5759ULONG ulCSR_M3_ARB_CNTL_FS3D[10];5760ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5];5761ULONG ulGMCRestoreResetTime;5762ULONG ulMinimumNClk;5763ULONG ulIdleNClk;5764ULONG ulDDR_DLL_PowerUpTime;5765ULONG ulDDR_PLL_PowerUpTime;5766USHORT usPCIEClkSSPercentage;5767USHORT usPCIEClkSSType;5768USHORT usLvdsSSPercentage;5769USHORT usLvdsSSpreadRateIn10Hz;5770USHORT usHDMISSPercentage;5771USHORT usHDMISSpreadRateIn10Hz;5772USHORT usDVISSPercentage;5773USHORT usDVISSpreadRateIn10Hz;5774ULONG SclkDpmBoostMargin;5775ULONG SclkDpmThrottleMargin;5776USHORT SclkDpmTdpLimitPG;5777USHORT SclkDpmTdpLimitBoost;5778ULONG ulBoostEngineCLock;5779UCHAR ulBoostVid_2bit;5780UCHAR EnableBoost;5781USHORT GnbTdpLimit;5782USHORT usMaxLVDSPclkFreqInSingleLink;5783UCHAR ucLvdsMisc;5784UCHAR ucLVDSReserved;5785ULONG ulReserved3[15];5786ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;5787}ATOM_INTEGRATED_SYSTEM_INFO_V6;57885789// ulGPUCapInfo5790#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x015791#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x0857925793//ucLVDSMisc:5794#define SYS_INFO_LVDSMISC__888_FPDI_MODE 0x015795#define SYS_INFO_LVDSMISC__DL_CH_SWAP 0x025796#define SYS_INFO_LVDSMISC__888_BPC 0x045797#define SYS_INFO_LVDSMISC__OVERRIDE_EN 0x085798#define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW 0x105799// new since Trinity5800#define SYS_INFO_LVDSMISC__TRAVIS_LVDS_VOL_OVERRIDE_EN 0x2058015802// not used any more5803#define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW 0x045804#define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW 0x0858055806/**********************************************************************************************************************5807ATOM_INTEGRATED_SYSTEM_INFO_V6 Description5808ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock5809ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.5810ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.5811sDISPCLK_Voltage: Report Display clock voltage requirement.58125813ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects:5814ATOM_DEVICE_CRT1_SUPPORT 0x00015815ATOM_DEVICE_CRT2_SUPPORT 0x00105816ATOM_DEVICE_DFP1_SUPPORT 0x00085817ATOM_DEVICE_DFP6_SUPPORT 0x00405818ATOM_DEVICE_DFP2_SUPPORT 0x00805819ATOM_DEVICE_DFP3_SUPPORT 0x02005820ATOM_DEVICE_DFP4_SUPPORT 0x04005821ATOM_DEVICE_DFP5_SUPPORT 0x08005822ATOM_DEVICE_LCD1_SUPPORT 0x00025823ulOtherDisplayMisc: Other display related flags, not defined yet.5824ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.5825=1: TMDS/HDMI Coherent Mode use signel PLL mode.5826bit[3]=0: Enable HW AUX mode detection logic5827=1: Disable HW AUX mode dettion logic5828ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.58295830usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).5831Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;58325833When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:58341. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;5835VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,5836Changing BL using VBIOS function is functional in both driver and non-driver present environment;5837and enabling VariBri under the driver environment from PP table is optional.583858392. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating5840that BL control from GPU is expected.5841VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==15842Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but5843it's per platform5844and enabling VariBri under the driver environment from PP table is optional.58455846ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt.5847Threshold on value to enter HTC_active state.5848ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.5849To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.5850ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.5851ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled5852=1: PCIE Power Gating Enabled5853Bit[1]=0: DDR-DLL shut-down feature disabled.58541: DDR-DLL shut-down feature enabled.5855Bit[2]=0: DDR-PLL Power down feature disabled.58561: DDR-PLL Power down feature enabled.5857ulCPUCapInfo: TBD5858usNBP0Voltage: VID for voltage on NB P0 State5859usNBP1Voltage: VID for voltage on NB P1 State5860usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.5861usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure5862usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set5863to indicate a range.5864SUPPORTED_LCD_REFRESHRATE_30Hz 0x00045865SUPPORTED_LCD_REFRESHRATE_40Hz 0x00085866SUPPORTED_LCD_REFRESHRATE_50Hz 0x00105867SUPPORTED_LCD_REFRESHRATE_60Hz 0x00205868ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.5869ucUMAChannelNumber: System memory channel numbers.5870ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default5871ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback.5872ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications.5873sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high5874ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.5875ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.5876ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.5877ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.5878ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.5879usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%.5880usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread.5881usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.5882usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.5883usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.5884usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.5885usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.5886usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.5887usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz5888ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode5889[bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped5890[bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color5891[bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used5892[bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )5893**********************************************************************************************************************/58945895// this Table is used for Liano/Ontario APU5896typedef struct _ATOM_FUSION_SYSTEM_INFO_V15897{5898ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo;5899ULONG ulPowerplayTable[128];5900}ATOM_FUSION_SYSTEM_INFO_V1;590159025903typedef struct _ATOM_TDP_CONFIG_BITS5904{5905#if ATOM_BIG_ENDIAN5906ULONG uReserved:2;5907ULONG uTDP_Value:14; // Original TDP value in tens of milli watts5908ULONG uCTDP_Value:14; // Override value in tens of milli watts5909ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))5910#else5911ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))5912ULONG uCTDP_Value:14; // Override value in tens of milli watts5913ULONG uTDP_Value:14; // Original TDP value in tens of milli watts5914ULONG uReserved:2;5915#endif5916}ATOM_TDP_CONFIG_BITS;59175918typedef union _ATOM_TDP_CONFIG5919{5920ATOM_TDP_CONFIG_BITS TDP_config;5921ULONG TDP_config_all;5922}ATOM_TDP_CONFIG;59235924/**********************************************************************************************************************5925ATOM_FUSION_SYSTEM_INFO_V1 Description5926sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition.5927ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0]5928**********************************************************************************************************************/59295930// this IntegrateSystemInfoTable is used for Trinity APU5931typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_75932{5933ATOM_COMMON_TABLE_HEADER sHeader;5934ULONG ulBootUpEngineClock;5935ULONG ulDentistVCOFreq;5936ULONG ulBootUpUMAClock;5937ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];5938ULONG ulBootUpReqDisplayVector;5939ULONG ulOtherDisplayMisc;5940ULONG ulGPUCapInfo;5941ULONG ulSB_MMIO_Base_Addr;5942USHORT usRequestedPWMFreqInHz;5943UCHAR ucHtcTmpLmt;5944UCHAR ucHtcHystLmt;5945ULONG ulMinEngineClock;5946ULONG ulSystemConfig;5947ULONG ulCPUCapInfo;5948USHORT usNBP0Voltage;5949USHORT usNBP1Voltage;5950USHORT usBootUpNBVoltage;5951USHORT usExtDispConnInfoOffset;5952USHORT usPanelRefreshRateRange;5953UCHAR ucMemoryType;5954UCHAR ucUMAChannelNumber;5955UCHAR strVBIOSMsg[40];5956ATOM_TDP_CONFIG asTdpConfig;5957ULONG ulReserved[19];5958ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5];5959ULONG ulGMCRestoreResetTime;5960ULONG ulMinimumNClk;5961ULONG ulIdleNClk;5962ULONG ulDDR_DLL_PowerUpTime;5963ULONG ulDDR_PLL_PowerUpTime;5964USHORT usPCIEClkSSPercentage;5965USHORT usPCIEClkSSType;5966USHORT usLvdsSSPercentage;5967USHORT usLvdsSSpreadRateIn10Hz;5968USHORT usHDMISSPercentage;5969USHORT usHDMISSpreadRateIn10Hz;5970USHORT usDVISSPercentage;5971USHORT usDVISSpreadRateIn10Hz;5972ULONG SclkDpmBoostMargin;5973ULONG SclkDpmThrottleMargin;5974USHORT SclkDpmTdpLimitPG;5975USHORT SclkDpmTdpLimitBoost;5976ULONG ulBoostEngineCLock;5977UCHAR ulBoostVid_2bit;5978UCHAR EnableBoost;5979USHORT GnbTdpLimit;5980USHORT usMaxLVDSPclkFreqInSingleLink;5981UCHAR ucLvdsMisc;5982UCHAR ucTravisLVDSVolAdjust;5983UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;5984UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;5985UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;5986UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;5987UCHAR ucLVDSOffToOnDelay_in4Ms;5988UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;5989UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;5990UCHAR ucMinAllowedBL_Level;5991ULONG ulLCDBitDepthControlVal;5992ULONG ulNbpStateMemclkFreq[4];5993USHORT usNBP2Voltage;5994USHORT usNBP3Voltage;5995ULONG ulNbpStateNClkFreq[4];5996UCHAR ucNBDPMEnable;5997UCHAR ucReserved[3];5998UCHAR ucDPMState0VclkFid;5999UCHAR ucDPMState0DclkFid;6000UCHAR ucDPMState1VclkFid;6001UCHAR ucDPMState1DclkFid;6002UCHAR ucDPMState2VclkFid;6003UCHAR ucDPMState2DclkFid;6004UCHAR ucDPMState3VclkFid;6005UCHAR ucDPMState3DclkFid;6006ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;6007}ATOM_INTEGRATED_SYSTEM_INFO_V1_7;60086009// ulOtherDisplayMisc6010#define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x016011#define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT 0x026012#define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT 0x046013#define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT 0x0860146015// ulGPUCapInfo6016#define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x016017#define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE 0x026018#define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT 0x086019#define SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS 0x106020//ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML6021#define SYS_INFO_GPUCAPS__GNB_FAST_RESUME_CAPABLE 0x0001000060226023//ulGPUCapInfo[17]=1 indicate battery boost feature is enable, from ML6024#define SYS_INFO_GPUCAPS__BATTERY_BOOST_ENABLE 0x0002000060256026/**********************************************************************************************************************6027ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description6028ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock6029ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.6030ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.6031sDISPCLK_Voltage: Report Display clock voltage requirement.60326033ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects:6034ATOM_DEVICE_CRT1_SUPPORT 0x00016035ATOM_DEVICE_DFP1_SUPPORT 0x00086036ATOM_DEVICE_DFP6_SUPPORT 0x00406037ATOM_DEVICE_DFP2_SUPPORT 0x00806038ATOM_DEVICE_DFP3_SUPPORT 0x02006039ATOM_DEVICE_DFP4_SUPPORT 0x04006040ATOM_DEVICE_DFP5_SUPPORT 0x08006041ATOM_DEVICE_LCD1_SUPPORT 0x00026042ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS.6043=1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.6044bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS6045=1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS6046bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS6047=1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS6048bit[3]=0: VBIOS fast boot is disable6049=1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open)6050ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.6051=1: TMDS/HDMI Coherent Mode use signel PLL mode.6052bit[1]=0: DP mode use cascade PLL mode ( New for Trinity )6053=1: DP mode use single PLL mode6054bit[3]=0: Enable AUX HW mode detection logic6055=1: Disable AUX HW mode detection logic60566057ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.60586059usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).6060Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;60616062When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:60631. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;6064VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,6065Changing BL using VBIOS function is functional in both driver and non-driver present environment;6066and enabling VariBri under the driver environment from PP table is optional.606760682. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating6069that BL control from GPU is expected.6070VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==16071Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but6072it's per platform6073and enabling VariBri under the driver environment from PP table is optional.60746075ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt.6076Threshold on value to enter HTC_active state.6077ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.6078To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.6079ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.6080ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled6081=1: PCIE Power Gating Enabled6082Bit[1]=0: DDR-DLL shut-down feature disabled.60831: DDR-DLL shut-down feature enabled.6084Bit[2]=0: DDR-PLL Power down feature disabled.60851: DDR-PLL Power down feature enabled.6086ulCPUCapInfo: TBD6087usNBP0Voltage: VID for voltage on NB P0 State6088usNBP1Voltage: VID for voltage on NB P1 State6089usNBP2Voltage: VID for voltage on NB P2 State6090usNBP3Voltage: VID for voltage on NB P3 State6091usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.6092usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure6093usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set6094to indicate a range.6095SUPPORTED_LCD_REFRESHRATE_30Hz 0x00046096SUPPORTED_LCD_REFRESHRATE_40Hz 0x00086097SUPPORTED_LCD_REFRESHRATE_50Hz 0x00106098SUPPORTED_LCD_REFRESHRATE_60Hz 0x00206099ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.6100ucUMAChannelNumber: System memory channel numbers.6101ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default6102ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback.6103ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications.6104sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high6105ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.6106ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.6107ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.6108ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.6109ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.6110usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.6111usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread.6112usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.6113usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.6114usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.6115usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.6116usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.6117usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.6118usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz6119ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode6120[bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped6121[bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color6122[bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used6123[bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )6124[bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_46125ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust6126value to program Travis register LVDS_CTRL_46127ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ).6128=0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.6129This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.6130ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ).6131=0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.6132This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.61336134ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off.6135=0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON6136This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.61376138ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off.6139=0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON6140This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.61416142ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active.6143=0 means to use VBIOS default delay which is 125 ( 500ms ).6144This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.61456146ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms:6147LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active.6148=0 means to use VBIOS default delay which is 0 ( 0ms ).6149This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.61506151ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms:6152LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off.6153=0 means to use VBIOS default delay which is 0 ( 0ms ).6154This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.61556156ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0.61576158ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate.61596160**********************************************************************************************************************/61616162// this IntegrateSystemInfoTable is used for Kaveri & Kabini APU6163typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_86164{6165ATOM_COMMON_TABLE_HEADER sHeader;6166ULONG ulBootUpEngineClock;6167ULONG ulDentistVCOFreq;6168ULONG ulBootUpUMAClock;6169ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];6170ULONG ulBootUpReqDisplayVector;6171ULONG ulVBIOSMisc;6172ULONG ulGPUCapInfo;6173ULONG ulDISP_CLK2Freq;6174USHORT usRequestedPWMFreqInHz;6175UCHAR ucHtcTmpLmt;6176UCHAR ucHtcHystLmt;6177ULONG ulReserved2;6178ULONG ulSystemConfig;6179ULONG ulCPUCapInfo;6180ULONG ulReserved3;6181USHORT usGPUReservedSysMemSize;6182USHORT usExtDispConnInfoOffset;6183USHORT usPanelRefreshRateRange;6184UCHAR ucMemoryType;6185UCHAR ucUMAChannelNumber;6186UCHAR strVBIOSMsg[40];6187ATOM_TDP_CONFIG asTdpConfig;6188ULONG ulReserved[19];6189ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5];6190ULONG ulGMCRestoreResetTime;6191ULONG ulReserved4;6192ULONG ulIdleNClk;6193ULONG ulDDR_DLL_PowerUpTime;6194ULONG ulDDR_PLL_PowerUpTime;6195USHORT usPCIEClkSSPercentage;6196USHORT usPCIEClkSSType;6197USHORT usLvdsSSPercentage;6198USHORT usLvdsSSpreadRateIn10Hz;6199USHORT usHDMISSPercentage;6200USHORT usHDMISSpreadRateIn10Hz;6201USHORT usDVISSPercentage;6202USHORT usDVISSpreadRateIn10Hz;6203ULONG ulGPUReservedSysMemBaseAddrLo;6204ULONG ulGPUReservedSysMemBaseAddrHi;6205ATOM_CLK_VOLT_CAPABILITY s5thDISPCLK_Voltage;6206ULONG ulReserved5;6207USHORT usMaxLVDSPclkFreqInSingleLink;6208UCHAR ucLvdsMisc;6209UCHAR ucTravisLVDSVolAdjust;6210UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;6211UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;6212UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;6213UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;6214UCHAR ucLVDSOffToOnDelay_in4Ms;6215UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;6216UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;6217UCHAR ucMinAllowedBL_Level;6218ULONG ulLCDBitDepthControlVal;6219ULONG ulNbpStateMemclkFreq[4];6220ULONG ulPSPVersion;6221ULONG ulNbpStateNClkFreq[4];6222USHORT usNBPStateVoltage[4];6223USHORT usBootUpNBVoltage;6224USHORT usReserved2;6225ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;6226}ATOM_INTEGRATED_SYSTEM_INFO_V1_8;62276228/**********************************************************************************************************************6229ATOM_INTEGRATED_SYSTEM_INFO_V1_8 Description6230ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock6231ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.6232ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.6233sDISPCLK_Voltage: Report Display clock frequency requirement on GNB voltage(up to 4 voltage levels).62346235ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects:6236ATOM_DEVICE_CRT1_SUPPORT 0x00016237ATOM_DEVICE_DFP1_SUPPORT 0x00086238ATOM_DEVICE_DFP6_SUPPORT 0x00406239ATOM_DEVICE_DFP2_SUPPORT 0x00806240ATOM_DEVICE_DFP3_SUPPORT 0x02006241ATOM_DEVICE_DFP4_SUPPORT 0x04006242ATOM_DEVICE_DFP5_SUPPORT 0x08006243ATOM_DEVICE_LCD1_SUPPORT 0x000262446245ulVBIOSMisc: Miscellenous flags for VBIOS requirement and interface6246bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS.6247=1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.6248bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS6249=1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS6250bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS6251=1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS6252bit[3]=0: VBIOS fast boot is disable6253=1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open)62546255ulGPUCapInfo: bit[0~2]= Reserved6256bit[3]=0: Enable AUX HW mode detection logic6257=1: Disable AUX HW mode detection logic6258bit[4]=0: Disable DFS bypass feature6259=1: Enable DFS bypass feature62606261usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).6262Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;62636264When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:62651. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;6266VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,6267Changing BL using VBIOS function is functional in both driver and non-driver present environment;6268and enabling VariBri under the driver environment from PP table is optional.626962702. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating6271that BL control from GPU is expected.6272VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==16273Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but6274it's per platform6275and enabling VariBri under the driver environment from PP table is optional.62766277ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state.6278ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.6279To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.62806281ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled6282=1: PCIE Power Gating Enabled6283Bit[1]=0: DDR-DLL shut-down feature disabled.62841: DDR-DLL shut-down feature enabled.6285Bit[2]=0: DDR-PLL Power down feature disabled.62861: DDR-PLL Power down feature enabled.6287Bit[3]=0: GNB DPM is disabled6288=1: GNB DPM is enabled6289ulCPUCapInfo: TBD62906291usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure6292usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set6293to indicate a range.6294SUPPORTED_LCD_REFRESHRATE_30Hz 0x00046295SUPPORTED_LCD_REFRESHRATE_40Hz 0x00086296SUPPORTED_LCD_REFRESHRATE_50Hz 0x00106297SUPPORTED_LCD_REFRESHRATE_60Hz 0x002062986299ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved.6300ucUMAChannelNumber: System memory channel numbers.63016302strVBIOSMsg[40]: VBIOS boot up customized message string63036304sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high63056306ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.6307ulIdleNClk: NCLK speed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz.6308ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.6309ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.63106311usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.6312usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread.6313usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.6314usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.6315usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.6316usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.6317usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.6318usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.63196320usGPUReservedSysMemSize: Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV only, not on KB.6321ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory.6322ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory.63236324usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz6325ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode6326[bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped6327[bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color6328[bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used6329[bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )6330[bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_46331ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust6332value to program Travis register LVDS_CTRL_46333ucLVDSPwrOnSeqDIGONtoDE_in4Ms:6334LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ).6335=0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.6336This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.6337ucLVDSPwrOnDEtoVARY_BL_in4Ms:6338LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ).6339=0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.6340This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.6341ucLVDSPwrOffVARY_BLtoDE_in4Ms:6342LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off.6343=0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON6344This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.6345ucLVDSPwrOffDEtoDIGON_in4Ms:6346LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off.6347=0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON6348This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.6349ucLVDSOffToOnDelay_in4Ms:6350LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active.6351=0 means to use VBIOS default delay which is 125 ( 500ms ).6352This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.6353ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms:6354LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active.6355=0 means to use VBIOS default delay which is 0 ( 0ms ).6356This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.63576358ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms:6359LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off.6360=0 means to use VBIOS default delay which is 0 ( 0ms ).6361This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.6362ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0.63636364ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL63656366ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3).6367ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State6368usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage6369usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded6370sExtDispConnInfo: Display connector information table provided to VBIOS63716372**********************************************************************************************************************/63736374typedef struct _ATOM_I2C_REG_INFO6375{6376UCHAR ucI2cRegIndex;6377UCHAR ucI2cRegVal;6378}ATOM_I2C_REG_INFO;63796380// this IntegrateSystemInfoTable is used for Carrizo6381typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_96382{6383ATOM_COMMON_TABLE_HEADER sHeader;6384ULONG ulBootUpEngineClock;6385ULONG ulDentistVCOFreq;6386ULONG ulBootUpUMAClock;6387ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; // no longer used, keep it as is to avoid driver compiling error6388ULONG ulBootUpReqDisplayVector;6389ULONG ulVBIOSMisc;6390ULONG ulGPUCapInfo;6391ULONG ulDISP_CLK2Freq;6392USHORT usRequestedPWMFreqInHz;6393UCHAR ucHtcTmpLmt;6394UCHAR ucHtcHystLmt;6395ULONG ulReserved2;6396ULONG ulSystemConfig;6397ULONG ulCPUCapInfo;6398ULONG ulReserved3;6399USHORT usGPUReservedSysMemSize;6400USHORT usExtDispConnInfoOffset;6401USHORT usPanelRefreshRateRange;6402UCHAR ucMemoryType;6403UCHAR ucUMAChannelNumber;6404UCHAR strVBIOSMsg[40];6405ATOM_TDP_CONFIG asTdpConfig;6406UCHAR ucExtHDMIReDrvSlvAddr;6407UCHAR ucExtHDMIReDrvRegNum;6408ATOM_I2C_REG_INFO asExtHDMIRegSetting[9];6409ULONG ulReserved[2];6410ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8];6411ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; // no longer used, keep it as is to avoid driver compiling error6412ULONG ulGMCRestoreResetTime;6413ULONG ulReserved4;6414ULONG ulIdleNClk;6415ULONG ulDDR_DLL_PowerUpTime;6416ULONG ulDDR_PLL_PowerUpTime;6417USHORT usPCIEClkSSPercentage;6418USHORT usPCIEClkSSType;6419USHORT usLvdsSSPercentage;6420USHORT usLvdsSSpreadRateIn10Hz;6421USHORT usHDMISSPercentage;6422USHORT usHDMISSpreadRateIn10Hz;6423USHORT usDVISSPercentage;6424USHORT usDVISSpreadRateIn10Hz;6425ULONG ulGPUReservedSysMemBaseAddrLo;6426ULONG ulGPUReservedSysMemBaseAddrHi;6427ULONG ulReserved5[3];6428USHORT usMaxLVDSPclkFreqInSingleLink;6429UCHAR ucLvdsMisc;6430UCHAR ucTravisLVDSVolAdjust;6431UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;6432UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;6433UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;6434UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;6435UCHAR ucLVDSOffToOnDelay_in4Ms;6436UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;6437UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;6438UCHAR ucMinAllowedBL_Level;6439ULONG ulLCDBitDepthControlVal;6440ULONG ulNbpStateMemclkFreq[4]; // only 2 level is changed.6441ULONG ulPSPVersion;6442ULONG ulNbpStateNClkFreq[4];6443USHORT usNBPStateVoltage[4];6444USHORT usBootUpNBVoltage;6445UCHAR ucEDPv1_4VSMode;6446UCHAR ucReserved2;6447ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;6448}ATOM_INTEGRATED_SYSTEM_INFO_V1_9;644964506451// definition for ucEDPv1_4VSMode6452#define EDP_VS_LEGACY_MODE 06453#define EDP_VS_LOW_VDIFF_MODE 16454#define EDP_VS_HIGH_VDIFF_MODE 26455#define EDP_VS_STRETCH_MODE 36456#define EDP_VS_SINGLE_VDIFF_MODE 46457#define EDP_VS_VARIABLE_PREM_MODE 5645864596460// ulGPUCapInfo6461#define SYS_INFO_V1_9_GPUCAPSINFO_DISABLE_AUX_MODE_DETECT 0x086462#define SYS_INFO_V1_9_GPUCAPSINFO_ENABLE_DFS_BYPASS 0x106463//ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML6464#define SYS_INFO_V1_9_GPUCAPSINFO_GNB_FAST_RESUME_CAPABLE 0x000100006465//ulGPUCapInfo[18]=1 indicate the IOMMU is not available6466#define SYS_INFO_V1_9_GPUCAPINFO_IOMMU_DISABLE 0x000400006467//ulGPUCapInfo[19]=1 indicate the MARC Aperture is opened.6468#define SYS_INFO_V1_9_GPUCAPINFO_MARC_APERTURE_ENABLE 0x00080000646964706471typedef struct _DPHY_TIMING_PARA6472{6473UCHAR ucProfileID; // SENSOR_PROFILES6474ULONG ucPara;6475} DPHY_TIMING_PARA;64766477typedef struct _DPHY_ELEC_PARA6478{6479USHORT usPara[3];6480} DPHY_ELEC_PARA;64816482typedef struct _CAMERA_MODULE_INFO6483{6484UCHAR ucID; // 0: Rear, 1: Front right of user, 2: Front left of user6485UCHAR strModuleName[8];6486DPHY_TIMING_PARA asTimingPara[6]; // Exact number is under estimation and confirmation from sensor vendor6487} CAMERA_MODULE_INFO;64886489typedef struct _FLASHLIGHT_INFO6490{6491UCHAR ucID; // 0: Rear, 1: Front6492UCHAR strName[8];6493} FLASHLIGHT_INFO;64946495typedef struct _CAMERA_DATA6496{6497ULONG ulVersionCode;6498CAMERA_MODULE_INFO asCameraInfo[3]; // Assuming 3 camera sensors max6499FLASHLIGHT_INFO asFlashInfo; // Assuming 1 flashlight max6500DPHY_ELEC_PARA asDphyElecPara;6501ULONG ulCrcVal; // CRC6502}CAMERA_DATA;65036504typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_106505{6506ATOM_COMMON_TABLE_HEADER sHeader;6507ULONG ulBootUpEngineClock;6508ULONG ulDentistVCOFreq;6509ULONG ulBootUpUMAClock;6510ULONG ulReserved0[8];6511ULONG ulBootUpReqDisplayVector;6512ULONG ulVBIOSMisc;6513ULONG ulGPUCapInfo;6514ULONG ulReserved1;6515USHORT usRequestedPWMFreqInHz;6516UCHAR ucHtcTmpLmt;6517UCHAR ucHtcHystLmt;6518ULONG ulReserved2;6519ULONG ulSystemConfig;6520ULONG ulCPUCapInfo;6521ULONG ulReserved3;6522USHORT usGPUReservedSysMemSize;6523USHORT usExtDispConnInfoOffset;6524USHORT usPanelRefreshRateRange;6525UCHAR ucMemoryType;6526UCHAR ucUMAChannelNumber;6527ULONG ulMsgReserved[10];6528ATOM_TDP_CONFIG asTdpConfig;6529ULONG ulReserved[7];6530ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8];6531ULONG ulReserved6[10];6532ULONG ulGMCRestoreResetTime;6533ULONG ulReserved4;6534ULONG ulIdleNClk;6535ULONG ulDDR_DLL_PowerUpTime;6536ULONG ulDDR_PLL_PowerUpTime;6537USHORT usPCIEClkSSPercentage;6538USHORT usPCIEClkSSType;6539USHORT usLvdsSSPercentage;6540USHORT usLvdsSSpreadRateIn10Hz;6541USHORT usHDMISSPercentage;6542USHORT usHDMISSpreadRateIn10Hz;6543USHORT usDVISSPercentage;6544USHORT usDVISSpreadRateIn10Hz;6545ULONG ulGPUReservedSysMemBaseAddrLo;6546ULONG ulGPUReservedSysMemBaseAddrHi;6547ULONG ulReserved5[3];6548USHORT usMaxLVDSPclkFreqInSingleLink;6549UCHAR ucLvdsMisc;6550UCHAR ucTravisLVDSVolAdjust;6551UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;6552UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;6553UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;6554UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;6555UCHAR ucLVDSOffToOnDelay_in4Ms;6556UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;6557UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;6558UCHAR ucMinAllowedBL_Level;6559ULONG ulLCDBitDepthControlVal;6560ULONG ulNbpStateMemclkFreq[2];6561ULONG ulReserved7[2];6562ULONG ulPSPVersion;6563ULONG ulNbpStateNClkFreq[4];6564USHORT usNBPStateVoltage[4];6565USHORT usBootUpNBVoltage;6566UCHAR ucEDPv1_4VSMode;6567UCHAR ucReserved2;6568ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;6569CAMERA_DATA asCameraInfo;6570ULONG ulReserved8[29];6571}ATOM_INTEGRATED_SYSTEM_INFO_V1_10;657265736574// this Table is used for Kaveri/Kabini APU6575typedef struct _ATOM_FUSION_SYSTEM_INFO_V26576{6577ATOM_INTEGRATED_SYSTEM_INFO_V1_8 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition6578ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure6579}ATOM_FUSION_SYSTEM_INFO_V2;658065816582typedef struct _ATOM_FUSION_SYSTEM_INFO_V36583{6584ATOM_INTEGRATED_SYSTEM_INFO_V1_10 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition6585ULONG ulPowerplayTable[192]; // Reserve 768 bytes space for PowerPlayInfoTable6586}ATOM_FUSION_SYSTEM_INFO_V3;65876588#define FUSION_V3_OFFSET_FROM_TOP_OF_FB 0x80065896590/**************************************************************************/6591// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design6592//Memory SS Info Table6593//Define Memory Clock SS chip ID6594#define ICS91719 16595#define ICS91720 265966597//Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol6598typedef struct _ATOM_I2C_DATA_RECORD6599{6600UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop"6601UCHAR ucI2CData[]; //I2C data in bytes, should be less than 16 bytes usually6602}ATOM_I2C_DATA_RECORD;660366046605//Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information6606typedef struct _ATOM_I2C_DEVICE_SETUP_INFO6607{6608ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap.6609UCHAR ucSSChipID; //SS chip being used6610UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip6611UCHAR ucNumOfI2CDataRecords; //number of data block6612ATOM_I2C_DATA_RECORD asI2CData[];6613}ATOM_I2C_DEVICE_SETUP_INFO;66146615//==========================================================================================6616typedef struct _ATOM_ASIC_MVDD_INFO6617{6618ATOM_COMMON_TABLE_HEADER sHeader;6619ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[];6620}ATOM_ASIC_MVDD_INFO;66216622//==========================================================================================6623#define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO66246625//==========================================================================================6626/**************************************************************************/66276628typedef struct _ATOM_ASIC_SS_ASSIGNMENT6629{6630ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz6631USHORT usSpreadSpectrumPercentage; //in unit of 0.01%6632USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq6633UCHAR ucClockIndication; //Indicate which clock source needs SS6634UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread.6635UCHAR ucReserved[2];6636}ATOM_ASIC_SS_ASSIGNMENT;66376638//Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a clock branch/signal type.6639//SS is not required or enabled if a match is not found.6640#define ASIC_INTERNAL_MEMORY_SS 16641#define ASIC_INTERNAL_ENGINE_SS 26642#define ASIC_INTERNAL_UVD_SS 36643#define ASIC_INTERNAL_SS_ON_TMDS 46644#define ASIC_INTERNAL_SS_ON_HDMI 56645#define ASIC_INTERNAL_SS_ON_LVDS 66646#define ASIC_INTERNAL_SS_ON_DP 76647#define ASIC_INTERNAL_SS_ON_DCPLL 86648#define ASIC_EXTERNAL_SS_ON_DP_CLOCK 96649#define ASIC_INTERNAL_VCE_SS 106650#define ASIC_INTERNAL_GPUPLL_SS 11665166526653typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V26654{6655ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz6656//For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )6657USHORT usSpreadSpectrumPercentage; //in unit of 0.01%6658USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq6659UCHAR ucClockIndication; //Indicate which clock source needs SS6660UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS6661UCHAR ucReserved[2];6662}ATOM_ASIC_SS_ASSIGNMENT_V2;66636664//ucSpreadSpectrumMode6665//#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x000000006666//#define ATOM_SS_DOWN_SPREAD_MODE 0x000000006667//#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x000000016668//#define ATOM_SS_CENTRE_SPREAD_MODE 0x000000016669//#define ATOM_INTERNAL_SS_MASK 0x000000006670//#define ATOM_EXTERNAL_SS_MASK 0x0000000266716672typedef struct _ATOM_ASIC_INTERNAL_SS_INFO6673{6674ATOM_COMMON_TABLE_HEADER sHeader;6675ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4];6676}ATOM_ASIC_INTERNAL_SS_INFO;66776678typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V26679{6680ATOM_COMMON_TABLE_HEADER sHeader;6681ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[]; //this is point only.6682}ATOM_ASIC_INTERNAL_SS_INFO_V2;66836684typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V36685{6686ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz6687//For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )6688USHORT usSpreadSpectrumPercentage; //in unit of 0.01% or 0.001%, decided by ucSpreadSpectrumMode bit46689USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq6690UCHAR ucClockIndication; //Indicate which clock source needs SS6691UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS6692UCHAR ucReserved[2];6693}ATOM_ASIC_SS_ASSIGNMENT_V3;66946695//ATOM_ASIC_SS_ASSIGNMENT_V3.ucSpreadSpectrumMode6696#define SS_MODE_V3_CENTRE_SPREAD_MASK 0x016697#define SS_MODE_V3_EXTERNAL_SS_MASK 0x026698#define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK 0x1066996700typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V36701{6702ATOM_COMMON_TABLE_HEADER sHeader;6703ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[]; //this is pointer only.6704}ATOM_ASIC_INTERNAL_SS_INFO_V3;670567066707//==============================Scratch Pad Definition Portion===============================6708#define ATOM_DEVICE_CONNECT_INFO_DEF 06709#define ATOM_ROM_LOCATION_DEF 16710#define ATOM_TV_STANDARD_DEF 26711#define ATOM_ACTIVE_INFO_DEF 36712#define ATOM_LCD_INFO_DEF 46713#define ATOM_DOS_REQ_INFO_DEF 56714#define ATOM_ACC_CHANGE_INFO_DEF 66715#define ATOM_DOS_MODE_INFO_DEF 76716#define ATOM_I2C_CHANNEL_STATUS_DEF 86717#define ATOM_I2C_CHANNEL_STATUS1_DEF 96718#define ATOM_INTERNAL_TIMER_DEF 1067196720// BIOS_0_SCRATCH Definition6721#define ATOM_S0_CRT1_MONO 0x00000001L6722#define ATOM_S0_CRT1_COLOR 0x00000002L6723#define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR)67246725#define ATOM_S0_TV1_COMPOSITE_A 0x00000004L6726#define ATOM_S0_TV1_SVIDEO_A 0x00000008L6727#define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A)67286729#define ATOM_S0_CV_A 0x00000010L6730#define ATOM_S0_CV_DIN_A 0x00000020L6731#define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A)673267336734#define ATOM_S0_CRT2_MONO 0x00000100L6735#define ATOM_S0_CRT2_COLOR 0x00000200L6736#define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR)67376738#define ATOM_S0_TV1_COMPOSITE 0x00000400L6739#define ATOM_S0_TV1_SVIDEO 0x00000800L6740#define ATOM_S0_TV1_SCART 0x00004000L6741#define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART)67426743#define ATOM_S0_CV 0x00001000L6744#define ATOM_S0_CV_DIN 0x00002000L6745#define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN)67466747#define ATOM_S0_DFP1 0x00010000L6748#define ATOM_S0_DFP2 0x00020000L6749#define ATOM_S0_LCD1 0x00040000L6750#define ATOM_S0_LCD2 0x00080000L6751#define ATOM_S0_DFP6 0x00100000L6752#define ATOM_S0_DFP3 0x00200000L6753#define ATOM_S0_DFP4 0x00400000L6754#define ATOM_S0_DFP5 0x00800000L675567566757#define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP667586759#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with6760// the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx67616762#define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L6763#define ATOM_S0_THERMAL_STATE_SHIFT 2667646765#define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L6766#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 2967676768#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 16769#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 26770#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 36771#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 467726773//Byte aligned defintion for BIOS usage6774#define ATOM_S0_CRT1_MONOb0 0x016775#define ATOM_S0_CRT1_COLORb0 0x026776#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0)67776778#define ATOM_S0_TV1_COMPOSITEb0 0x046779#define ATOM_S0_TV1_SVIDEOb0 0x086780#define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0)67816782#define ATOM_S0_CVb0 0x106783#define ATOM_S0_CV_DINb0 0x206784#define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0)67856786#define ATOM_S0_CRT2_MONOb1 0x016787#define ATOM_S0_CRT2_COLORb1 0x026788#define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1)67896790#define ATOM_S0_TV1_COMPOSITEb1 0x046791#define ATOM_S0_TV1_SVIDEOb1 0x086792#define ATOM_S0_TV1_SCARTb1 0x406793#define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1)67946795#define ATOM_S0_CVb1 0x106796#define ATOM_S0_CV_DINb1 0x206797#define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1)67986799#define ATOM_S0_DFP1b2 0x016800#define ATOM_S0_DFP2b2 0x026801#define ATOM_S0_LCD1b2 0x046802#define ATOM_S0_LCD2b2 0x086803#define ATOM_S0_DFP6b2 0x106804#define ATOM_S0_DFP3b2 0x206805#define ATOM_S0_DFP4b2 0x406806#define ATOM_S0_DFP5b2 0x80680768086809#define ATOM_S0_THERMAL_STATE_MASKb3 0x1C6810#define ATOM_S0_THERMAL_STATE_SHIFTb3 268116812#define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE06813#define ATOM_S0_LCD1_SHIFT 1868146815// BIOS_1_SCRATCH Definition6816#define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL6817#define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L68186819// BIOS_2_SCRATCH Definition6820#define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL6821#define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L6822#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 868236824#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L6825#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 266826#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L68276828#define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L6829#define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L68306831#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x06832#define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x16833#define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x26834#define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x36835#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 306836#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L683768386839//Byte aligned defintion for BIOS usage6840#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F6841#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF6842#define ATOM_S2_DEVICE_DPMS_STATEb2 0x0168436844#define ATOM_S2_TMDS_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode for TMDS/HDMI mode6845#define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x206846#define ATOM_S2_ROTATION_STATE_MASKb3 0xC0684768486849// BIOS_3_SCRATCH Definition6850#define ATOM_S3_CRT1_ACTIVE 0x00000001L6851#define ATOM_S3_LCD1_ACTIVE 0x00000002L6852#define ATOM_S3_TV1_ACTIVE 0x00000004L6853#define ATOM_S3_DFP1_ACTIVE 0x00000008L6854#define ATOM_S3_CRT2_ACTIVE 0x00000010L6855#define ATOM_S3_LCD2_ACTIVE 0x00000020L6856#define ATOM_S3_DFP6_ACTIVE 0x00000040L6857#define ATOM_S3_DFP2_ACTIVE 0x00000080L6858#define ATOM_S3_CV_ACTIVE 0x00000100L6859#define ATOM_S3_DFP3_ACTIVE 0x00000200L6860#define ATOM_S3_DFP4_ACTIVE 0x00000400L6861#define ATOM_S3_DFP5_ACTIVE 0x00000800L686268636864#define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL68656866#define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L6867#define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L68686869#define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L6870#define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L6871#define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L6872#define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L6873#define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L6874#define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L6875#define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L6876#define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L6877#define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L6878#define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L6879#define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L6880#define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L688168826883#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L6884#define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L6885//Below two definitions are not supported in pplib, but in the old powerplay in DAL6886#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L6887#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L6888688968906891//Byte aligned defintion for BIOS usage6892#define ATOM_S3_CRT1_ACTIVEb0 0x016893#define ATOM_S3_LCD1_ACTIVEb0 0x026894#define ATOM_S3_TV1_ACTIVEb0 0x046895#define ATOM_S3_DFP1_ACTIVEb0 0x086896#define ATOM_S3_CRT2_ACTIVEb0 0x106897#define ATOM_S3_LCD2_ACTIVEb0 0x206898#define ATOM_S3_DFP6_ACTIVEb0 0x406899#define ATOM_S3_DFP2_ACTIVEb0 0x806900#define ATOM_S3_CV_ACTIVEb1 0x016901#define ATOM_S3_DFP3_ACTIVEb1 0x026902#define ATOM_S3_DFP4_ACTIVEb1 0x046903#define ATOM_S3_DFP5_ACTIVEb1 0x08690469056906#define ATOM_S3_ACTIVE_CRTC1w0 0xFFF69076908#define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x016909#define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x026910#define ATOM_S3_TV1_CRTC_ACTIVEb2 0x046911#define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x086912#define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x106913#define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x206914#define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x406915#define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x806916#define ATOM_S3_CV_CRTC_ACTIVEb3 0x016917#define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x026918#define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x046919#define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08692069216922#define ATOM_S3_ACTIVE_CRTC2w1 0xFFF692369246925// BIOS_4_SCRATCH Definition6926#define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL6927#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L6928#define ATOM_S4_LCD1_REFRESH_SHIFT 869296930//Byte aligned defintion for BIOS usage6931#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF6932#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb06933#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb069346935// BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!!6936#define ATOM_S5_DOS_REQ_CRT1b0 0x016937#define ATOM_S5_DOS_REQ_LCD1b0 0x026938#define ATOM_S5_DOS_REQ_TV1b0 0x046939#define ATOM_S5_DOS_REQ_DFP1b0 0x086940#define ATOM_S5_DOS_REQ_CRT2b0 0x106941#define ATOM_S5_DOS_REQ_LCD2b0 0x206942#define ATOM_S5_DOS_REQ_DFP6b0 0x406943#define ATOM_S5_DOS_REQ_DFP2b0 0x806944#define ATOM_S5_DOS_REQ_CVb1 0x016945#define ATOM_S5_DOS_REQ_DFP3b1 0x026946#define ATOM_S5_DOS_REQ_DFP4b1 0x046947#define ATOM_S5_DOS_REQ_DFP5b1 0x08694869496950#define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF69516952#define ATOM_S5_DOS_REQ_CRT1 0x00016953#define ATOM_S5_DOS_REQ_LCD1 0x00026954#define ATOM_S5_DOS_REQ_TV1 0x00046955#define ATOM_S5_DOS_REQ_DFP1 0x00086956#define ATOM_S5_DOS_REQ_CRT2 0x00106957#define ATOM_S5_DOS_REQ_LCD2 0x00206958#define ATOM_S5_DOS_REQ_DFP6 0x00406959#define ATOM_S5_DOS_REQ_DFP2 0x00806960#define ATOM_S5_DOS_REQ_CV 0x01006961#define ATOM_S5_DOS_REQ_DFP3 0x02006962#define ATOM_S5_DOS_REQ_DFP4 0x04006963#define ATOM_S5_DOS_REQ_DFP5 0x080069646965#define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b06966#define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b06967#define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b06968#define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb16969#define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\6970(ATOM_S5_DOS_FORCE_CVb3<<8))6971// BIOS_6_SCRATCH Definition6972#define ATOM_S6_DEVICE_CHANGE 0x00000001L6973#define ATOM_S6_SCALER_CHANGE 0x00000002L6974#define ATOM_S6_LID_CHANGE 0x00000004L6975#define ATOM_S6_DOCKING_CHANGE 0x00000008L6976#define ATOM_S6_ACC_MODE 0x00000010L6977#define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L6978#define ATOM_S6_LID_STATE 0x00000040L6979#define ATOM_S6_DOCK_STATE 0x00000080L6980#define ATOM_S6_CRITICAL_STATE 0x00000100L6981#define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L6982#define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L6983#define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L6984#define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD6985#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD69866987#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion6988#define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion69896990#define ATOM_S6_ACC_REQ_CRT1 0x00010000L6991#define ATOM_S6_ACC_REQ_LCD1 0x00020000L6992#define ATOM_S6_ACC_REQ_TV1 0x00040000L6993#define ATOM_S6_ACC_REQ_DFP1 0x00080000L6994#define ATOM_S6_ACC_REQ_CRT2 0x00100000L6995#define ATOM_S6_ACC_REQ_LCD2 0x00200000L6996#define ATOM_S6_ACC_REQ_DFP6 0x00400000L6997#define ATOM_S6_ACC_REQ_DFP2 0x00800000L6998#define ATOM_S6_ACC_REQ_CV 0x01000000L6999#define ATOM_S6_ACC_REQ_DFP3 0x02000000L7000#define ATOM_S6_ACC_REQ_DFP4 0x04000000L7001#define ATOM_S6_ACC_REQ_DFP5 0x08000000L70027003#define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L7004#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L7005#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L7006#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L7007#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L70087009//Byte aligned defintion for BIOS usage7010#define ATOM_S6_DEVICE_CHANGEb0 0x017011#define ATOM_S6_SCALER_CHANGEb0 0x027012#define ATOM_S6_LID_CHANGEb0 0x047013#define ATOM_S6_DOCKING_CHANGEb0 0x087014#define ATOM_S6_ACC_MODEb0 0x107015#define ATOM_S6_EXT_DESKTOP_MODEb0 0x207016#define ATOM_S6_LID_STATEb0 0x407017#define ATOM_S6_DOCK_STATEb0 0x807018#define ATOM_S6_CRITICAL_STATEb1 0x017019#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x027020#define ATOM_S6_THERMAL_STATE_CHANGEb1 0x047021#define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x087022#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x107023#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x2070247025#define ATOM_S6_ACC_REQ_CRT1b2 0x017026#define ATOM_S6_ACC_REQ_LCD1b2 0x027027#define ATOM_S6_ACC_REQ_TV1b2 0x047028#define ATOM_S6_ACC_REQ_DFP1b2 0x087029#define ATOM_S6_ACC_REQ_CRT2b2 0x107030#define ATOM_S6_ACC_REQ_LCD2b2 0x207031#define ATOM_S6_ACC_REQ_DFP6b2 0x407032#define ATOM_S6_ACC_REQ_DFP2b2 0x807033#define ATOM_S6_ACC_REQ_CVb3 0x017034#define ATOM_S6_ACC_REQ_DFP3b3 0x027035#define ATOM_S6_ACC_REQ_DFP4b3 0x047036#define ATOM_S6_ACC_REQ_DFP5b3 0x0870377038#define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw07039#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x107040#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x207041#define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x407042#define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x8070437044#define ATOM_S6_DEVICE_CHANGE_SHIFT 07045#define ATOM_S6_SCALER_CHANGE_SHIFT 17046#define ATOM_S6_LID_CHANGE_SHIFT 27047#define ATOM_S6_DOCKING_CHANGE_SHIFT 37048#define ATOM_S6_ACC_MODE_SHIFT 47049#define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 57050#define ATOM_S6_LID_STATE_SHIFT 67051#define ATOM_S6_DOCK_STATE_SHIFT 77052#define ATOM_S6_CRITICAL_STATE_SHIFT 87053#define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 97054#define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 107055#define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 117056#define ATOM_S6_REQ_SCALER_SHIFT 127057#define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 137058#define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 147059#define ATOM_S6_I2C_STATE_CHANGE_SHIFT 157060#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 287061#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 297062#define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 307063#define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 3170647065// BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!!7066#define ATOM_S7_DOS_MODE_TYPEb0 0x037067#define ATOM_S7_DOS_MODE_VGAb0 0x007068#define ATOM_S7_DOS_MODE_VESAb0 0x017069#define ATOM_S7_DOS_MODE_EXTb0 0x027070#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C7071#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF07072#define ATOM_S7_DOS_8BIT_DAC_ENb1 0x017073#define ATOM_S7_ASIC_INIT_COMPLETEb1 0x027074#define ATOM_S7_ASIC_INIT_COMPLETE_MASK 0x000002007075#define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF70767077#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 870787079// BIOS_8_SCRATCH Definition7080#define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF7081#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF000070827083#define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 07084#define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 1670857086// BIOS_9_SCRATCH Definition7087#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK7088#define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF7089#endif7090#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK7091#define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF00007092#endif7093#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT7094#define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 07095#endif7096#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT7097#define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 167098#endif709971007101#define ATOM_FLAG_SET 0x207102#define ATOM_FLAG_CLEAR 07103#define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR)7104#define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET)7105#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET)7106#define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET)7107#define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET)71087109#define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET)7110#define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR)71117112#define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET)7113#define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET)7114#define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR)71157116#define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET)7117#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET)7118#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET)71197120#define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET)7121#define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR)71227123#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET)7124#define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR )71257126#define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET )7127#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR )71287129#define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )71307131#define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )71327133#define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET)7134#define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR )7135#define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET )7136#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR )71377138/****************************************************************************/7139//Portion II: Definitinos only used in Driver7140/****************************************************************************/71417142// Macros used by driver71437144#ifdef __cplusplus7145#define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT))71467147#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F)7148#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F)7149#else // not __cplusplus7150#define GetIndexIntoMasterTable(MasterOrData, FieldName) (offsetof(ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES, FieldName) / sizeof(USHORT))71517152#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)7153#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)7154#endif // __cplusplus71557156#define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION7157#define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION71587159/****************************************************************************/7160//Portion III: Definitinos only used in VBIOS7161/****************************************************************************/7162#define ATOM_DAC_SRC 0x807163#define ATOM_SRC_DAC1 07164#define ATOM_SRC_DAC2 0x807165716671677168typedef struct _MEMORY_PLLINIT_PARAMETERS7169{7170ULONG ulTargetMemoryClock; //In 10Khz unit7171UCHAR ucAction; //not define yet7172UCHAR ucFbDiv_Hi; //Fbdiv Hi byte7173UCHAR ucFbDiv; //FB value7174UCHAR ucPostDiv; //Post div7175}MEMORY_PLLINIT_PARAMETERS;71767177#define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS717871797180#define GPIO_PIN_WRITE 0x017181#define GPIO_PIN_READ 0x0071827183typedef struct _GPIO_PIN_CONTROL_PARAMETERS7184{7185UCHAR ucGPIO_ID; //return value, read from GPIO pins7186UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update7187UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask7188UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write7189}GPIO_PIN_CONTROL_PARAMETERS;71907191typedef struct _ENABLE_SCALER_PARAMETERS7192{7193UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER27194UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION7195UCHAR ucTVStandard; //7196UCHAR ucPadding[1];7197}ENABLE_SCALER_PARAMETERS;7198#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS71997200//ucEnable:7201#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 07202#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 17203#define SCALER_ENABLE_2TAP_ALPHA_MODE 27204#define SCALER_ENABLE_MULTITAP_MODE 372057206typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS7207{7208ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position7209UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset7210UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset7211UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON27212UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE7213}ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS;72147215typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION7216{7217ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon;7218ENABLE_CRTC_PARAMETERS sReserved;7219}ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION;72207221typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS7222{7223USHORT usHight; // Image Hight7224USHORT usWidth; // Image Width7225UCHAR ucSurface; // Surface 1 or 27226UCHAR ucPadding[3];7227}ENABLE_GRAPH_SURFACE_PARAMETERS;72287229typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_27230{7231USHORT usHight; // Image Hight7232USHORT usWidth; // Image Width7233UCHAR ucSurface; // Surface 1 or 27234UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE7235UCHAR ucPadding[2];7236}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2;72377238typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_37239{7240USHORT usHight; // Image Hight7241USHORT usWidth; // Image Width7242UCHAR ucSurface; // Surface 1 or 27243UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE7244USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0.7245}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3;72467247typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_47248{7249USHORT usHight; // Image Hight7250USHORT usWidth; // Image Width7251USHORT usGraphPitch;7252UCHAR ucColorDepth;7253UCHAR ucPixelFormat;7254UCHAR ucSurface; // Surface 1 or 27255UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE7256UCHAR ucModeType;7257UCHAR ucReserved;7258}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4;72597260// ucEnable7261#define ATOM_GRAPH_CONTROL_SET_PITCH 0x0f7262#define ATOM_GRAPH_CONTROL_SET_DISP_START 0x1072637264typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION7265{7266ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface;7267ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one7268}ENABLE_GRAPH_SURFACE_PS_ALLOCATION;72697270typedef struct _MEMORY_CLEAN_UP_PARAMETERS7271{7272USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address7273USHORT usMemorySize; //8Kb blocks aligned7274}MEMORY_CLEAN_UP_PARAMETERS;72757276#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS72777278typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS7279{7280USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC7281USHORT usY_Size;7282}GET_DISPLAY_SURFACE_SIZE_PARAMETERS;72837284typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V27285{7286union{7287USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC7288USHORT usSurface;7289};7290USHORT usY_Size;7291USHORT usDispXStart;7292USHORT usDispYStart;7293}GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2;729472957296typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V37297{7298UCHAR ucLutId;7299UCHAR ucAction;7300USHORT usLutStartIndex;7301USHORT usLutLength;7302USHORT usLutOffsetInVram;7303}PALETTE_DATA_CONTROL_PARAMETERS_V3;73047305// ucAction:7306#define PALETTE_DATA_AUTO_FILL 17307#define PALETTE_DATA_READ 27308#define PALETTE_DATA_WRITE 3730973107311typedef struct _INTERRUPT_SERVICE_PARAMETERS_V27312{7313UCHAR ucInterruptId;7314UCHAR ucServiceId;7315UCHAR ucStatus;7316UCHAR ucReserved;7317}INTERRUPT_SERVICE_PARAMETER_V2;73187319// ucInterruptId7320#define HDP1_INTERRUPT_ID 17321#define HDP2_INTERRUPT_ID 27322#define HDP3_INTERRUPT_ID 37323#define HDP4_INTERRUPT_ID 47324#define HDP5_INTERRUPT_ID 57325#define HDP6_INTERRUPT_ID 67326#define SW_INTERRUPT_ID 1173277328// ucAction7329#define INTERRUPT_SERVICE_GEN_SW_INT 17330#define INTERRUPT_SERVICE_GET_STATUS 273317332// ucStatus7333#define INTERRUPT_STATUS__INT_TRIGGER 17334#define INTERRUPT_STATUS__HPD_HIGH 273357336typedef struct _EFUSE_INPUT_PARAMETER7337{7338USHORT usEfuseIndex;7339UCHAR ucBitShift;7340UCHAR ucBitLength;7341}EFUSE_INPUT_PARAMETER;73427343// ReadEfuseValue command table input/output parameter7344typedef union _READ_EFUSE_VALUE_PARAMETER7345{7346EFUSE_INPUT_PARAMETER sEfuse;7347ULONG ulEfuseValue;7348}READ_EFUSE_VALUE_PARAMETER;73497350typedef struct _INDIRECT_IO_ACCESS7351{7352ATOM_COMMON_TABLE_HEADER sHeader;7353UCHAR IOAccessSequence[256];7354} INDIRECT_IO_ACCESS;73557356#define INDIRECT_READ 0x007357#define INDIRECT_WRITE 0x8073587359#define INDIRECT_IO_MM 07360#define INDIRECT_IO_PLL 17361#define INDIRECT_IO_MC 27362#define INDIRECT_IO_PCIE 37363#define INDIRECT_IO_PCIEP 47364#define INDIRECT_IO_NBMISC 57365#define INDIRECT_IO_SMU 573667367#define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ7368#define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE7369#define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ7370#define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE7371#define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ7372#define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE7373#define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ7374#define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE7375#define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ7376#define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE7377#define INDIRECT_IO_SMU_READ INDIRECT_IO_SMU | INDIRECT_READ7378#define INDIRECT_IO_SMU_WRITE INDIRECT_IO_SMU | INDIRECT_WRITE737973807381typedef struct _ATOM_OEM_INFO7382{7383ATOM_COMMON_TABLE_HEADER sHeader;7384ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;7385}ATOM_OEM_INFO;73867387typedef struct _ATOM_TV_MODE7388{7389UCHAR ucVMode_Num; //Video mode number7390UCHAR ucTV_Mode_Num; //Internal TV mode number7391}ATOM_TV_MODE;73927393typedef struct _ATOM_BIOS_INT_TVSTD_MODE7394{7395ATOM_COMMON_TABLE_HEADER sHeader;7396USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table7397USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table7398USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table7399USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table7400USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table7401}ATOM_BIOS_INT_TVSTD_MODE;740274037404typedef struct _ATOM_TV_MODE_SCALER_PTR7405{7406USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients7407USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients7408UCHAR ucTV_Mode_Num;7409}ATOM_TV_MODE_SCALER_PTR;74107411typedef struct _ATOM_STANDARD_VESA_TIMING7412{7413ATOM_COMMON_TABLE_HEADER sHeader;7414ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation7415}ATOM_STANDARD_VESA_TIMING;741674177418typedef struct _ATOM_STD_FORMAT7419{7420USHORT usSTD_HDisp;7421USHORT usSTD_VDisp;7422USHORT usSTD_RefreshRate;7423USHORT usReserved;7424}ATOM_STD_FORMAT;74257426typedef struct _ATOM_VESA_TO_EXTENDED_MODE7427{7428USHORT usVESA_ModeNumber;7429USHORT usExtendedModeNumber;7430}ATOM_VESA_TO_EXTENDED_MODE;74317432typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT7433{7434ATOM_COMMON_TABLE_HEADER sHeader;7435ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76];7436}ATOM_VESA_TO_INTENAL_MODE_LUT;74377438/*************** ATOM Memory Related Data Structure ***********************/7439typedef struct _ATOM_MEMORY_VENDOR_BLOCK{7440UCHAR ucMemoryType;7441UCHAR ucMemoryVendor;7442UCHAR ucAdjMCId;7443UCHAR ucDynClkId;7444ULONG ulDllResetClkRange;7445}ATOM_MEMORY_VENDOR_BLOCK;744674477448typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{7449#if ATOM_BIG_ENDIAN7450ULONG ucMemBlkId:8;7451ULONG ulMemClockRange:24;7452#else7453ULONG ulMemClockRange:24;7454ULONG ucMemBlkId:8;7455#endif7456}ATOM_MEMORY_SETTING_ID_CONFIG;74577458typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS7459{7460ATOM_MEMORY_SETTING_ID_CONFIG slAccess;7461ULONG ulAccess;7462}ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS;746374647465typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{7466ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID;7467ULONG aulMemData[1];7468}ATOM_MEMORY_SETTING_DATA_BLOCK;746974707471typedef struct _ATOM_INIT_REG_INDEX_FORMAT{7472USHORT usRegIndex; // MC register index7473UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf7474}ATOM_INIT_REG_INDEX_FORMAT;747574767477typedef struct _ATOM_INIT_REG_BLOCK{7478USHORT usRegIndexTblSize; //size of asRegIndexBuf7479USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK7480ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1];7481ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1];7482}ATOM_INIT_REG_BLOCK;74837484#define END_OF_REG_INDEX_BLOCK 0x0ffff7485#define END_OF_REG_DATA_BLOCK 0x000000007486#define ATOM_INIT_REG_MASK_FLAG 0x80 //Not used in BIOS7487#define CLOCK_RANGE_HIGHEST 0x00ffffff74887489#define VALUE_DWORD SIZEOF ULONG7490#define VALUE_SAME_AS_ABOVE 07491#define VALUE_MASK_DWORD 0x8474927493#define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1)7494#define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1)7495#define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1)7496//#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code7497#define ACCESS_PLACEHOLDER 0x80749874997500typedef struct _ATOM_MC_INIT_PARAM_TABLE7501{7502ATOM_COMMON_TABLE_HEADER sHeader;7503USHORT usAdjustARB_SEQDataOffset;7504USHORT usMCInitMemTypeTblOffset;7505USHORT usMCInitCommonTblOffset;7506USHORT usMCInitPowerDownTblOffset;7507ULONG ulARB_SEQDataBuf[32];7508ATOM_INIT_REG_BLOCK asMCInitMemType;7509ATOM_INIT_REG_BLOCK asMCInitCommon;7510}ATOM_MC_INIT_PARAM_TABLE;751175127513typedef struct _ATOM_REG_INIT_SETTING7514{7515USHORT usRegIndex;7516ULONG ulRegValue;7517}ATOM_REG_INIT_SETTING;75187519typedef struct _ATOM_MC_INIT_PARAM_TABLE_V2_17520{7521ATOM_COMMON_TABLE_HEADER sHeader;7522ULONG ulMCUcodeVersion;7523ULONG ulMCUcodeRomStartAddr;7524ULONG ulMCUcodeLength;7525USHORT usMcRegInitTableOffset; // offset of ATOM_REG_INIT_SETTING array for MC core register settings.7526USHORT usReserved; // offset of ATOM_INIT_REG_BLOCK for MC SEQ/PHY register setting7527}ATOM_MC_INIT_PARAM_TABLE_V2_1;752875297530#define _4Mx16 0x27531#define _4Mx32 0x37532#define _8Mx16 0x127533#define _8Mx32 0x137534#define _8Mx128 0x157535#define _16Mx16 0x227536#define _16Mx32 0x237537#define _16Mx128 0x257538#define _32Mx16 0x327539#define _32Mx32 0x337540#define _32Mx128 0x357541#define _64Mx8 0x417542#define _64Mx16 0x427543#define _64Mx32 0x437544#define _64Mx128 0x457545#define _128Mx8 0x517546#define _128Mx16 0x527547#define _128Mx32 0x537548#define _256Mx8 0x617549#define _256Mx16 0x627550#define _256Mx32 0x637551#define _512Mx8 0x717552#define _512Mx16 0x72755375547555#define SAMSUNG 0x17556#define INFINEON 0x27557#define ELPIDA 0x37558#define ETRON 0x47559#define NANYA 0x57560#define HYNIX 0x67561#define MOSEL 0x77562#define WINBOND 0x87563#define ESMT 0x97564#define MICRON 0xF75657566#define QIMONDA INFINEON7567#define PROMOS MOSEL7568#define KRETON INFINEON7569#define ELIXIR NANYA7570#define MEZZA ELPIDA757175727573/////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM/////////////75747575#define UCODE_ROM_START_ADDRESS 0x1b8007576#define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode75777578//uCode block header for reference75797580typedef struct _MCuCodeHeader7581{7582ULONG ulSignature;7583UCHAR ucRevision;7584UCHAR ucChecksum;7585UCHAR ucReserved1;7586UCHAR ucReserved2;7587USHORT usParametersLength;7588USHORT usUCodeLength;7589USHORT usReserved1;7590USHORT usReserved2;7591} MCuCodeHeader;75927593//////////////////////////////////////////////////////////////////////////////////75947595#define ATOM_MAX_NUMBER_OF_VRAM_MODULE 1675967597#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF7598typedef struct _ATOM_VRAM_MODULE_V17599{7600ULONG ulReserved;7601USHORT usEMRSValue;7602USHORT usMRSValue;7603USHORT usReserved;7604UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module7605UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved;7606UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender7607UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...7608UCHAR ucRow; // Number of Row,in power of 2;7609UCHAR ucColumn; // Number of Column,in power of 2;7610UCHAR ucBank; // Nunber of Bank;7611UCHAR ucRank; // Number of Rank, in power of 27612UCHAR ucChannelNum; // Number of channel;7613UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 27614UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;7615UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;7616UCHAR ucReserved[2];7617}ATOM_VRAM_MODULE_V1;761876197620typedef struct _ATOM_VRAM_MODULE_V27621{7622ULONG ulReserved;7623ULONG ulFlags; // To enable/disable functionalities based on memory type7624ULONG ulEngineClock; // Override of default engine clock for particular memory type7625ULONG ulMemoryClock; // Override of default memory clock for particular memory type7626USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type7627USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type7628USHORT usEMRSValue;7629USHORT usMRSValue;7630USHORT usReserved;7631UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module7632UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;7633UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed7634UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...7635UCHAR ucRow; // Number of Row,in power of 2;7636UCHAR ucColumn; // Number of Column,in power of 2;7637UCHAR ucBank; // Nunber of Bank;7638UCHAR ucRank; // Number of Rank, in power of 27639UCHAR ucChannelNum; // Number of channel;7640UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 27641UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;7642UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;7643UCHAR ucRefreshRateFactor;7644UCHAR ucReserved[3];7645}ATOM_VRAM_MODULE_V2;764676477648typedef struct _ATOM_MEMORY_TIMING_FORMAT7649{7650ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing7651union{7652USHORT usMRS; // mode register7653USHORT usDDR3_MR0;7654};7655union{7656USHORT usEMRS; // extended mode register7657USHORT usDDR3_MR1;7658};7659UCHAR ucCL; // CAS latency7660UCHAR ucWL; // WRITE Latency7661UCHAR uctRAS; // tRAS7662UCHAR uctRC; // tRC7663UCHAR uctRFC; // tRFC7664UCHAR uctRCDR; // tRCDR7665UCHAR uctRCDW; // tRCDW7666UCHAR uctRP; // tRP7667UCHAR uctRRD; // tRRD7668UCHAR uctWR; // tWR7669UCHAR uctWTR; // tWTR7670UCHAR uctPDIX; // tPDIX7671UCHAR uctFAW; // tFAW7672UCHAR uctAOND; // tAOND7673union7674{7675struct {7676UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon7677UCHAR ucReserved;7678};7679USHORT usDDR3_MR2;7680};7681}ATOM_MEMORY_TIMING_FORMAT;768276837684typedef struct _ATOM_MEMORY_TIMING_FORMAT_V17685{7686ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing7687USHORT usMRS; // mode register7688USHORT usEMRS; // extended mode register7689UCHAR ucCL; // CAS latency7690UCHAR ucWL; // WRITE Latency7691UCHAR uctRAS; // tRAS7692UCHAR uctRC; // tRC7693UCHAR uctRFC; // tRFC7694UCHAR uctRCDR; // tRCDR7695UCHAR uctRCDW; // tRCDW7696UCHAR uctRP; // tRP7697UCHAR uctRRD; // tRRD7698UCHAR uctWR; // tWR7699UCHAR uctWTR; // tWTR7700UCHAR uctPDIX; // tPDIX7701UCHAR uctFAW; // tFAW7702UCHAR uctAOND; // tAOND7703UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon7704////////////////////////////////////GDDR parameters///////////////////////////////////7705UCHAR uctCCDL; //7706UCHAR uctCRCRL; //7707UCHAR uctCRCWL; //7708UCHAR uctCKE; //7709UCHAR uctCKRSE; //7710UCHAR uctCKRSX; //7711UCHAR uctFAW32; //7712UCHAR ucMR5lo; //7713UCHAR ucMR5hi; //7714UCHAR ucTerminator;7715}ATOM_MEMORY_TIMING_FORMAT_V1;77167717771877197720typedef struct _ATOM_MEMORY_TIMING_FORMAT_V27721{7722ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing7723USHORT usMRS; // mode register7724USHORT usEMRS; // extended mode register7725UCHAR ucCL; // CAS latency7726UCHAR ucWL; // WRITE Latency7727UCHAR uctRAS; // tRAS7728UCHAR uctRC; // tRC7729UCHAR uctRFC; // tRFC7730UCHAR uctRCDR; // tRCDR7731UCHAR uctRCDW; // tRCDW7732UCHAR uctRP; // tRP7733UCHAR uctRRD; // tRRD7734UCHAR uctWR; // tWR7735UCHAR uctWTR; // tWTR7736UCHAR uctPDIX; // tPDIX7737UCHAR uctFAW; // tFAW7738UCHAR uctAOND; // tAOND7739UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon7740////////////////////////////////////GDDR parameters///////////////////////////////////7741UCHAR uctCCDL; //7742UCHAR uctCRCRL; //7743UCHAR uctCRCWL; //7744UCHAR uctCKE; //7745UCHAR uctCKRSE; //7746UCHAR uctCKRSX; //7747UCHAR uctFAW32; //7748UCHAR ucMR4lo; //7749UCHAR ucMR4hi; //7750UCHAR ucMR5lo; //7751UCHAR ucMR5hi; //7752UCHAR ucTerminator;7753UCHAR ucReserved;7754}ATOM_MEMORY_TIMING_FORMAT_V2;775577567757typedef struct _ATOM_MEMORY_FORMAT7758{7759ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock7760union{7761USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type7762USHORT usDDR3_Reserved; // Not used for DDR3 memory7763};7764union{7765USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type7766USHORT usDDR3_MR3; // Used for DDR3 memory7767};7768UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;7769UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed7770UCHAR ucRow; // Number of Row,in power of 2;7771UCHAR ucColumn; // Number of Column,in power of 2;7772UCHAR ucBank; // Nunber of Bank;7773UCHAR ucRank; // Number of Rank, in power of 27774UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=87775UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )7776UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms7777UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx167778UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble7779UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc7780ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; // Memory Timing block sort from lower clock to higher clock7781}ATOM_MEMORY_FORMAT;778277837784typedef struct _ATOM_VRAM_MODULE_V37785{7786ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination7787USHORT usSize; // size of ATOM_VRAM_MODULE_V37788USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage7789USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage7790UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module7791UCHAR ucChannelNum; // board dependent parameter:Number of channel;7792UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit7793UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv7794UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters7795UCHAR ucFlag; // To enable/disable functionalities based on memory type7796ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec7797}ATOM_VRAM_MODULE_V3;779877997800//ATOM_VRAM_MODULE_V3.ucNPL_RT7801#define NPL_RT_MASK 0x0f7802#define BATTERY_ODT_MASK 0xc078037804#define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V378057806typedef struct _ATOM_VRAM_MODULE_V47807{7808ULONG ulChannelMapCfg; // board dependent parameter: Channel combination7809USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE7810USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!7811// MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)7812USHORT usReserved;7813UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module7814UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;7815UCHAR ucChannelNum; // Number of channels present in this module config7816UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits7817UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx167818UCHAR ucFlag; // To enable/disable functionalities based on memory type7819UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 87820UCHAR ucVREFI; // board dependent parameter7821UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters7822UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble7823UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!7824// Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros7825UCHAR ucReserved[3];78267827//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level7828union{7829USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type7830USHORT usDDR3_Reserved;7831};7832union{7833USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type7834USHORT usDDR3_MR3; // Used for DDR3 memory7835};7836UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed7837UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)7838UCHAR ucReserved2[2];7839ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock7840}ATOM_VRAM_MODULE_V4;78417842#define VRAM_MODULE_V4_MISC_RANK_MASK 0x37843#define VRAM_MODULE_V4_MISC_DUAL_RANK 0x17844#define VRAM_MODULE_V4_MISC_BL_MASK 0x47845#define VRAM_MODULE_V4_MISC_BL8 0x47846#define VRAM_MODULE_V4_MISC_DUAL_CS 0x1078477848typedef struct _ATOM_VRAM_MODULE_V57849{7850ULONG ulChannelMapCfg; // board dependent parameter: Channel combination7851USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE7852USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!7853// MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)7854USHORT usReserved;7855UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module7856UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;7857UCHAR ucChannelNum; // Number of channels present in this module config7858UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits7859UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx167860UCHAR ucFlag; // To enable/disable functionalities based on memory type7861UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 87862UCHAR ucVREFI; // board dependent parameter7863UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters7864UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble7865UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!7866// Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros7867UCHAR ucReserved[3];78687869//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level7870USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type7871USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type7872UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed7873UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)7874UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth7875UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth7876ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock7877}ATOM_VRAM_MODULE_V5;787878797880typedef struct _ATOM_VRAM_MODULE_V67881{7882ULONG ulChannelMapCfg; // board dependent parameter: Channel combination7883USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE7884USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!7885// MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)7886USHORT usReserved;7887UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module7888UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;7889UCHAR ucChannelNum; // Number of channels present in this module config7890UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits7891UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx167892UCHAR ucFlag; // To enable/disable functionalities based on memory type7893UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 87894UCHAR ucVREFI; // board dependent parameter7895UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters7896UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble7897UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!7898// Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros7899UCHAR ucReserved[3];79007901//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level7902USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type7903USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type7904UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed7905UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)7906UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth7907UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth7908ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock7909}ATOM_VRAM_MODULE_V6;79107911typedef struct _ATOM_VRAM_MODULE_V77912{7913// Design Specific Values7914ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP7915USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V77916USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)7917USHORT usEnableChannels; // bit vector which indicate which channels are enabled7918UCHAR ucExtMemoryID; // Current memory module ID7919UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR57920UCHAR ucChannelNum; // Number of mem. channels supported in this module7921UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT7922UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx167923UCHAR ucReserve; // In MC7x, the lower 4 bits are used as bit8-11 of memory size. In other MC code, it's not used.7924UCHAR ucMisc; // RANK_OF_THISMEMORY etc.7925UCHAR ucVREFI; // Not used.7926UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.7927UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble7928UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros7929USHORT usSEQSettingOffset;7930UCHAR ucReserved;7931// Memory Module specific values7932USHORT usEMRS2Value; // EMRS2/MR2 Value.7933USHORT usEMRS3Value; // EMRS3/MR3 Value.7934UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code7935UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)7936UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory7937UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth7938char strMemPNString[20]; // part number end with '0'.7939}ATOM_VRAM_MODULE_V7;794079417942typedef struct _ATOM_VRAM_MODULE_V87943{7944// Design Specific Values7945ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP7946USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V77947USHORT usMcRamCfg; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)7948USHORT usEnableChannels; // bit vector which indicate which channels are enabled7949UCHAR ucExtMemoryID; // Current memory module ID7950UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR57951UCHAR ucChannelNum; // Number of mem. channels supported in this module7952UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT7953UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx167954UCHAR ucBankCol; // bit[3:2]= BANK ( =2:16bank, =1:8bank, =0:4bank ) bit[1:0]=Col ( =2: 10 bit, =1:9bit, =0:8bit )7955UCHAR ucMisc; // RANK_OF_THISMEMORY etc.7956UCHAR ucVREFI; // Not used.7957USHORT usReserved; // Not used7958USHORT usMemorySize; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros7959UCHAR ucMcTunningSetId; // MC phy registers set per.7960UCHAR ucRowNum;7961// Memory Module specific values7962USHORT usEMRS2Value; // EMRS2/MR2 Value.7963USHORT usEMRS3Value; // EMRS3/MR3 Value.7964UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code7965UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)7966UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory7967UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth79687969ULONG ulChannelMapCfg1; // channel mapping for channel8~157970ULONG ulBankMapCfg;7971ULONG ulReserved;7972char strMemPNString[20]; // part number end with '0'.7973}ATOM_VRAM_MODULE_V8;797479757976typedef struct _ATOM_VRAM_INFO_V27977{7978ATOM_COMMON_TABLE_HEADER sHeader;7979UCHAR ucNumOfVRAMModule;7980ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;7981}ATOM_VRAM_INFO_V2;79827983typedef struct _ATOM_VRAM_INFO_V37984{7985ATOM_COMMON_TABLE_HEADER sHeader;7986USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting7987USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting7988USHORT usRerseved;7989UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator7990UCHAR ucNumOfVRAMModule;7991ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;7992ATOM_INIT_REG_BLOCK asMemPatch; // for allocation79937994}ATOM_VRAM_INFO_V3;79957996#define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V379977998typedef struct _ATOM_VRAM_INFO_V47999{8000ATOM_COMMON_TABLE_HEADER sHeader;8001USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting8002USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting8003USHORT usRerseved;8004UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE38005ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21]8006UCHAR ucReservde[4];8007UCHAR ucNumOfVRAMModule;8008ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;8009ATOM_INIT_REG_BLOCK asMemPatch; // for allocation8010}ATOM_VRAM_INFO_V4;80118012typedef struct _ATOM_VRAM_INFO_HEADER_V2_18013{8014ATOM_COMMON_TABLE_HEADER sHeader;8015USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting8016USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting8017USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings8018USHORT usReserved[3];8019UCHAR ucNumOfVRAMModule; // indicate number of VRAM module8020UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list8021UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version8022UCHAR ucReserved;8023ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;8024}ATOM_VRAM_INFO_HEADER_V2_1;80258026typedef struct _ATOM_VRAM_INFO_HEADER_V2_28027{8028ATOM_COMMON_TABLE_HEADER sHeader;8029USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting8030USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting8031USHORT usMcAdjustPerTileTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings8032USHORT usMcPhyInitTableOffset; // offset of ATOM_INIT_REG_BLOCK structure for MC phy init set8033USHORT usDramDataRemapTblOffset; // offset of ATOM_DRAM_DATA_REMAP array to indicate DRAM data lane to GPU mapping8034USHORT usReserved1;8035UCHAR ucNumOfVRAMModule; // indicate number of VRAM module8036UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list8037UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version8038UCHAR ucMcPhyTileNum; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset8039ATOM_VRAM_MODULE_V8 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;8040}ATOM_VRAM_INFO_HEADER_V2_2;804180428043typedef struct _ATOM_DRAM_DATA_REMAP8044{8045UCHAR ucByteRemapCh0;8046UCHAR ucByteRemapCh1;8047ULONG ulByte0BitRemapCh0;8048ULONG ulByte1BitRemapCh0;8049ULONG ulByte2BitRemapCh0;8050ULONG ulByte3BitRemapCh0;8051ULONG ulByte0BitRemapCh1;8052ULONG ulByte1BitRemapCh1;8053ULONG ulByte2BitRemapCh1;8054ULONG ulByte3BitRemapCh1;8055}ATOM_DRAM_DATA_REMAP;80568057typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO8058{8059ATOM_COMMON_TABLE_HEADER sHeader;8060UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator8061}ATOM_VRAM_GPIO_DETECTION_INFO;806280638064typedef struct _ATOM_MEMORY_TRAINING_INFO8065{8066ATOM_COMMON_TABLE_HEADER sHeader;8067UCHAR ucTrainingLoop;8068UCHAR ucReserved[3];8069ATOM_INIT_REG_BLOCK asMemTrainingSetting;8070}ATOM_MEMORY_TRAINING_INFO;807180728073typedef struct _ATOM_MEMORY_TRAINING_INFO_V3_18074{8075ATOM_COMMON_TABLE_HEADER sHeader;8076ULONG ulMCUcodeVersion;8077USHORT usMCIOInitLen; //len of ATOM_REG_INIT_SETTING array8078USHORT usMCUcodeLen; //len of ATOM_MC_UCODE_DATA array8079USHORT usMCIORegInitOffset; //point of offset of ATOM_REG_INIT_SETTING array8080USHORT usMCUcodeOffset; //point of offset of MC uCode ULONG array.8081}ATOM_MEMORY_TRAINING_INFO_V3_1;808280838084typedef struct SW_I2C_CNTL_DATA_PARAMETERS8085{8086UCHAR ucControl;8087UCHAR ucData;8088UCHAR ucSatus;8089UCHAR ucTemp;8090} SW_I2C_CNTL_DATA_PARAMETERS;80918092#define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS80938094typedef struct _SW_I2C_IO_DATA_PARAMETERS8095{8096USHORT GPIO_Info;8097UCHAR ucAct;8098UCHAR ucData;8099} SW_I2C_IO_DATA_PARAMETERS;81008101#define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS81028103/****************************SW I2C CNTL DEFINITIONS**********************/8104#define SW_I2C_IO_RESET 08105#define SW_I2C_IO_GET 18106#define SW_I2C_IO_DRIVE 28107#define SW_I2C_IO_SET 38108#define SW_I2C_IO_START 481098110#define SW_I2C_IO_CLOCK 08111#define SW_I2C_IO_DATA 0x8081128113#define SW_I2C_IO_ZERO 08114#define SW_I2C_IO_ONE 0x10081158116#define SW_I2C_CNTL_READ 08117#define SW_I2C_CNTL_WRITE 18118#define SW_I2C_CNTL_START 28119#define SW_I2C_CNTL_STOP 38120#define SW_I2C_CNTL_OPEN 48121#define SW_I2C_CNTL_CLOSE 58122#define SW_I2C_CNTL_WRITE1BIT 681238124//==============================VESA definition Portion===============================8125#define VESA_OEM_PRODUCT_REV '01.00'8126#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support8127#define VESA_MODE_WIN_ATTRIBUTE 78128#define VESA_WIN_SIZE 6481298130typedef struct _PTR_32_BIT_STRUCTURE8131{8132USHORT Offset16;8133USHORT Segment16;8134} PTR_32_BIT_STRUCTURE;81358136typedef union _PTR_32_BIT_UNION8137{8138PTR_32_BIT_STRUCTURE SegmentOffset;8139ULONG Ptr32_Bit;8140} PTR_32_BIT_UNION;81418142typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE8143{8144UCHAR VbeSignature[4];8145USHORT VbeVersion;8146PTR_32_BIT_UNION OemStringPtr;8147UCHAR Capabilities[4];8148PTR_32_BIT_UNION VideoModePtr;8149USHORT TotalMemory;8150} VBE_1_2_INFO_BLOCK_UPDATABLE;815181528153typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE8154{8155VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock;8156USHORT OemSoftRev;8157PTR_32_BIT_UNION OemVendorNamePtr;8158PTR_32_BIT_UNION OemProductNamePtr;8159PTR_32_BIT_UNION OemProductRevPtr;8160} VBE_2_0_INFO_BLOCK_UPDATABLE;81618162typedef union _VBE_VERSION_UNION8163{8164VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock;8165VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock;8166} VBE_VERSION_UNION;81678168typedef struct _VBE_INFO_BLOCK8169{8170VBE_VERSION_UNION UpdatableVBE_Info;8171UCHAR Reserved[222];8172UCHAR OemData[256];8173} VBE_INFO_BLOCK;81748175typedef struct _VBE_FP_INFO8176{8177USHORT HSize;8178USHORT VSize;8179USHORT FPType;8180UCHAR RedBPP;8181UCHAR GreenBPP;8182UCHAR BlueBPP;8183UCHAR ReservedBPP;8184ULONG RsvdOffScrnMemSize;8185ULONG RsvdOffScrnMEmPtr;8186UCHAR Reserved[14];8187} VBE_FP_INFO;81888189typedef struct _VESA_MODE_INFO_BLOCK8190{8191// Mandatory information for all VBE revisions8192USHORT ModeAttributes; // dw ? ; mode attributes8193UCHAR WinAAttributes; // db ? ; window A attributes8194UCHAR WinBAttributes; // db ? ; window B attributes8195USHORT WinGranularity; // dw ? ; window granularity8196USHORT WinSize; // dw ? ; window size8197USHORT WinASegment; // dw ? ; window A start segment8198USHORT WinBSegment; // dw ? ; window B start segment8199ULONG WinFuncPtr; // dd ? ; real mode pointer to window function8200USHORT BytesPerScanLine;// dw ? ; bytes per scan line82018202//; Mandatory information for VBE 1.2 and above8203USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters8204USHORT YResolution; // dw ? ; vertical resolution in pixels or characters8205UCHAR XCharSize; // db ? ; character cell width in pixels8206UCHAR YCharSize; // db ? ; character cell height in pixels8207UCHAR NumberOfPlanes; // db ? ; number of memory planes8208UCHAR BitsPerPixel; // db ? ; bits per pixel8209UCHAR NumberOfBanks; // db ? ; number of banks8210UCHAR MemoryModel; // db ? ; memory model type8211UCHAR BankSize; // db ? ; bank size in KB8212UCHAR NumberOfImagePages;// db ? ; number of images8213UCHAR ReservedForPageFunction;//db 1 ; reserved for page function82148215//; Direct Color fields(required for direct/6 and YUV/7 memory models)8216UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits8217UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask8218UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits8219UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask8220UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits8221UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask8222UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits8223UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask8224UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes82258226//; Mandatory information for VBE 2.0 and above8227ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer8228ULONG Reserved_1; // dd 0 ; reserved - always set to 08229USHORT Reserved_2; // dw 0 ; reserved - always set to 082308231//; Mandatory information for VBE 3.0 and above8232USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes8233UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes8234UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes8235UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes)8236UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes)8237UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes)8238UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes)8239UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes)8240UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes)8241UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes)8242UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes)8243ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode8244UCHAR Reserved; // db 190 dup (0)8245} VESA_MODE_INFO_BLOCK;82468247// BIOS function CALLS8248#define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code8249#define ATOM_BIOS_FUNCTION_COP_MODE 0x008250#define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x048251#define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x058252#define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x068253#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B8254#define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E8255#define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F8256#define ATOM_BIOS_FUNCTION_STV_STD 0x168257#define ATOM_BIOS_FUNCTION_DEVICE_DET 0x178258#define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x1882598260#define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x828261#define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x838262#define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x848263#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A8264#define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B8265#define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 808266#define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 8082678268#define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D8269#define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E8270#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F8271#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 038272#define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 78273#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state8274#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state8275#define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 858276#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 898277#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported827882798280#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS8281#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 018282#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 028283#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON.8284#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY8285#define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND8286#define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF8287#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED)82888289#define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L8290#define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L8291#define ATOM_BIOS_REG_LOW_MASK 0x000000FFL82928293// structure used for VBIOS only82948295//DispOutInfoTable8296typedef struct _ASIC_TRANSMITTER_INFO8297{8298USHORT usTransmitterObjId;8299USHORT usSupportDevice;8300UCHAR ucTransmitterCmdTblId;8301UCHAR ucConfig;8302UCHAR ucEncoderID; //available 1st encoder ( default )8303UCHAR ucOptionEncoderID; //available 2nd encoder ( optional )8304UCHAR uc2ndEncoderID;8305UCHAR ucReserved;8306}ASIC_TRANSMITTER_INFO;83078308#define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x018309#define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x028310#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc48311#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x008312#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x048313#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x408314#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x448315#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x808316#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x8483178318typedef struct _ASIC_ENCODER_INFO8319{8320UCHAR ucEncoderID;8321UCHAR ucEncoderConfig;8322USHORT usEncoderCmdTblId;8323}ASIC_ENCODER_INFO;83248325typedef struct _ATOM_DISP_OUT_INFO8326{8327ATOM_COMMON_TABLE_HEADER sHeader;8328USHORT ptrTransmitterInfo;8329USHORT ptrEncoderInfo;8330ASIC_TRANSMITTER_INFO asTransmitterInfo[1];8331ASIC_ENCODER_INFO asEncoderInfo[1];8332}ATOM_DISP_OUT_INFO;833383348335typedef struct _ATOM_DISP_OUT_INFO_V28336{8337ATOM_COMMON_TABLE_HEADER sHeader;8338USHORT ptrTransmitterInfo;8339USHORT ptrEncoderInfo;8340USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary.8341ASIC_TRANSMITTER_INFO asTransmitterInfo[1];8342ASIC_ENCODER_INFO asEncoderInfo[1];8343}ATOM_DISP_OUT_INFO_V2;834483458346typedef struct _ATOM_DISP_CLOCK_ID {8347UCHAR ucPpllId;8348UCHAR ucPpllAttribute;8349}ATOM_DISP_CLOCK_ID;83508351// ucPpllAttribute8352#define CLOCK_SOURCE_SHAREABLE 0x018353#define CLOCK_SOURCE_DP_MODE 0x028354#define CLOCK_SOURCE_NONE_DP_MODE 0x0483558356//DispOutInfoTable8357typedef struct _ASIC_TRANSMITTER_INFO_V28358{8359USHORT usTransmitterObjId;8360USHORT usDispClkIdOffset; // point to clock source id list supported by Encoder Object8361UCHAR ucTransmitterCmdTblId;8362UCHAR ucConfig;8363UCHAR ucEncoderID; // available 1st encoder ( default )8364UCHAR ucOptionEncoderID; // available 2nd encoder ( optional )8365UCHAR uc2ndEncoderID;8366UCHAR ucReserved;8367}ASIC_TRANSMITTER_INFO_V2;83688369typedef struct _ATOM_DISP_OUT_INFO_V38370{8371ATOM_COMMON_TABLE_HEADER sHeader;8372USHORT ptrTransmitterInfo;8373USHORT ptrEncoderInfo;8374USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary.8375USHORT usReserved;8376UCHAR ucDCERevision;8377UCHAR ucMaxDispEngineNum;8378UCHAR ucMaxActiveDispEngineNum;8379UCHAR ucMaxPPLLNum;8380UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE8381UCHAR ucDispCaps;8382UCHAR ucReserved[2];8383ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only8384}ATOM_DISP_OUT_INFO_V3;83858386//ucDispCaps8387#define DISPLAY_CAPS__DP_PCLK_FROM_PPLL 0x018388#define DISPLAY_CAPS__FORCE_DISPDEV_CONNECTED 0x0283898390typedef enum CORE_REF_CLK_SOURCE{8391CLOCK_SRC_XTALIN=0,8392CLOCK_SRC_XO_IN=1,8393CLOCK_SRC_XO_IN2=2,8394}CORE_REF_CLK_SOURCE;83958396// DispDevicePriorityInfo8397typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO8398{8399ATOM_COMMON_TABLE_HEADER sHeader;8400USHORT asDevicePriority[16];8401}ATOM_DISPLAY_DEVICE_PRIORITY_INFO;84028403//ProcessAuxChannelTransactionTable8404typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS8405{8406USHORT lpAuxRequest;8407USHORT lpDataOut;8408UCHAR ucChannelID;8409union8410{8411UCHAR ucReplyStatus;8412UCHAR ucDelay;8413};8414UCHAR ucDataOutLen;8415UCHAR ucReserved;8416}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS;84178418//ProcessAuxChannelTransactionTable8419typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V28420{8421USHORT lpAuxRequest;8422USHORT lpDataOut;8423UCHAR ucChannelID;8424union8425{8426UCHAR ucReplyStatus;8427UCHAR ucDelay;8428};8429UCHAR ucDataOutLen;8430UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD68431}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2;84328433#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS84348435//GetSinkType84368437typedef struct _DP_ENCODER_SERVICE_PARAMETERS8438{8439USHORT ucLinkClock;8440union8441{8442UCHAR ucConfig; // for DP training command8443UCHAR ucI2cId; // use for GET_SINK_TYPE command8444};8445UCHAR ucAction;8446UCHAR ucStatus;8447UCHAR ucLaneNum;8448UCHAR ucReserved[2];8449}DP_ENCODER_SERVICE_PARAMETERS;84508451// ucAction8452#define ATOM_DP_ACTION_GET_SINK_TYPE 0x0184538454#define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS845584568457typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V28458{8459USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION8460UCHAR ucAuxId;8461UCHAR ucAction;8462UCHAR ucSinkType; // Iput and Output parameters.8463UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION8464UCHAR ucReserved[2];8465}DP_ENCODER_SERVICE_PARAMETERS_V2;84668467typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V28468{8469DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam;8470PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam;8471}DP_ENCODER_SERVICE_PS_ALLOCATION_V2;84728473// ucAction8474#define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x018475#define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02847684778478// DP_TRAINING_TABLE8479#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR8480#define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 )8481#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 )8482#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 )8483#define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32)8484#define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40)8485#define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48)8486#define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60)8487#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64)8488#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72)8489#define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76)8490#define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80)8491#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84)849284938494typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS8495{8496UCHAR ucI2CSpeed;8497union8498{8499UCHAR ucRegIndex;8500UCHAR ucStatus;8501};8502USHORT lpI2CDataOut;8503UCHAR ucFlag;8504UCHAR ucTransBytes;8505UCHAR ucSlaveAddr;8506UCHAR ucLineNumber;8507}PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS;85088509#define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS85108511//ucFlag8512#define HW_I2C_WRITE 18513#define HW_I2C_READ 08514#define I2C_2BYTE_ADDR 0x0285158516/****************************************************************************/8517// Structures used by HW_Misc_OperationTable8518/****************************************************************************/8519typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_18520{8521UCHAR ucCmd; // Input: To tell which action to take8522UCHAR ucReserved[3];8523ULONG ulReserved;8524}ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1;85258526typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_18527{8528UCHAR ucReturnCode; // Output: Return value base on action was taken8529UCHAR ucReserved[3];8530ULONG ulReserved;8531}ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1;85328533// Actions code8534#define ATOM_GET_SDI_SUPPORT 0xF085358536// Return code8537#define ATOM_UNKNOWN_CMD 08538#define ATOM_FEATURE_NOT_SUPPORTED 18539#define ATOM_FEATURE_SUPPORTED 285408541typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION8542{8543ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 sInput_Output;8544PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved;8545}ATOM_HW_MISC_OPERATION_PS_ALLOCATION;85468547/****************************************************************************/85488549typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V28550{8551UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ...8552UCHAR ucReserved[3];8553}SET_HWBLOCK_INSTANCE_PARAMETER_V2;85548555#define HWBLKINST_INSTANCE_MASK 0x078556#define HWBLKINST_HWBLK_MASK 0xF08557#define HWBLKINST_HWBLK_SHIFT 0x0485588559//ucHWBlock8560#define SELECT_DISP_ENGINE 08561#define SELECT_DISP_PLL 18562#define SELECT_DCIO_UNIPHY_LINK0 28563#define SELECT_DCIO_UNIPHY_LINK1 38564#define SELECT_DCIO_IMPCAL 48565#define SELECT_DCIO_DIG 68566#define SELECT_CRTC_PIXEL_RATE 78567#define SELECT_VGA_BLK 885688569// DIGTransmitterInfoTable structure used to program UNIPHY settings8570typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{8571ATOM_COMMON_TABLE_HEADER sHeader;8572USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock8573USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info8574USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range8575USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info8576USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings8577}DIG_TRANSMITTER_INFO_HEADER_V3_1;85788579typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{8580ATOM_COMMON_TABLE_HEADER sHeader;8581USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock8582USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info8583USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range8584USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info8585USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings8586USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info8587USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings8588}DIG_TRANSMITTER_INFO_HEADER_V3_2;858985908591typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_3{8592ATOM_COMMON_TABLE_HEADER sHeader;8593USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock8594USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info8595USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range8596USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info8597USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings8598USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info8599USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings8600USHORT usEDPVsLegacyModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Legacy Mode Voltage Swing and Pre-Emphasis for each Link clock8601USHORT useDPVsLowVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Low VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock8602USHORT useDPVsHighVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP High VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock8603USHORT useDPVsStretchModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Stretch Mode Voltage Swing and Pre-Emphasis for each Link clock8604USHORT useDPVsSingleVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vdiff Mode Voltage Swing and Pre-Emphasis for each Link clock8605USHORT useDPVsVariablePremModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vidff+Variable PreEmphasis Voltage Swing and Pre-Emphasis for each Link clock8606}DIG_TRANSMITTER_INFO_HEADER_V3_3;860786088609typedef struct _CLOCK_CONDITION_REGESTER_INFO{8610USHORT usRegisterIndex;8611UCHAR ucStartBit;8612UCHAR ucEndBit;8613}CLOCK_CONDITION_REGESTER_INFO;86148615typedef struct _CLOCK_CONDITION_SETTING_ENTRY{8616USHORT usMaxClockFreq;8617UCHAR ucEncodeMode;8618UCHAR ucPhySel;8619ULONG ulAnalogSetting[1];8620}CLOCK_CONDITION_SETTING_ENTRY;86218622typedef struct _CLOCK_CONDITION_SETTING_INFO{8623USHORT usEntrySize;8624CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1];8625}CLOCK_CONDITION_SETTING_INFO;86268627typedef struct _PHY_CONDITION_REG_VAL{8628ULONG ulCondition;8629ULONG ulRegVal;8630}PHY_CONDITION_REG_VAL;86318632typedef struct _PHY_CONDITION_REG_VAL_V2{8633ULONG ulCondition;8634UCHAR ucCondition2;8635ULONG ulRegVal;8636}PHY_CONDITION_REG_VAL_V2;86378638typedef struct _PHY_CONDITION_REG_INFO{8639USHORT usRegIndex;8640USHORT usSize;8641PHY_CONDITION_REG_VAL asRegVal[1];8642}PHY_CONDITION_REG_INFO;86438644typedef struct _PHY_CONDITION_REG_INFO_V2{8645USHORT usRegIndex;8646USHORT usSize;8647PHY_CONDITION_REG_VAL_V2 asRegVal[1];8648}PHY_CONDITION_REG_INFO_V2;86498650typedef struct _PHY_ANALOG_SETTING_INFO{8651UCHAR ucEncodeMode;8652UCHAR ucPhySel;8653USHORT usSize;8654PHY_CONDITION_REG_INFO asAnalogSetting[1];8655}PHY_ANALOG_SETTING_INFO;86568657typedef struct _PHY_ANALOG_SETTING_INFO_V2{8658UCHAR ucEncodeMode;8659UCHAR ucPhySel;8660USHORT usSize;8661PHY_CONDITION_REG_INFO_V2 asAnalogSetting[1];8662}PHY_ANALOG_SETTING_INFO_V2;866386648665typedef struct _GFX_HAVESTING_PARAMETERS {8666UCHAR ucGfxBlkId; //GFX blk id to be harvested, like CU, RB or PRIM8667UCHAR ucReserved; //reserved8668UCHAR ucActiveUnitNumPerSH; //requested active CU/RB/PRIM number per shader array8669UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array8670} GFX_HAVESTING_PARAMETERS;86718672//ucGfxBlkId8673#define GFX_HARVESTING_CU_ID 08674#define GFX_HARVESTING_RB_ID 18675#define GFX_HARVESTING_PRIM_ID 2867686778678typedef struct _VBIOS_ROM_HEADER{8679UCHAR PciRomSignature[2];8680UCHAR ucPciRomSizeIn512bytes;8681UCHAR ucJumpCoreMainInitBIOS;8682USHORT usLabelCoreMainInitBIOS;8683UCHAR PciReservedSpace[18];8684USHORT usPciDataStructureOffset;8685UCHAR Rsvd1d_1a[4];8686char strIbm[3];8687UCHAR CheckSum[14];8688UCHAR ucBiosMsgNumber;8689char str761295520[16];8690USHORT usLabelCoreVPOSTNoMode;8691USHORT usSpecialPostOffset;8692UCHAR ucSpeicalPostImageSizeIn512Bytes;8693UCHAR Rsved47_45[3];8694USHORT usROM_HeaderInformationTableOffset;8695UCHAR Rsved4f_4a[6];8696char strBuildTimeStamp[20];8697UCHAR ucJumpCoreXFuncFarHandler;8698USHORT usCoreXFuncFarHandlerOffset;8699UCHAR ucRsved67;8700UCHAR ucJumpCoreVFuncFarHandler;8701USHORT usCoreVFuncFarHandlerOffset;8702UCHAR Rsved6d_6b[3];8703USHORT usATOM_BIOS_MESSAGE_Offset;8704}VBIOS_ROM_HEADER;87058706/****************************************************************************/8707//Portion VI: Definitinos for vbios MC scratch registers that driver used8708/****************************************************************************/87098710#define MC_MISC0__MEMORY_TYPE_MASK 0xF00000008711#define MC_MISC0__MEMORY_TYPE__GDDR1 0x100000008712#define MC_MISC0__MEMORY_TYPE__DDR2 0x200000008713#define MC_MISC0__MEMORY_TYPE__GDDR3 0x300000008714#define MC_MISC0__MEMORY_TYPE__GDDR4 0x400000008715#define MC_MISC0__MEMORY_TYPE__GDDR5 0x500000008716#define MC_MISC0__MEMORY_TYPE__HBM 0x600000008717#define MC_MISC0__MEMORY_TYPE__DDR3 0xB000000087188719#define ATOM_MEM_TYPE_DDR_STRING "DDR"8720#define ATOM_MEM_TYPE_DDR2_STRING "DDR2"8721#define ATOM_MEM_TYPE_GDDR3_STRING "GDDR3"8722#define ATOM_MEM_TYPE_GDDR4_STRING "GDDR4"8723#define ATOM_MEM_TYPE_GDDR5_STRING "GDDR5"8724#define ATOM_MEM_TYPE_HBM_STRING "HBM"8725#define ATOM_MEM_TYPE_DDR3_STRING "DDR3"87268727/****************************************************************************/8728//Portion VII: Definitinos being oboselete8729/****************************************************************************/87308731//==========================================================================================8732//Remove the definitions below when driver is ready!8733typedef struct _ATOM_DAC_INFO8734{8735ATOM_COMMON_TABLE_HEADER sHeader;8736USHORT usMaxFrequency; // in 10kHz unit8737USHORT usReserved;8738}ATOM_DAC_INFO;873987408741typedef struct _COMPASSIONATE_DATA8742{8743ATOM_COMMON_TABLE_HEADER sHeader;87448745//============================== DAC1 portion8746UCHAR ucDAC1_BG_Adjustment;8747UCHAR ucDAC1_DAC_Adjustment;8748USHORT usDAC1_FORCE_Data;8749//============================== DAC2 portion8750UCHAR ucDAC2_CRT2_BG_Adjustment;8751UCHAR ucDAC2_CRT2_DAC_Adjustment;8752USHORT usDAC2_CRT2_FORCE_Data;8753USHORT usDAC2_CRT2_MUX_RegisterIndex;8754UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low8755UCHAR ucDAC2_NTSC_BG_Adjustment;8756UCHAR ucDAC2_NTSC_DAC_Adjustment;8757USHORT usDAC2_TV1_FORCE_Data;8758USHORT usDAC2_TV1_MUX_RegisterIndex;8759UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low8760UCHAR ucDAC2_CV_BG_Adjustment;8761UCHAR ucDAC2_CV_DAC_Adjustment;8762USHORT usDAC2_CV_FORCE_Data;8763USHORT usDAC2_CV_MUX_RegisterIndex;8764UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low8765UCHAR ucDAC2_PAL_BG_Adjustment;8766UCHAR ucDAC2_PAL_DAC_Adjustment;8767USHORT usDAC2_TV2_FORCE_Data;8768}COMPASSIONATE_DATA;87698770/****************************Supported Device Info Table Definitions**********************/8771// ucConnectInfo:8772// [7:4] - connector type8773// = 1 - VGA connector8774// = 2 - DVI-I8775// = 3 - DVI-D8776// = 4 - DVI-A8777// = 5 - SVIDEO8778// = 6 - COMPOSITE8779// = 7 - LVDS8780// = 8 - DIGITAL LINK8781// = 9 - SCART8782// = 0xA - HDMI_type A8783// = 0xB - HDMI_type B8784// = 0xE - Special case1 (DVI+DIN)8785// Others=TBD8786// [3:0] - DAC Associated8787// = 0 - no DAC8788// = 1 - DACA8789// = 2 - DACB8790// = 3 - External DAC8791// Others=TBD8792//87938794typedef struct _ATOM_CONNECTOR_INFO8795{8796#if ATOM_BIG_ENDIAN8797UCHAR bfConnectorType:4;8798UCHAR bfAssociatedDAC:4;8799#else8800UCHAR bfAssociatedDAC:4;8801UCHAR bfConnectorType:4;8802#endif8803}ATOM_CONNECTOR_INFO;88048805typedef union _ATOM_CONNECTOR_INFO_ACCESS8806{8807ATOM_CONNECTOR_INFO sbfAccess;8808UCHAR ucAccess;8809}ATOM_CONNECTOR_INFO_ACCESS;88108811typedef struct _ATOM_CONNECTOR_INFO_I2C8812{8813ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo;8814ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;8815}ATOM_CONNECTOR_INFO_I2C;881688178818typedef struct _ATOM_SUPPORTED_DEVICES_INFO8819{8820ATOM_COMMON_TABLE_HEADER sHeader;8821USHORT usDeviceSupport;8822ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO];8823}ATOM_SUPPORTED_DEVICES_INFO;88248825#define NO_INT_SRC_MAPPED 0xFF88268827typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP8828{8829UCHAR ucIntSrcBitmap;8830}ATOM_CONNECTOR_INC_SRC_BITMAP;88318832typedef struct _ATOM_SUPPORTED_DEVICES_INFO_28833{8834ATOM_COMMON_TABLE_HEADER sHeader;8835USHORT usDeviceSupport;8836ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];8837ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];8838}ATOM_SUPPORTED_DEVICES_INFO_2;88398840typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d18841{8842ATOM_COMMON_TABLE_HEADER sHeader;8843USHORT usDeviceSupport;8844ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE];8845ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE];8846}ATOM_SUPPORTED_DEVICES_INFO_2d1;88478848#define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d18849885088518852typedef struct _ATOM_MISC_CONTROL_INFO8853{8854USHORT usFrequency;8855UCHAR ucPLL_ChargePump; // PLL charge-pump gain control8856UCHAR ucPLL_DutyCycle; // PLL duty cycle control8857UCHAR ucPLL_VCO_Gain; // PLL VCO gain control8858UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control8859}ATOM_MISC_CONTROL_INFO;886088618862#define ATOM_MAX_MISC_INFO 488638864typedef struct _ATOM_TMDS_INFO8865{8866ATOM_COMMON_TABLE_HEADER sHeader;8867USHORT usMaxFrequency; // in 10Khz8868ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO];8869}ATOM_TMDS_INFO;887088718872typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE8873{8874UCHAR ucTVStandard; //Same as TV standards defined above,8875UCHAR ucPadding[1];8876}ATOM_ENCODER_ANALOG_ATTRIBUTE;88778878typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE8879{8880UCHAR ucAttribute; //Same as other digital encoder attributes defined above8881UCHAR ucPadding[1];8882}ATOM_ENCODER_DIGITAL_ATTRIBUTE;88838884typedef union _ATOM_ENCODER_ATTRIBUTE8885{8886ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib;8887ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib;8888}ATOM_ENCODER_ATTRIBUTE;888988908891typedef struct _DVO_ENCODER_CONTROL_PARAMETERS8892{8893USHORT usPixelClock;8894USHORT usEncoderID;8895UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only.8896UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT8897ATOM_ENCODER_ATTRIBUTE usDevAttr;8898}DVO_ENCODER_CONTROL_PARAMETERS;88998900typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION8901{8902DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder;8903WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion8904}DVO_ENCODER_CONTROL_PS_ALLOCATION;890589068907#define ATOM_XTMDS_ASIC_SI164_ID 18908#define ATOM_XTMDS_ASIC_SI178_ID 28909#define ATOM_XTMDS_ASIC_TFP513_ID 38910#define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x000000018911#define ATOM_XTMDS_SUPPORTED_DUALLINK 0x000000028912#define ATOM_XTMDS_MVPU_FPGA 0x00000004891389148915typedef struct _ATOM_XTMDS_INFO8916{8917ATOM_COMMON_TABLE_HEADER sHeader;8918USHORT usSingleLinkMaxFrequency;8919ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip8920UCHAR ucXtransimitterID;8921UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported8922UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters8923// due to design. This ID is used to alert driver that the sequence is not "standard"!8924UCHAR ucMasterAddress; // Address to control Master xTMDS Chip8925UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip8926}ATOM_XTMDS_INFO;89278928typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS8929{8930UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off8931UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX....8932UCHAR ucPadding[2];8933}DFP_DPMS_STATUS_CHANGE_PARAMETERS;89348935/****************************Legacy Power Play Table Definitions **********************/89368937//Definitions for ulPowerPlayMiscInfo8938#define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L8939#define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L8940#define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L89418942#define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L8943#define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L89448945#define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L89468947#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L8948#define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L8949#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program89508951#define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L8952#define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L8953#define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L8954#define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L8955#define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L8956#define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L8957#define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L89588959#define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L8960#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L8961#define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L8962#define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L8963#define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L89648965#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved8966#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 2089678968#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L8969#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L8970#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L8971#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic8972#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic8973#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode89748975#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks)8976#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 288977#define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L89788979#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L8980#define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L8981#define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L8982#define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L8983#define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L8984#define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L8985#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption.8986//If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback8987#define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L8988#define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L8989#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L89908991//ucTableFormatRevision=18992//ucTableContentRevision=18993typedef struct _ATOM_POWERMODE_INFO8994{8995ULONG ulMiscInfo; //The power level should be arranged in ascending order8996ULONG ulReserved1; // must set to 08997ULONG ulReserved2; // must set to 08998USHORT usEngineClock;8999USHORT usMemoryClock;9000UCHAR ucVoltageDropIndex; // index to GPIO table9001UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate9002UCHAR ucMinTemperature;9003UCHAR ucMaxTemperature;9004UCHAR ucNumPciELanes; // number of PCIE lanes9005}ATOM_POWERMODE_INFO;90069007//ucTableFormatRevision=29008//ucTableContentRevision=19009typedef struct _ATOM_POWERMODE_INFO_V29010{9011ULONG ulMiscInfo; //The power level should be arranged in ascending order9012ULONG ulMiscInfo2;9013ULONG ulEngineClock;9014ULONG ulMemoryClock;9015UCHAR ucVoltageDropIndex; // index to GPIO table9016UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate9017UCHAR ucMinTemperature;9018UCHAR ucMaxTemperature;9019UCHAR ucNumPciELanes; // number of PCIE lanes9020}ATOM_POWERMODE_INFO_V2;90219022//ucTableFormatRevision=29023//ucTableContentRevision=29024typedef struct _ATOM_POWERMODE_INFO_V39025{9026ULONG ulMiscInfo; //The power level should be arranged in ascending order9027ULONG ulMiscInfo2;9028ULONG ulEngineClock;9029ULONG ulMemoryClock;9030UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table9031UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate9032UCHAR ucMinTemperature;9033UCHAR ucMaxTemperature;9034UCHAR ucNumPciELanes; // number of PCIE lanes9035UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table9036}ATOM_POWERMODE_INFO_V3;903790389039#define ATOM_MAX_NUMBEROF_POWER_BLOCK 890409041#define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x019042#define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x0290439044#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x019045#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x029046#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x039047#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x049048#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x059049#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x069050#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog905190529053typedef struct _ATOM_POWERPLAY_INFO9054{9055ATOM_COMMON_TABLE_HEADER sHeader;9056UCHAR ucOverdriveThermalController;9057UCHAR ucOverdriveI2cLine;9058UCHAR ucOverdriveIntBitmap;9059UCHAR ucOverdriveControllerAddress;9060UCHAR ucSizeOfPowerModeEntry;9061UCHAR ucNumOfPowerModeEntries;9062ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];9063}ATOM_POWERPLAY_INFO;90649065typedef struct _ATOM_POWERPLAY_INFO_V29066{9067ATOM_COMMON_TABLE_HEADER sHeader;9068UCHAR ucOverdriveThermalController;9069UCHAR ucOverdriveI2cLine;9070UCHAR ucOverdriveIntBitmap;9071UCHAR ucOverdriveControllerAddress;9072UCHAR ucSizeOfPowerModeEntry;9073UCHAR ucNumOfPowerModeEntries;9074ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];9075}ATOM_POWERPLAY_INFO_V2;90769077typedef struct _ATOM_POWERPLAY_INFO_V39078{9079ATOM_COMMON_TABLE_HEADER sHeader;9080UCHAR ucOverdriveThermalController;9081UCHAR ucOverdriveI2cLine;9082UCHAR ucOverdriveIntBitmap;9083UCHAR ucOverdriveControllerAddress;9084UCHAR ucSizeOfPowerModeEntry;9085UCHAR ucNumOfPowerModeEntries;9086ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];9087}ATOM_POWERPLAY_INFO_V3;9088908990909091/**************************************************************************/909290939094// Following definitions are for compatiblity issue in different SW components.9095#define ATOM_MASTER_DATA_TABLE_REVISION 0x019096#define Object_Info Object_Header9097#define AdjustARB_SEQ MC_InitParameter9098#define VRAM_GPIO_DetectionInfo VoltageObjectInfo9099#define ASIC_VDDCI_Info ASIC_ProfilingInfo9100#define ASIC_MVDDQ_Info MemoryTrainingInfo9101#define SS_Info PPLL_SS_Info9102#define ASIC_MVDDC_Info ASIC_InternalSS_Info9103#define DispDevicePriorityInfo SaveRestoreInfo9104#define DispOutInfo TV_VideoMode910591069107#define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE9108#define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE91099110//New device naming, remove them when both DAL/VBIOS is ready9111#define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS9112#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS91139114#define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS9115#define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS91169117#define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS9118#define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION91199120#define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT9121#define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT91229123#define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX9124#define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX91259126#define ATOM_DEVICE_DFP2I_INDEX 0x000000099127#define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX)91289129#define ATOM_S0_DFP1I ATOM_S0_DFP19130#define ATOM_S0_DFP1X ATOM_S0_DFP291319132#define ATOM_S0_DFP2I 0x00200000L9133#define ATOM_S0_DFP2Ib2 0x2091349135#define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE9136#define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE91379138#define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L9139#define ATOM_S2_DFP2I_DPMS_STATEb3 0x0291409141#define ATOM_S3_DFP2I_ACTIVEb1 0x0291429143#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE9144#define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE91459146#define ATOM_S3_DFP2I_ACTIVE 0x00000200L91479148#define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE9149#define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE9150#define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L915191529153#define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x029154#define ATOM_S5_DOS_REQ_DFP2Ib1 0x0291559156#define ATOM_S5_DOS_REQ_DFP2I 0x02009157#define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP19158#define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP291599160#define ATOM_S6_ACC_REQ_DFP2Ib3 0x029161#define ATOM_S6_ACC_REQ_DFP2I 0x02000000L91629163#define TMDS1XEncoderControl DVOEncoderControl9164#define DFP1XOutputControl DVOOutputControl91659166#define ExternalDFPOutputControl DFP1XOutputControl9167#define EnableExternalTMDS_Encoder TMDS1XEncoderControl91689169#define DFP1IOutputControl TMDSAOutputControl9170#define DFP2IOutputControl LVTMAOutputControl91719172#define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS9173#define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION91749175#define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS9176#define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION91779178#define ucDac1Standard ucDacStandard9179#define ucDac2Standard ucDacStandard91809181#define TMDS1EncoderControl TMDSAEncoderControl9182#define TMDS2EncoderControl LVTMAEncoderControl91839184#define DFP1OutputControl TMDSAOutputControl9185#define DFP2OutputControl LVTMAOutputControl9186#define CRT1OutputControl DAC1OutputControl9187#define CRT2OutputControl DAC2OutputControl91889189//These two lines will be removed for sure in a few days, will follow up with Michael V.9190#define EnableLVDS_SS EnableSpreadSpectrumOnPPLL9191#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL91929193#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L9194#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE9195#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE9196#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE9197#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE91989199#define ATOM_S6_ACC_REQ_TV2 0x00400000L9200#define ATOM_DEVICE_TV2_INDEX 0x000000069201#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX)9202#define ATOM_S0_TV2 0x00100000L9203#define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE9204#define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE92059206/*********************************************************************************/92079208#pragma pack() // BIOS data must use byte alignment92099210#pragma pack(1)92119212typedef struct _ATOM_HOLE_INFO9213{9214USHORT usOffset; // offset of the hole ( from the start of the binary )9215USHORT usLength; // length of the hole ( in bytes )9216}ATOM_HOLE_INFO;92179218typedef struct _ATOM_SERVICE_DESCRIPTION9219{9220UCHAR ucRevision; // Holes set revision9221UCHAR ucAlgorithm; // Hash algorithm9222UCHAR ucSignatureType; // Signature type ( 0 - no signature, 1 - test, 2 - production )9223UCHAR ucReserved;9224USHORT usSigOffset; // Signature offset ( from the start of the binary )9225USHORT usSigLength; // Signature length9226}ATOM_SERVICE_DESCRIPTION;922792289229typedef struct _ATOM_SERVICE_INFO9230{9231ATOM_COMMON_TABLE_HEADER asHeader;9232ATOM_SERVICE_DESCRIPTION asDescr;9233UCHAR ucholesNo; // number of holes that follow9234ATOM_HOLE_INFO holes[1]; // array of hole descriptions9235}ATOM_SERVICE_INFO;9236923792389239#pragma pack() // BIOS data must use byte alignment92409241//9242// AMD ACPI Table9243//9244#pragma pack(1)92459246typedef struct {9247ULONG Signature;9248ULONG TableLength; //Length9249UCHAR Revision;9250UCHAR Checksum;9251UCHAR OemId[6];9252UCHAR OemTableId[8]; //UINT64 OemTableId;9253ULONG OemRevision;9254ULONG CreatorId;9255ULONG CreatorRevision;9256} AMD_ACPI_DESCRIPTION_HEADER;9257/*9258//EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h9259typedef struct {9260UINT32 Signature; //0x09261UINT32 Length; //0x49262UINT8 Revision; //0x89263UINT8 Checksum; //0x99264UINT8 OemId[6]; //0xA9265UINT64 OemTableId; //0x109266UINT32 OemRevision; //0x189267UINT32 CreatorId; //0x1C9268UINT32 CreatorRevision; //0x209269}EFI_ACPI_DESCRIPTION_HEADER;9270*/9271typedef struct {9272AMD_ACPI_DESCRIPTION_HEADER SHeader;9273UCHAR TableUUID[16]; //0x249274ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.9275ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.9276ULONG Reserved[4]; //0x3C9277}UEFI_ACPI_VFCT;92789279typedef struct {9280ULONG PCIBus; //0x4C9281ULONG PCIDevice; //0x509282ULONG PCIFunction; //0x549283USHORT VendorID; //0x589284USHORT DeviceID; //0x5A9285USHORT SSVID; //0x5C9286USHORT SSID; //0x5E9287ULONG Revision; //0x609288ULONG ImageLength; //0x649289}VFCT_IMAGE_HEADER;929092919292typedef struct {9293VFCT_IMAGE_HEADER VbiosHeader;9294UCHAR VbiosContent[];9295}GOP_VBIOS_CONTENT;92969297typedef struct {9298VFCT_IMAGE_HEADER Lib1Header;9299UCHAR Lib1Content[1];9300}GOP_LIB1_CONTENT;93019302#pragma pack()930393049305#endif /* _ATOMBIOS_H */93069307#include "pptable.h"9308930993109311