Path: blob/master/drivers/gpu/drm/amd/include/atomfirmwareid.h
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/****************************************************************************\1*2* File Name atomfirmwareid.h3*4* Description ATOM BIOS command/data table ID definition header file5*6* Copyright 2016 Advanced Micro Devices, Inc.7*8* Permission is hereby granted, free of charge, to any person obtaining a copy of this software9* and associated documentation files (the "Software"), to deal in the Software without restriction,10* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,11* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,12* subject to the following conditions:13*14* The above copyright notice and this permission notice shall be included in all copies or substantial15* portions of the Software.16*17* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR18* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,19* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL20* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR21* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,22* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR23* OTHER DEALINGS IN THE SOFTWARE.24*25\****************************************************************************/2627#ifndef _ATOMFIRMWAREID_H_28#define _ATOMFIRMWAREID_H_2930enum atom_master_data_table_id31{32VBIOS_DATA_TBL_ID__UTILITY_PIPELINE,33VBIOS_DATA_TBL_ID__MULTIMEDIA_INF,34VBIOS_DATA_TBL_ID__FIRMWARE_INF,35VBIOS_DATA_TBL_ID__LCD_INF,36VBIOS_DATA_TBL_ID__SMU_INF,37VBIOS_DATA_TBL_ID__VRAM_USAGE_BY_FIRMWARE,38VBIOS_DATA_TBL_ID__GPIO_PIN_LUT,39VBIOS_DATA_TBL_ID__GFX_INF,40VBIOS_DATA_TBL_ID__POWER_PLAY_INF,41VBIOS_DATA_TBL_ID__DISPLAY_OBJECT_INF,42VBIOS_DATA_TBL_ID__INDIRECT_IO_ACCESS,43VBIOS_DATA_TBL_ID__UMC_INF,44VBIOS_DATA_TBL_ID__DCE_INF,45VBIOS_DATA_TBL_ID__VRAM_INF,46VBIOS_DATA_TBL_ID__INTEGRATED_SYS_INF,47VBIOS_DATA_TBL_ID__ASIC_PROFILING_INF,48VBIOS_DATA_TBL_ID__VOLTAGE_OBJ_INF,4950VBIOS_DATA_TBL_ID__UNDEFINED,51};5253enum atom_master_command_table_id54{55VBIOS_CMD_TBL_ID__ASIC_INIT,56VBIOS_CMD_TBL_ID__DIGX_ENCODER_CONTROL,57VBIOS_CMD_TBL_ID__SET_ENGINE_CLOCK,58VBIOS_CMD_TBL_ID__SET_MEMORY_CLOCK,59VBIOS_CMD_TBL_ID__SET_PIXEL_CLOCK,60VBIOS_CMD_TBL_ID__ENABLE_DISP_POWER_GATING,61VBIOS_CMD_TBL_ID__BLANK_CRTC,62VBIOS_CMD_TBL_ID__ENABLE_CRTC,63VBIOS_CMD_TBL_ID__GET_SMU_CLOCK_INFO,64VBIOS_CMD_TBL_ID__SELECT_CRTC_SOURCE,65VBIOS_CMD_TBL_ID__SET_DCE_CLOCK,66VBIOS_CMD_TBL_ID__GET_MEMORY_CLOCK,67VBIOS_CMD_TBL_ID__GET_ENGINE_CLOCK,68VBIOS_CMD_TBL_ID__SET_CRTC_USING_DTD_TIMING,69VBIOS_CMD_TBL_ID__EXTENAL_ENCODER_CONTROL,70VBIOS_CMD_TBL_ID__PROCESS_I2C_CHANNEL_TRANSACTION,71VBIOS_CMD_TBL_ID__COMPUTE_GPU_CLOCK_PARAM,72VBIOS_CMD_TBL_ID__DYNAMIC_MEMORY_SETTINGS,73VBIOS_CMD_TBL_ID__MEMORY_TRAINING,74VBIOS_CMD_TBL_ID__SET_VOLTAGE,75VBIOS_CMD_TBL_ID__DIG1_TRANSMITTER_CONTROL,76VBIOS_CMD_TBL_ID__PROCESS_AUX_CHANNEL_TRANSACTION,77VBIOS_CMD_TBL_ID__GET_VOLTAGE_INF,7879VBIOS_CMD_TBL_ID__UNDEFINED,80};81828384#endif /* _ATOMFIRMWAREID_H_ */85/* ### EOF ### */868788