Path: blob/master/drivers/gpu/drm/amd/include/navi10_ip_offset.h
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/*1* Copyright (C) 2019 Advanced Micro Devices, Inc.2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice shall be included11* in all copies or substantial portions of the Software.12*13* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS14* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,15* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL16* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN17* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN18* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.19*/20#ifndef _navi10_ip_offset_HEADER21#define _navi10_ip_offset_HEADER2223#define MAX_INSTANCE 624#define MAX_SEGMENT 6252627struct IP_BASE_INSTANCE {28unsigned int segment[MAX_SEGMENT];29};3031struct IP_BASE {32struct IP_BASE_INSTANCE instance[MAX_INSTANCE];33} __maybe_unused;343536static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0, 0, 0, 0, 0 } },37{ { 0, 0, 0, 0, 0, 0 } },38{ { 0, 0, 0, 0, 0, 0 } },39{ { 0, 0, 0, 0, 0, 0 } },40{ { 0, 0, 0, 0, 0, 0 } },41{ { 0, 0, 0, 0, 0, 0 } } } };42static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017200, 0x00017E00, 0x0001B000 } },43{ { 0, 0, 0, 0, 0, 0 } },44{ { 0, 0, 0, 0, 0, 0 } },45{ { 0, 0, 0, 0, 0, 0 } },46{ { 0, 0, 0, 0, 0, 0 } },47{ { 0, 0, 0, 0, 0, 0 } } } };48static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0, 0, 0, 0, 0 } },49{ { 0, 0, 0, 0, 0, 0 } },50{ { 0, 0, 0, 0, 0, 0 } },51{ { 0, 0, 0, 0, 0, 0 } },52{ { 0, 0, 0, 0, 0, 0 } },53{ { 0, 0, 0, 0, 0, 0 } } } };54static const struct IP_BASE DCN_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0, 0 } },55{ { 0, 0, 0, 0, 0, 0 } },56{ { 0, 0, 0, 0, 0, 0 } },57{ { 0, 0, 0, 0, 0, 0 } },58{ { 0, 0, 0, 0, 0, 0 } },59{ { 0, 0, 0, 0, 0, 0 } } } };60static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0, 0, 0, 0, 0 } },61{ { 0, 0, 0, 0, 0, 0 } },62{ { 0, 0, 0, 0, 0, 0 } },63{ { 0, 0, 0, 0, 0, 0 } },64{ { 0, 0, 0, 0, 0, 0 } },65{ { 0, 0, 0, 0, 0, 0 } } } };66static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0, 0, 0, 0 } },67{ { 0, 0, 0, 0, 0, 0 } },68{ { 0, 0, 0, 0, 0, 0 } },69{ { 0, 0, 0, 0, 0, 0 } },70{ { 0, 0, 0, 0, 0, 0 } },71{ { 0, 0, 0, 0, 0, 0 } } } };72static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0, 0, 0, 0, 0 } },73{ { 0, 0, 0, 0, 0, 0 } },74{ { 0, 0, 0, 0, 0, 0 } },75{ { 0, 0, 0, 0, 0, 0 } },76{ { 0, 0, 0, 0, 0, 0 } },77{ { 0, 0, 0, 0, 0, 0 } } } };78static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0, 0 } },79{ { 0, 0, 0, 0, 0, 0 } },80{ { 0, 0, 0, 0, 0, 0 } },81{ { 0, 0, 0, 0, 0, 0 } },82{ { 0, 0, 0, 0, 0, 0 } },83{ { 0, 0, 0, 0, 0, 0 } } } };84static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },85{ { 0, 0, 0, 0, 0, 0 } },86{ { 0, 0, 0, 0, 0, 0 } },87{ { 0, 0, 0, 0, 0, 0 } },88{ { 0, 0, 0, 0, 0, 0 } },89{ { 0, 0, 0, 0, 0, 0 } } } };90static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },91{ { 0, 0, 0, 0, 0, 0 } },92{ { 0, 0, 0, 0, 0, 0 } },93{ { 0, 0, 0, 0, 0, 0 } },94{ { 0, 0, 0, 0, 0, 0 } },95{ { 0, 0, 0, 0, 0, 0 } } } };96static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } },97{ { 0, 0, 0, 0, 0, 0 } },98{ { 0, 0, 0, 0, 0, 0 } },99{ { 0, 0, 0, 0, 0, 0 } },100{ { 0, 0, 0, 0, 0, 0 } },101{ { 0, 0, 0, 0, 0, 0 } } } };102static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0, 0, 0, 0, 0 } },103{ { 0, 0, 0, 0, 0, 0 } },104{ { 0, 0, 0, 0, 0, 0 } },105{ { 0, 0, 0, 0, 0, 0 } },106{ { 0, 0, 0, 0, 0, 0 } },107{ { 0, 0, 0, 0, 0, 0 } } } };108static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0, 0 } },109{ { 0, 0, 0, 0, 0, 0 } },110{ { 0, 0, 0, 0, 0, 0 } },111{ { 0, 0, 0, 0, 0, 0 } },112{ { 0, 0, 0, 0, 0, 0 } },113{ { 0, 0, 0, 0, 0, 0 } } } };114static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } },115{ { 0, 0, 0, 0, 0, 0 } },116{ { 0, 0, 0, 0, 0, 0 } },117{ { 0, 0, 0, 0, 0, 0 } },118{ { 0, 0, 0, 0, 0, 0 } },119{ { 0, 0, 0, 0, 0, 0 } } } };120static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } },121{ { 0, 0, 0, 0, 0, 0 } },122{ { 0, 0, 0, 0, 0, 0 } },123{ { 0, 0, 0, 0, 0, 0 } },124{ { 0, 0, 0, 0, 0, 0 } },125{ { 0, 0, 0, 0, 0, 0 } } } };126static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0, 0, 0, 0, 0 } },127{ { 0, 0, 0, 0, 0, 0 } },128{ { 0, 0, 0, 0, 0, 0 } },129{ { 0, 0, 0, 0, 0, 0 } },130{ { 0, 0, 0, 0, 0, 0 } },131{ { 0, 0, 0, 0, 0, 0 } } } };132static const struct IP_BASE VCN_BASE ={ { { { 0x00007800, 0x00007E00, 0, 0, 0, 0 } },133{ { 0, 0, 0, 0, 0, 0 } },134{ { 0, 0, 0, 0, 0, 0 } },135{ { 0, 0, 0, 0, 0, 0 } },136{ { 0, 0, 0, 0, 0, 0 } },137{ { 0, 0, 0, 0, 0, 0 } } } };138139140#define ATHUB_BASE__INST0_SEG0 0x00000C00141#define ATHUB_BASE__INST0_SEG1 0142#define ATHUB_BASE__INST0_SEG2 0143#define ATHUB_BASE__INST0_SEG3 0144#define ATHUB_BASE__INST0_SEG4 0145#define ATHUB_BASE__INST0_SEG5 0146147#define ATHUB_BASE__INST1_SEG0 0148#define ATHUB_BASE__INST1_SEG1 0149#define ATHUB_BASE__INST1_SEG2 0150#define ATHUB_BASE__INST1_SEG3 0151#define ATHUB_BASE__INST1_SEG4 0152#define ATHUB_BASE__INST1_SEG5 0153154#define ATHUB_BASE__INST2_SEG0 0155#define ATHUB_BASE__INST2_SEG1 0156#define ATHUB_BASE__INST2_SEG2 0157#define ATHUB_BASE__INST2_SEG3 0158#define ATHUB_BASE__INST2_SEG4 0159#define ATHUB_BASE__INST2_SEG5 0160161#define ATHUB_BASE__INST3_SEG0 0162#define ATHUB_BASE__INST3_SEG1 0163#define ATHUB_BASE__INST3_SEG2 0164#define ATHUB_BASE__INST3_SEG3 0165#define ATHUB_BASE__INST3_SEG4 0166#define ATHUB_BASE__INST3_SEG5 0167168#define ATHUB_BASE__INST4_SEG0 0169#define ATHUB_BASE__INST4_SEG1 0170#define ATHUB_BASE__INST4_SEG2 0171#define ATHUB_BASE__INST4_SEG3 0172#define ATHUB_BASE__INST4_SEG4 0173#define ATHUB_BASE__INST4_SEG5 0174175#define ATHUB_BASE__INST5_SEG0 0176#define ATHUB_BASE__INST5_SEG1 0177#define ATHUB_BASE__INST5_SEG2 0178#define ATHUB_BASE__INST5_SEG3 0179#define ATHUB_BASE__INST5_SEG4 0180#define ATHUB_BASE__INST5_SEG5 0181182#define CLK_BASE__INST0_SEG0 0x00016C00183#define CLK_BASE__INST0_SEG1 0x00016E00184#define CLK_BASE__INST0_SEG2 0x00017000185#define CLK_BASE__INST0_SEG3 0x00017200186#define CLK_BASE__INST0_SEG4 0x00017E00187#define CLK_BASE__INST0_SEG5 0x0001B000188189#define CLK_BASE__INST1_SEG0 0190#define CLK_BASE__INST1_SEG1 0191#define CLK_BASE__INST1_SEG2 0192#define CLK_BASE__INST1_SEG3 0193#define CLK_BASE__INST1_SEG4 0194#define CLK_BASE__INST1_SEG5 0195196#define CLK_BASE__INST2_SEG0 0197#define CLK_BASE__INST2_SEG1 0198#define CLK_BASE__INST2_SEG2 0199#define CLK_BASE__INST2_SEG3 0200#define CLK_BASE__INST2_SEG4 0201#define CLK_BASE__INST2_SEG5 0202203#define CLK_BASE__INST3_SEG0 0204#define CLK_BASE__INST3_SEG1 0205#define CLK_BASE__INST3_SEG2 0206#define CLK_BASE__INST3_SEG3 0207#define CLK_BASE__INST3_SEG4 0208#define CLK_BASE__INST3_SEG5 0209210#define CLK_BASE__INST4_SEG0 0211#define CLK_BASE__INST4_SEG1 0212#define CLK_BASE__INST4_SEG2 0213#define CLK_BASE__INST4_SEG3 0214#define CLK_BASE__INST4_SEG4 0215#define CLK_BASE__INST4_SEG5 0216217#define CLK_BASE__INST5_SEG0 0218#define CLK_BASE__INST5_SEG1 0219#define CLK_BASE__INST5_SEG2 0220#define CLK_BASE__INST5_SEG3 0221#define CLK_BASE__INST5_SEG4 0222#define CLK_BASE__INST5_SEG5 0223224#define DF_BASE__INST0_SEG0 0x00007000225#define DF_BASE__INST0_SEG1 0226#define DF_BASE__INST0_SEG2 0227#define DF_BASE__INST0_SEG3 0228#define DF_BASE__INST0_SEG4 0229#define DF_BASE__INST0_SEG5 0230231#define DF_BASE__INST1_SEG0 0232#define DF_BASE__INST1_SEG1 0233#define DF_BASE__INST1_SEG2 0234#define DF_BASE__INST1_SEG3 0235#define DF_BASE__INST1_SEG4 0236#define DF_BASE__INST1_SEG5 0237238#define DF_BASE__INST2_SEG0 0239#define DF_BASE__INST2_SEG1 0240#define DF_BASE__INST2_SEG2 0241#define DF_BASE__INST2_SEG3 0242#define DF_BASE__INST2_SEG4 0243#define DF_BASE__INST2_SEG5 0244245#define DF_BASE__INST3_SEG0 0246#define DF_BASE__INST3_SEG1 0247#define DF_BASE__INST3_SEG2 0248#define DF_BASE__INST3_SEG3 0249#define DF_BASE__INST3_SEG4 0250#define DF_BASE__INST3_SEG5 0251252#define DF_BASE__INST4_SEG0 0253#define DF_BASE__INST4_SEG1 0254#define DF_BASE__INST4_SEG2 0255#define DF_BASE__INST4_SEG3 0256#define DF_BASE__INST4_SEG4 0257#define DF_BASE__INST4_SEG5 0258259#define DF_BASE__INST5_SEG0 0260#define DF_BASE__INST5_SEG1 0261#define DF_BASE__INST5_SEG2 0262#define DF_BASE__INST5_SEG3 0263#define DF_BASE__INST5_SEG4 0264#define DF_BASE__INST5_SEG5 0265266#define DCN_BASE__INST0_SEG0 0x00000012267#define DCN_BASE__INST0_SEG1 0x000000C0268#define DCN_BASE__INST0_SEG2 0x000034C0269#define DCN_BASE__INST0_SEG3 0x00009000270#define DCN_BASE__INST0_SEG4 0271#define DCN_BASE__INST0_SEG5 0272273#define DCN_BASE__INST1_SEG0 0274#define DCN_BASE__INST1_SEG1 0275#define DCN_BASE__INST1_SEG2 0276#define DCN_BASE__INST1_SEG3 0277#define DCN_BASE__INST1_SEG4 0278#define DCN_BASE__INST1_SEG5 0279280#define DCN_BASE__INST2_SEG0 0281#define DCN_BASE__INST2_SEG1 0282#define DCN_BASE__INST2_SEG2 0283#define DCN_BASE__INST2_SEG3 0284#define DCN_BASE__INST2_SEG4 0285#define DCN_BASE__INST2_SEG5 0286287#define DCN_BASE__INST3_SEG0 0288#define DCN_BASE__INST3_SEG1 0289#define DCN_BASE__INST3_SEG2 0290#define DCN_BASE__INST3_SEG3 0291#define DCN_BASE__INST3_SEG4 0292#define DCN_BASE__INST3_SEG5 0293294#define DCN_BASE__INST4_SEG0 0295#define DCN_BASE__INST4_SEG1 0296#define DCN_BASE__INST4_SEG2 0297#define DCN_BASE__INST4_SEG3 0298#define DCN_BASE__INST4_SEG4 0299#define DCN_BASE__INST4_SEG5 0300301#define DCN_BASE__INST5_SEG0 0302#define DCN_BASE__INST5_SEG1 0303#define DCN_BASE__INST5_SEG2 0304#define DCN_BASE__INST5_SEG3 0305#define DCN_BASE__INST5_SEG4 0306#define DCN_BASE__INST5_SEG5 0307308#define FUSE_BASE__INST0_SEG0 0x00017400309#define FUSE_BASE__INST0_SEG1 0310#define FUSE_BASE__INST0_SEG2 0311#define FUSE_BASE__INST0_SEG3 0312#define FUSE_BASE__INST0_SEG4 0313#define FUSE_BASE__INST0_SEG5 0314315#define FUSE_BASE__INST1_SEG0 0316#define FUSE_BASE__INST1_SEG1 0317#define FUSE_BASE__INST1_SEG2 0318#define FUSE_BASE__INST1_SEG3 0319#define FUSE_BASE__INST1_SEG4 0320#define FUSE_BASE__INST1_SEG5 0321322#define FUSE_BASE__INST2_SEG0 0323#define FUSE_BASE__INST2_SEG1 0324#define FUSE_BASE__INST2_SEG2 0325#define FUSE_BASE__INST2_SEG3 0326#define FUSE_BASE__INST2_SEG4 0327#define FUSE_BASE__INST2_SEG5 0328329#define FUSE_BASE__INST3_SEG0 0330#define FUSE_BASE__INST3_SEG1 0331#define FUSE_BASE__INST3_SEG2 0332#define FUSE_BASE__INST3_SEG3 0333#define FUSE_BASE__INST3_SEG4 0334#define FUSE_BASE__INST3_SEG5 0335336#define FUSE_BASE__INST4_SEG0 0337#define FUSE_BASE__INST4_SEG1 0338#define FUSE_BASE__INST4_SEG2 0339#define FUSE_BASE__INST4_SEG3 0340#define FUSE_BASE__INST4_SEG4 0341#define FUSE_BASE__INST4_SEG5 0342343#define FUSE_BASE__INST5_SEG0 0344#define FUSE_BASE__INST5_SEG1 0345#define FUSE_BASE__INST5_SEG2 0346#define FUSE_BASE__INST5_SEG3 0347#define FUSE_BASE__INST5_SEG4 0348#define FUSE_BASE__INST5_SEG5 0349350#define GC_BASE__INST0_SEG0 0x00001260351#define GC_BASE__INST0_SEG1 0x0000A000352#define GC_BASE__INST0_SEG2 0353#define GC_BASE__INST0_SEG3 0354#define GC_BASE__INST0_SEG4 0355#define GC_BASE__INST0_SEG5 0356357#define GC_BASE__INST1_SEG0 0358#define GC_BASE__INST1_SEG1 0359#define GC_BASE__INST1_SEG2 0360#define GC_BASE__INST1_SEG3 0361#define GC_BASE__INST1_SEG4 0362#define GC_BASE__INST1_SEG5 0363364#define GC_BASE__INST2_SEG0 0365#define GC_BASE__INST2_SEG1 0366#define GC_BASE__INST2_SEG2 0367#define GC_BASE__INST2_SEG3 0368#define GC_BASE__INST2_SEG4 0369#define GC_BASE__INST2_SEG5 0370371#define GC_BASE__INST3_SEG0 0372#define GC_BASE__INST3_SEG1 0373#define GC_BASE__INST3_SEG2 0374#define GC_BASE__INST3_SEG3 0375#define GC_BASE__INST3_SEG4 0376#define GC_BASE__INST3_SEG5 0377378#define GC_BASE__INST4_SEG0 0379#define GC_BASE__INST4_SEG1 0380#define GC_BASE__INST4_SEG2 0381#define GC_BASE__INST4_SEG3 0382#define GC_BASE__INST4_SEG4 0383#define GC_BASE__INST4_SEG5 0384385#define GC_BASE__INST5_SEG0 0386#define GC_BASE__INST5_SEG1 0387#define GC_BASE__INST5_SEG2 0388#define GC_BASE__INST5_SEG3 0389#define GC_BASE__INST5_SEG4 0390#define GC_BASE__INST5_SEG5 0391392#define HDP_BASE__INST0_SEG0 0x00000F20393#define HDP_BASE__INST0_SEG1 0394#define HDP_BASE__INST0_SEG2 0395#define HDP_BASE__INST0_SEG3 0396#define HDP_BASE__INST0_SEG4 0397#define HDP_BASE__INST0_SEG5 0398399#define HDP_BASE__INST1_SEG0 0400#define HDP_BASE__INST1_SEG1 0401#define HDP_BASE__INST1_SEG2 0402#define HDP_BASE__INST1_SEG3 0403#define HDP_BASE__INST1_SEG4 0404#define HDP_BASE__INST1_SEG5 0405406#define HDP_BASE__INST2_SEG0 0407#define HDP_BASE__INST2_SEG1 0408#define HDP_BASE__INST2_SEG2 0409#define HDP_BASE__INST2_SEG3 0410#define HDP_BASE__INST2_SEG4 0411#define HDP_BASE__INST2_SEG5 0412413#define HDP_BASE__INST3_SEG0 0414#define HDP_BASE__INST3_SEG1 0415#define HDP_BASE__INST3_SEG2 0416#define HDP_BASE__INST3_SEG3 0417#define HDP_BASE__INST3_SEG4 0418#define HDP_BASE__INST3_SEG5 0419420#define HDP_BASE__INST4_SEG0 0421#define HDP_BASE__INST4_SEG1 0422#define HDP_BASE__INST4_SEG2 0423#define HDP_BASE__INST4_SEG3 0424#define HDP_BASE__INST4_SEG4 0425#define HDP_BASE__INST4_SEG5 0426427#define HDP_BASE__INST5_SEG0 0428#define HDP_BASE__INST5_SEG1 0429#define HDP_BASE__INST5_SEG2 0430#define HDP_BASE__INST5_SEG3 0431#define HDP_BASE__INST5_SEG4 0432#define HDP_BASE__INST5_SEG5 0433434#define MMHUB_BASE__INST0_SEG0 0x0001A000435#define MMHUB_BASE__INST0_SEG1 0436#define MMHUB_BASE__INST0_SEG2 0437#define MMHUB_BASE__INST0_SEG3 0438#define MMHUB_BASE__INST0_SEG4 0439#define MMHUB_BASE__INST0_SEG5 0440441#define MMHUB_BASE__INST1_SEG0 0442#define MMHUB_BASE__INST1_SEG1 0443#define MMHUB_BASE__INST1_SEG2 0444#define MMHUB_BASE__INST1_SEG3 0445#define MMHUB_BASE__INST1_SEG4 0446#define MMHUB_BASE__INST1_SEG5 0447448#define MMHUB_BASE__INST2_SEG0 0449#define MMHUB_BASE__INST2_SEG1 0450#define MMHUB_BASE__INST2_SEG2 0451#define MMHUB_BASE__INST2_SEG3 0452#define MMHUB_BASE__INST2_SEG4 0453#define MMHUB_BASE__INST2_SEG5 0454455#define MMHUB_BASE__INST3_SEG0 0456#define MMHUB_BASE__INST3_SEG1 0457#define MMHUB_BASE__INST3_SEG2 0458#define MMHUB_BASE__INST3_SEG3 0459#define MMHUB_BASE__INST3_SEG4 0460#define MMHUB_BASE__INST3_SEG5 0461462#define MMHUB_BASE__INST4_SEG0 0463#define MMHUB_BASE__INST4_SEG1 0464#define MMHUB_BASE__INST4_SEG2 0465#define MMHUB_BASE__INST4_SEG3 0466#define MMHUB_BASE__INST4_SEG4 0467#define MMHUB_BASE__INST4_SEG5 0468469#define MMHUB_BASE__INST5_SEG0 0470#define MMHUB_BASE__INST5_SEG1 0471#define MMHUB_BASE__INST5_SEG2 0472#define MMHUB_BASE__INST5_SEG3 0473#define MMHUB_BASE__INST5_SEG4 0474#define MMHUB_BASE__INST5_SEG5 0475476#define MP0_BASE__INST0_SEG0 0x00016000477#define MP0_BASE__INST0_SEG1 0478#define MP0_BASE__INST0_SEG2 0479#define MP0_BASE__INST0_SEG3 0480#define MP0_BASE__INST0_SEG4 0481#define MP0_BASE__INST0_SEG5 0482483#define MP0_BASE__INST1_SEG0 0484#define MP0_BASE__INST1_SEG1 0485#define MP0_BASE__INST1_SEG2 0486#define MP0_BASE__INST1_SEG3 0487#define MP0_BASE__INST1_SEG4 0488#define MP0_BASE__INST1_SEG5 0489490#define MP0_BASE__INST2_SEG0 0491#define MP0_BASE__INST2_SEG1 0492#define MP0_BASE__INST2_SEG2 0493#define MP0_BASE__INST2_SEG3 0494#define MP0_BASE__INST2_SEG4 0495#define MP0_BASE__INST2_SEG5 0496497#define MP0_BASE__INST3_SEG0 0498#define MP0_BASE__INST3_SEG1 0499#define MP0_BASE__INST3_SEG2 0500#define MP0_BASE__INST3_SEG3 0501#define MP0_BASE__INST3_SEG4 0502#define MP0_BASE__INST3_SEG5 0503504#define MP0_BASE__INST4_SEG0 0505#define MP0_BASE__INST4_SEG1 0506#define MP0_BASE__INST4_SEG2 0507#define MP0_BASE__INST4_SEG3 0508#define MP0_BASE__INST4_SEG4 0509#define MP0_BASE__INST4_SEG5 0510511#define MP0_BASE__INST5_SEG0 0512#define MP0_BASE__INST5_SEG1 0513#define MP0_BASE__INST5_SEG2 0514#define MP0_BASE__INST5_SEG3 0515#define MP0_BASE__INST5_SEG4 0516#define MP0_BASE__INST5_SEG5 0517518#define MP1_BASE__INST0_SEG0 0x00016000519#define MP1_BASE__INST0_SEG1 0520#define MP1_BASE__INST0_SEG2 0521#define MP1_BASE__INST0_SEG3 0522#define MP1_BASE__INST0_SEG4 0523#define MP1_BASE__INST0_SEG5 0524525#define MP1_BASE__INST1_SEG0 0526#define MP1_BASE__INST1_SEG1 0527#define MP1_BASE__INST1_SEG2 0528#define MP1_BASE__INST1_SEG3 0529#define MP1_BASE__INST1_SEG4 0530#define MP1_BASE__INST1_SEG5 0531532#define MP1_BASE__INST2_SEG0 0533#define MP1_BASE__INST2_SEG1 0534#define MP1_BASE__INST2_SEG2 0535#define MP1_BASE__INST2_SEG3 0536#define MP1_BASE__INST2_SEG4 0537#define MP1_BASE__INST2_SEG5 0538539#define MP1_BASE__INST3_SEG0 0540#define MP1_BASE__INST3_SEG1 0541#define MP1_BASE__INST3_SEG2 0542#define MP1_BASE__INST3_SEG3 0543#define MP1_BASE__INST3_SEG4 0544#define MP1_BASE__INST3_SEG5 0545546#define MP1_BASE__INST4_SEG0 0547#define MP1_BASE__INST4_SEG1 0548#define MP1_BASE__INST4_SEG2 0549#define MP1_BASE__INST4_SEG3 0550#define MP1_BASE__INST4_SEG4 0551#define MP1_BASE__INST4_SEG5 0552553#define MP1_BASE__INST5_SEG0 0554#define MP1_BASE__INST5_SEG1 0555#define MP1_BASE__INST5_SEG2 0556#define MP1_BASE__INST5_SEG3 0557#define MP1_BASE__INST5_SEG4 0558#define MP1_BASE__INST5_SEG5 0559560#define NBIO_BASE__INST0_SEG0 0x00000000561#define NBIO_BASE__INST0_SEG1 0x00000014562#define NBIO_BASE__INST0_SEG2 0x00000D20563#define NBIO_BASE__INST0_SEG3 0x00010400564#define NBIO_BASE__INST0_SEG4 0565#define NBIO_BASE__INST0_SEG5 0566567#define NBIO_BASE__INST1_SEG0 0568#define NBIO_BASE__INST1_SEG1 0569#define NBIO_BASE__INST1_SEG2 0570#define NBIO_BASE__INST1_SEG3 0571#define NBIO_BASE__INST1_SEG4 0572#define NBIO_BASE__INST1_SEG5 0573574#define NBIO_BASE__INST2_SEG0 0575#define NBIO_BASE__INST2_SEG1 0576#define NBIO_BASE__INST2_SEG2 0577#define NBIO_BASE__INST2_SEG3 0578#define NBIO_BASE__INST2_SEG4 0579#define NBIO_BASE__INST2_SEG5 0580581#define NBIO_BASE__INST3_SEG0 0582#define NBIO_BASE__INST3_SEG1 0583#define NBIO_BASE__INST3_SEG2 0584#define NBIO_BASE__INST3_SEG3 0585#define NBIO_BASE__INST3_SEG4 0586#define NBIO_BASE__INST3_SEG5 0587588#define NBIO_BASE__INST4_SEG0 0589#define NBIO_BASE__INST4_SEG1 0590#define NBIO_BASE__INST4_SEG2 0591#define NBIO_BASE__INST4_SEG3 0592#define NBIO_BASE__INST4_SEG4 0593#define NBIO_BASE__INST4_SEG5 0594595#define NBIO_BASE__INST5_SEG0 0596#define NBIO_BASE__INST5_SEG1 0597#define NBIO_BASE__INST5_SEG2 0598#define NBIO_BASE__INST5_SEG3 0599#define NBIO_BASE__INST5_SEG4 0600#define NBIO_BASE__INST5_SEG5 0601602#define OSSSYS_BASE__INST0_SEG0 0x000010A0603#define OSSSYS_BASE__INST0_SEG1 0604#define OSSSYS_BASE__INST0_SEG2 0605#define OSSSYS_BASE__INST0_SEG3 0606#define OSSSYS_BASE__INST0_SEG4 0607#define OSSSYS_BASE__INST0_SEG5 0608609#define OSSSYS_BASE__INST1_SEG0 0610#define OSSSYS_BASE__INST1_SEG1 0611#define OSSSYS_BASE__INST1_SEG2 0612#define OSSSYS_BASE__INST1_SEG3 0613#define OSSSYS_BASE__INST1_SEG4 0614#define OSSSYS_BASE__INST1_SEG5 0615616#define OSSSYS_BASE__INST2_SEG0 0617#define OSSSYS_BASE__INST2_SEG1 0618#define OSSSYS_BASE__INST2_SEG2 0619#define OSSSYS_BASE__INST2_SEG3 0620#define OSSSYS_BASE__INST2_SEG4 0621#define OSSSYS_BASE__INST2_SEG5 0622623#define OSSSYS_BASE__INST3_SEG0 0624#define OSSSYS_BASE__INST3_SEG1 0625#define OSSSYS_BASE__INST3_SEG2 0626#define OSSSYS_BASE__INST3_SEG3 0627#define OSSSYS_BASE__INST3_SEG4 0628#define OSSSYS_BASE__INST3_SEG5 0629630#define OSSSYS_BASE__INST4_SEG0 0631#define OSSSYS_BASE__INST4_SEG1 0632#define OSSSYS_BASE__INST4_SEG2 0633#define OSSSYS_BASE__INST4_SEG3 0634#define OSSSYS_BASE__INST4_SEG4 0635#define OSSSYS_BASE__INST4_SEG5 0636637#define OSSSYS_BASE__INST5_SEG0 0638#define OSSSYS_BASE__INST5_SEG1 0639#define OSSSYS_BASE__INST5_SEG2 0640#define OSSSYS_BASE__INST5_SEG3 0641#define OSSSYS_BASE__INST5_SEG4 0642#define OSSSYS_BASE__INST5_SEG5 0643644#define RSMU_BASE__INST0_SEG0 0x00012000645#define RSMU_BASE__INST0_SEG1 0646#define RSMU_BASE__INST0_SEG2 0647#define RSMU_BASE__INST0_SEG3 0648#define RSMU_BASE__INST0_SEG4 0649#define RSMU_BASE__INST0_SEG5 0650651#define RSMU_BASE__INST1_SEG0 0652#define RSMU_BASE__INST1_SEG1 0653#define RSMU_BASE__INST1_SEG2 0654#define RSMU_BASE__INST1_SEG3 0655#define RSMU_BASE__INST1_SEG4 0656#define RSMU_BASE__INST1_SEG5 0657658#define RSMU_BASE__INST2_SEG0 0659#define RSMU_BASE__INST2_SEG1 0660#define RSMU_BASE__INST2_SEG2 0661#define RSMU_BASE__INST2_SEG3 0662#define RSMU_BASE__INST2_SEG4 0663#define RSMU_BASE__INST2_SEG5 0664665#define RSMU_BASE__INST3_SEG0 0666#define RSMU_BASE__INST3_SEG1 0667#define RSMU_BASE__INST3_SEG2 0668#define RSMU_BASE__INST3_SEG3 0669#define RSMU_BASE__INST3_SEG4 0670#define RSMU_BASE__INST3_SEG5 0671672#define RSMU_BASE__INST4_SEG0 0673#define RSMU_BASE__INST4_SEG1 0674#define RSMU_BASE__INST4_SEG2 0675#define RSMU_BASE__INST4_SEG3 0676#define RSMU_BASE__INST4_SEG4 0677#define RSMU_BASE__INST4_SEG5 0678679#define RSMU_BASE__INST5_SEG0 0680#define RSMU_BASE__INST5_SEG1 0681#define RSMU_BASE__INST5_SEG2 0682#define RSMU_BASE__INST5_SEG3 0683#define RSMU_BASE__INST5_SEG4 0684#define RSMU_BASE__INST5_SEG5 0685686#define SMUIO_BASE__INST0_SEG0 0x00016800687#define SMUIO_BASE__INST0_SEG1 0x00016A00688#define SMUIO_BASE__INST0_SEG2 0689#define SMUIO_BASE__INST0_SEG3 0690#define SMUIO_BASE__INST0_SEG4 0691#define SMUIO_BASE__INST0_SEG5 0692693#define SMUIO_BASE__INST1_SEG0 0694#define SMUIO_BASE__INST1_SEG1 0695#define SMUIO_BASE__INST1_SEG2 0696#define SMUIO_BASE__INST1_SEG3 0697#define SMUIO_BASE__INST1_SEG4 0698#define SMUIO_BASE__INST1_SEG5 0699700#define SMUIO_BASE__INST2_SEG0 0701#define SMUIO_BASE__INST2_SEG1 0702#define SMUIO_BASE__INST2_SEG2 0703#define SMUIO_BASE__INST2_SEG3 0704#define SMUIO_BASE__INST2_SEG4 0705#define SMUIO_BASE__INST2_SEG5 0706707#define SMUIO_BASE__INST3_SEG0 0708#define SMUIO_BASE__INST3_SEG1 0709#define SMUIO_BASE__INST3_SEG2 0710#define SMUIO_BASE__INST3_SEG3 0711#define SMUIO_BASE__INST3_SEG4 0712#define SMUIO_BASE__INST3_SEG5 0713714#define SMUIO_BASE__INST4_SEG0 0715#define SMUIO_BASE__INST4_SEG1 0716#define SMUIO_BASE__INST4_SEG2 0717#define SMUIO_BASE__INST4_SEG3 0718#define SMUIO_BASE__INST4_SEG4 0719#define SMUIO_BASE__INST4_SEG5 0720721#define SMUIO_BASE__INST5_SEG0 0722#define SMUIO_BASE__INST5_SEG1 0723#define SMUIO_BASE__INST5_SEG2 0724#define SMUIO_BASE__INST5_SEG3 0725#define SMUIO_BASE__INST5_SEG4 0726#define SMUIO_BASE__INST5_SEG5 0727728#define THM_BASE__INST0_SEG0 0x00016600729#define THM_BASE__INST0_SEG1 0730#define THM_BASE__INST0_SEG2 0731#define THM_BASE__INST0_SEG3 0732#define THM_BASE__INST0_SEG4 0733#define THM_BASE__INST0_SEG5 0734735#define THM_BASE__INST1_SEG0 0736#define THM_BASE__INST1_SEG1 0737#define THM_BASE__INST1_SEG2 0738#define THM_BASE__INST1_SEG3 0739#define THM_BASE__INST1_SEG4 0740#define THM_BASE__INST1_SEG5 0741742#define THM_BASE__INST2_SEG0 0743#define THM_BASE__INST2_SEG1 0744#define THM_BASE__INST2_SEG2 0745#define THM_BASE__INST2_SEG3 0746#define THM_BASE__INST2_SEG4 0747#define THM_BASE__INST2_SEG5 0748749#define THM_BASE__INST3_SEG0 0750#define THM_BASE__INST3_SEG1 0751#define THM_BASE__INST3_SEG2 0752#define THM_BASE__INST3_SEG3 0753#define THM_BASE__INST3_SEG4 0754#define THM_BASE__INST3_SEG5 0755756#define THM_BASE__INST4_SEG0 0757#define THM_BASE__INST4_SEG1 0758#define THM_BASE__INST4_SEG2 0759#define THM_BASE__INST4_SEG3 0760#define THM_BASE__INST4_SEG4 0761#define THM_BASE__INST4_SEG5 0762763#define THM_BASE__INST5_SEG0 0764#define THM_BASE__INST5_SEG1 0765#define THM_BASE__INST5_SEG2 0766#define THM_BASE__INST5_SEG3 0767#define THM_BASE__INST5_SEG4 0768#define THM_BASE__INST5_SEG5 0769770#define UMC_BASE__INST0_SEG0 0x00014000771#define UMC_BASE__INST0_SEG1 0772#define UMC_BASE__INST0_SEG2 0773#define UMC_BASE__INST0_SEG3 0774#define UMC_BASE__INST0_SEG4 0775#define UMC_BASE__INST0_SEG5 0776777#define UMC_BASE__INST1_SEG0 0778#define UMC_BASE__INST1_SEG1 0779#define UMC_BASE__INST1_SEG2 0780#define UMC_BASE__INST1_SEG3 0781#define UMC_BASE__INST1_SEG4 0782#define UMC_BASE__INST1_SEG5 0783784#define UMC_BASE__INST2_SEG0 0785#define UMC_BASE__INST2_SEG1 0786#define UMC_BASE__INST2_SEG2 0787#define UMC_BASE__INST2_SEG3 0788#define UMC_BASE__INST2_SEG4 0789#define UMC_BASE__INST2_SEG5 0790791#define UMC_BASE__INST3_SEG0 0792#define UMC_BASE__INST3_SEG1 0793#define UMC_BASE__INST3_SEG2 0794#define UMC_BASE__INST3_SEG3 0795#define UMC_BASE__INST3_SEG4 0796#define UMC_BASE__INST3_SEG5 0797798#define UMC_BASE__INST4_SEG0 0799#define UMC_BASE__INST4_SEG1 0800#define UMC_BASE__INST4_SEG2 0801#define UMC_BASE__INST4_SEG3 0802#define UMC_BASE__INST4_SEG4 0803#define UMC_BASE__INST4_SEG5 0804805#define UMC_BASE__INST5_SEG0 0806#define UMC_BASE__INST5_SEG1 0807#define UMC_BASE__INST5_SEG2 0808#define UMC_BASE__INST5_SEG3 0809#define UMC_BASE__INST5_SEG4 0810#define UMC_BASE__INST5_SEG5 0811812#define VCN_BASE__INST0_SEG0 0x00007800813#define VCN_BASE__INST0_SEG1 0x00007E00814#define VCN_BASE__INST0_SEG2 0815#define VCN_BASE__INST0_SEG3 0816#define VCN_BASE__INST0_SEG4 0817#define VCN_BASE__INST0_SEG5 0818819#define VCN_BASE__INST1_SEG0 0820#define VCN_BASE__INST1_SEG1 0821#define VCN_BASE__INST1_SEG2 0822#define VCN_BASE__INST1_SEG3 0823#define VCN_BASE__INST1_SEG4 0824#define VCN_BASE__INST1_SEG5 0825826#define VCN_BASE__INST2_SEG0 0827#define VCN_BASE__INST2_SEG1 0828#define VCN_BASE__INST2_SEG2 0829#define VCN_BASE__INST2_SEG3 0830#define VCN_BASE__INST2_SEG4 0831#define VCN_BASE__INST2_SEG5 0832833#define VCN_BASE__INST3_SEG0 0834#define VCN_BASE__INST3_SEG1 0835#define VCN_BASE__INST3_SEG2 0836#define VCN_BASE__INST3_SEG3 0837#define VCN_BASE__INST3_SEG4 0838#define VCN_BASE__INST3_SEG5 0839840#define VCN_BASE__INST4_SEG0 0841#define VCN_BASE__INST4_SEG1 0842#define VCN_BASE__INST4_SEG2 0843#define VCN_BASE__INST4_SEG3 0844#define VCN_BASE__INST4_SEG4 0845#define VCN_BASE__INST4_SEG5 0846847#define VCN_BASE__INST5_SEG0 0848#define VCN_BASE__INST5_SEG1 0849#define VCN_BASE__INST5_SEG2 0850#define VCN_BASE__INST5_SEG3 0851#define VCN_BASE__INST5_SEG4 0852#define VCN_BASE__INST5_SEG5 0853854#endif855856857