Path: blob/master/drivers/gpu/drm/amd/include/navi14_ip_offset.h
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/*1* Copyright (C) 2018 Advanced Micro Devices, Inc.2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice shall be included11* in all copies or substantial portions of the Software.12*13* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS14* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,15* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL16* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN17* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN18* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.19*/20#ifndef _navi14_ip_offset_HEADER21#define _navi14_ip_offset_HEADER2223#define MAX_INSTANCE 724#define MAX_SEGMENT 5252627struct IP_BASE_INSTANCE {28unsigned int segment[MAX_SEGMENT];29};3031struct IP_BASE {32struct IP_BASE_INSTANCE instance[MAX_INSTANCE];33} __maybe_unused;343536static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0x02408C00, 0, 0, 0 } },37{ { 0, 0, 0, 0, 0 } },38{ { 0, 0, 0, 0, 0 } },39{ { 0, 0, 0, 0, 0 } },40{ { 0, 0, 0, 0, 0 } },41{ { 0, 0, 0, 0, 0 } },42{ { 0, 0, 0, 0, 0 } } } };43static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } },44{ { 0x00016E00, 0x02401C00, 0, 0, 0 } },45{ { 0x00017000, 0x02402000, 0, 0, 0 } },46{ { 0x00017200, 0x02402400, 0, 0, 0 } },47{ { 0x0001B000, 0x0242D800, 0, 0, 0 } },48{ { 0x00017E00, 0x0240BC00, 0, 0, 0 } },49{ { 0, 0, 0, 0, 0 } } } };50static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } },51{ { 0, 0, 0, 0, 0 } },52{ { 0, 0, 0, 0, 0 } },53{ { 0, 0, 0, 0, 0 } },54{ { 0, 0, 0, 0, 0 } },55{ { 0, 0, 0, 0, 0 } },56{ { 0, 0, 0, 0, 0 } } } };57static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } },58{ { 0, 0, 0, 0, 0 } },59{ { 0, 0, 0, 0, 0 } },60{ { 0, 0, 0, 0, 0 } },61{ { 0, 0, 0, 0, 0 } },62{ { 0, 0, 0, 0, 0 } },63{ { 0, 0, 0, 0, 0 } } } };64static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },65{ { 0, 0, 0, 0, 0 } },66{ { 0, 0, 0, 0, 0 } },67{ { 0, 0, 0, 0, 0 } },68{ { 0, 0, 0, 0, 0 } },69{ { 0, 0, 0, 0, 0 } },70{ { 0, 0, 0, 0, 0 } } } };71static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },72{ { 0, 0, 0, 0, 0 } },73{ { 0, 0, 0, 0, 0 } },74{ { 0, 0, 0, 0, 0 } },75{ { 0, 0, 0, 0, 0 } },76{ { 0, 0, 0, 0, 0 } },77{ { 0, 0, 0, 0, 0 } } } };78static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } },79{ { 0, 0, 0, 0, 0 } },80{ { 0, 0, 0, 0, 0 } },81{ { 0, 0, 0, 0, 0 } },82{ { 0, 0, 0, 0, 0 } },83{ { 0, 0, 0, 0, 0 } },84{ { 0, 0, 0, 0, 0 } } } };85static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },86{ { 0, 0, 0, 0, 0 } },87{ { 0, 0, 0, 0, 0 } },88{ { 0, 0, 0, 0, 0 } },89{ { 0, 0, 0, 0, 0 } },90{ { 0, 0, 0, 0, 0 } },91{ { 0, 0, 0, 0, 0 } } } };92static const struct IP_BASE HDA_BASE ={ { { { 0x004C0000, 0x02404800, 0, 0, 0 } },93{ { 0, 0, 0, 0, 0 } },94{ { 0, 0, 0, 0, 0 } },95{ { 0, 0, 0, 0, 0 } },96{ { 0, 0, 0, 0, 0 } },97{ { 0, 0, 0, 0, 0 } },98{ { 0, 0, 0, 0, 0 } } } };99static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },100{ { 0, 0, 0, 0, 0 } },101{ { 0, 0, 0, 0, 0 } },102{ { 0, 0, 0, 0, 0 } },103{ { 0, 0, 0, 0, 0 } },104{ { 0, 0, 0, 0, 0 } },105{ { 0, 0, 0, 0, 0 } } } };106static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } },107{ { 0, 0, 0, 0, 0 } },108{ { 0, 0, 0, 0, 0 } },109{ { 0, 0, 0, 0, 0 } },110{ { 0, 0, 0, 0, 0 } },111{ { 0, 0, 0, 0, 0 } },112{ { 0, 0, 0, 0, 0 } } } };113static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } },114{ { 0, 0, 0, 0, 0 } },115{ { 0, 0, 0, 0, 0 } },116{ { 0, 0, 0, 0, 0 } },117{ { 0, 0, 0, 0, 0 } },118{ { 0, 0, 0, 0, 0 } },119{ { 0, 0, 0, 0, 0 } } } };120static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } },121{ { 0, 0, 0, 0, 0 } },122{ { 0, 0, 0, 0, 0 } },123{ { 0, 0, 0, 0, 0 } },124{ { 0, 0, 0, 0, 0 } },125{ { 0, 0, 0, 0, 0 } },126{ { 0, 0, 0, 0, 0 } } } };127static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },128{ { 0, 0, 0, 0, 0 } },129{ { 0, 0, 0, 0, 0 } },130{ { 0, 0, 0, 0, 0 } },131{ { 0, 0, 0, 0, 0 } },132{ { 0, 0, 0, 0, 0 } },133{ { 0, 0, 0, 0, 0 } } } };134static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } },135{ { 0, 0, 0, 0, 0 } },136{ { 0, 0, 0, 0, 0 } },137{ { 0, 0, 0, 0, 0 } },138{ { 0, 0, 0, 0, 0 } },139{ { 0, 0, 0, 0, 0 } },140{ { 0, 0, 0, 0, 0 } } } };141static const struct IP_BASE PCIE0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },142{ { 0, 0, 0, 0, 0 } },143{ { 0, 0, 0, 0, 0 } },144{ { 0, 0, 0, 0, 0 } },145{ { 0, 0, 0, 0, 0 } },146{ { 0, 0, 0, 0, 0 } },147{ { 0, 0, 0, 0, 0 } } } };148static const struct IP_BASE SDMA_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },149{ { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },150{ { 0, 0, 0, 0, 0 } },151{ { 0, 0, 0, 0, 0 } },152{ { 0, 0, 0, 0, 0 } },153{ { 0, 0, 0, 0, 0 } },154{ { 0, 0, 0, 0, 0 } } } };155static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } },156{ { 0, 0, 0, 0, 0 } },157{ { 0, 0, 0, 0, 0 } },158{ { 0, 0, 0, 0, 0 } },159{ { 0, 0, 0, 0, 0 } },160{ { 0, 0, 0, 0, 0 } },161{ { 0, 0, 0, 0, 0 } } } };162static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } },163{ { 0, 0, 0, 0, 0 } },164{ { 0, 0, 0, 0, 0 } },165{ { 0, 0, 0, 0, 0 } },166{ { 0, 0, 0, 0, 0 } },167{ { 0, 0, 0, 0, 0 } },168{ { 0, 0, 0, 0, 0 } } } };169static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } },170{ { 0x00054000, 0x02425C00, 0, 0, 0 } },171{ { 0x00094000, 0x02426000, 0, 0, 0 } },172{ { 0x000D4000, 0x02426400, 0, 0, 0 } },173{ { 0, 0, 0, 0, 0 } },174{ { 0, 0, 0, 0, 0 } },175{ { 0, 0, 0, 0, 0 } } } };176static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } },177{ { 0, 0, 0, 0, 0 } },178{ { 0, 0, 0, 0, 0 } },179{ { 0, 0, 0, 0, 0 } },180{ { 0, 0, 0, 0, 0 } },181{ { 0, 0, 0, 0, 0 } },182{ { 0, 0, 0, 0, 0 } } } };183static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },184{ { 0, 0, 0, 0, 0 } },185{ { 0, 0, 0, 0, 0 } },186{ { 0, 0, 0, 0, 0 } },187{ { 0, 0, 0, 0, 0 } },188{ { 0, 0, 0, 0, 0 } },189{ { 0, 0, 0, 0, 0 } } } };190191192#define ATHUB_BASE__INST0_SEG0 0x00000C00193#define ATHUB_BASE__INST0_SEG1 0x02408C00194#define ATHUB_BASE__INST0_SEG2 0195#define ATHUB_BASE__INST0_SEG3 0196#define ATHUB_BASE__INST0_SEG4 0197198#define ATHUB_BASE__INST1_SEG0 0199#define ATHUB_BASE__INST1_SEG1 0200#define ATHUB_BASE__INST1_SEG2 0201#define ATHUB_BASE__INST1_SEG3 0202#define ATHUB_BASE__INST1_SEG4 0203204#define ATHUB_BASE__INST2_SEG0 0205#define ATHUB_BASE__INST2_SEG1 0206#define ATHUB_BASE__INST2_SEG2 0207#define ATHUB_BASE__INST2_SEG3 0208#define ATHUB_BASE__INST2_SEG4 0209210#define ATHUB_BASE__INST3_SEG0 0211#define ATHUB_BASE__INST3_SEG1 0212#define ATHUB_BASE__INST3_SEG2 0213#define ATHUB_BASE__INST3_SEG3 0214#define ATHUB_BASE__INST3_SEG4 0215216#define ATHUB_BASE__INST4_SEG0 0217#define ATHUB_BASE__INST4_SEG1 0218#define ATHUB_BASE__INST4_SEG2 0219#define ATHUB_BASE__INST4_SEG3 0220#define ATHUB_BASE__INST4_SEG4 0221222#define ATHUB_BASE__INST5_SEG0 0223#define ATHUB_BASE__INST5_SEG1 0224#define ATHUB_BASE__INST5_SEG2 0225#define ATHUB_BASE__INST5_SEG3 0226#define ATHUB_BASE__INST5_SEG4 0227228#define ATHUB_BASE__INST6_SEG0 0229#define ATHUB_BASE__INST6_SEG1 0230#define ATHUB_BASE__INST6_SEG2 0231#define ATHUB_BASE__INST6_SEG3 0232#define ATHUB_BASE__INST6_SEG4 0233234#define CLK_BASE__INST0_SEG0 0x00016C00235#define CLK_BASE__INST0_SEG1 0x02401800236#define CLK_BASE__INST0_SEG2 0237#define CLK_BASE__INST0_SEG3 0238#define CLK_BASE__INST0_SEG4 0239240#define CLK_BASE__INST1_SEG0 0x00016E00241#define CLK_BASE__INST1_SEG1 0x02401C00242#define CLK_BASE__INST1_SEG2 0243#define CLK_BASE__INST1_SEG3 0244#define CLK_BASE__INST1_SEG4 0245246#define CLK_BASE__INST2_SEG0 0x00017000247#define CLK_BASE__INST2_SEG1 0x02402000248#define CLK_BASE__INST2_SEG2 0249#define CLK_BASE__INST2_SEG3 0250#define CLK_BASE__INST2_SEG4 0251252#define CLK_BASE__INST3_SEG0 0x00017200253#define CLK_BASE__INST3_SEG1 0x02402400254#define CLK_BASE__INST3_SEG2 0255#define CLK_BASE__INST3_SEG3 0256#define CLK_BASE__INST3_SEG4 0257258#define CLK_BASE__INST4_SEG0 0x0001B000259#define CLK_BASE__INST4_SEG1 0x0242D800260#define CLK_BASE__INST4_SEG2 0261#define CLK_BASE__INST4_SEG3 0262#define CLK_BASE__INST4_SEG4 0263264#define CLK_BASE__INST5_SEG0 0x00017E00265#define CLK_BASE__INST5_SEG1 0x0240BC00266#define CLK_BASE__INST5_SEG2 0267#define CLK_BASE__INST5_SEG3 0268#define CLK_BASE__INST5_SEG4 0269270#define CLK_BASE__INST6_SEG0 0271#define CLK_BASE__INST6_SEG1 0272#define CLK_BASE__INST6_SEG2 0273#define CLK_BASE__INST6_SEG3 0274#define CLK_BASE__INST6_SEG4 0275276#define DF_BASE__INST0_SEG0 0x00007000277#define DF_BASE__INST0_SEG1 0x0240B800278#define DF_BASE__INST0_SEG2 0279#define DF_BASE__INST0_SEG3 0280#define DF_BASE__INST0_SEG4 0281282#define DF_BASE__INST1_SEG0 0283#define DF_BASE__INST1_SEG1 0284#define DF_BASE__INST1_SEG2 0285#define DF_BASE__INST1_SEG3 0286#define DF_BASE__INST1_SEG4 0287288#define DF_BASE__INST2_SEG0 0289#define DF_BASE__INST2_SEG1 0290#define DF_BASE__INST2_SEG2 0291#define DF_BASE__INST2_SEG3 0292#define DF_BASE__INST2_SEG4 0293294#define DF_BASE__INST3_SEG0 0295#define DF_BASE__INST3_SEG1 0296#define DF_BASE__INST3_SEG2 0297#define DF_BASE__INST3_SEG3 0298#define DF_BASE__INST3_SEG4 0299300#define DF_BASE__INST4_SEG0 0301#define DF_BASE__INST4_SEG1 0302#define DF_BASE__INST4_SEG2 0303#define DF_BASE__INST4_SEG3 0304#define DF_BASE__INST4_SEG4 0305306#define DF_BASE__INST5_SEG0 0307#define DF_BASE__INST5_SEG1 0308#define DF_BASE__INST5_SEG2 0309#define DF_BASE__INST5_SEG3 0310#define DF_BASE__INST5_SEG4 0311312#define DF_BASE__INST6_SEG0 0313#define DF_BASE__INST6_SEG1 0314#define DF_BASE__INST6_SEG2 0315#define DF_BASE__INST6_SEG3 0316#define DF_BASE__INST6_SEG4 0317318#define DIO_BASE__INST0_SEG0 0x02404000319#define DIO_BASE__INST0_SEG1 0320#define DIO_BASE__INST0_SEG2 0321#define DIO_BASE__INST0_SEG3 0322#define DIO_BASE__INST0_SEG4 0323324#define DIO_BASE__INST1_SEG0 0325#define DIO_BASE__INST1_SEG1 0326#define DIO_BASE__INST1_SEG2 0327#define DIO_BASE__INST1_SEG3 0328#define DIO_BASE__INST1_SEG4 0329330#define DIO_BASE__INST2_SEG0 0331#define DIO_BASE__INST2_SEG1 0332#define DIO_BASE__INST2_SEG2 0333#define DIO_BASE__INST2_SEG3 0334#define DIO_BASE__INST2_SEG4 0335336#define DIO_BASE__INST3_SEG0 0337#define DIO_BASE__INST3_SEG1 0338#define DIO_BASE__INST3_SEG2 0339#define DIO_BASE__INST3_SEG3 0340#define DIO_BASE__INST3_SEG4 0341342#define DIO_BASE__INST4_SEG0 0343#define DIO_BASE__INST4_SEG1 0344#define DIO_BASE__INST4_SEG2 0345#define DIO_BASE__INST4_SEG3 0346#define DIO_BASE__INST4_SEG4 0347348#define DIO_BASE__INST5_SEG0 0349#define DIO_BASE__INST5_SEG1 0350#define DIO_BASE__INST5_SEG2 0351#define DIO_BASE__INST5_SEG3 0352#define DIO_BASE__INST5_SEG4 0353354#define DIO_BASE__INST6_SEG0 0355#define DIO_BASE__INST6_SEG1 0356#define DIO_BASE__INST6_SEG2 0357#define DIO_BASE__INST6_SEG3 0358#define DIO_BASE__INST6_SEG4 0359360#define DMU_BASE__INST0_SEG0 0x00000012361#define DMU_BASE__INST0_SEG1 0x000000C0362#define DMU_BASE__INST0_SEG2 0x000034C0363#define DMU_BASE__INST0_SEG3 0x00009000364#define DMU_BASE__INST0_SEG4 0x02403C00365366#define DMU_BASE__INST1_SEG0 0367#define DMU_BASE__INST1_SEG1 0368#define DMU_BASE__INST1_SEG2 0369#define DMU_BASE__INST1_SEG3 0370#define DMU_BASE__INST1_SEG4 0371372#define DMU_BASE__INST2_SEG0 0373#define DMU_BASE__INST2_SEG1 0374#define DMU_BASE__INST2_SEG2 0375#define DMU_BASE__INST2_SEG3 0376#define DMU_BASE__INST2_SEG4 0377378#define DMU_BASE__INST3_SEG0 0379#define DMU_BASE__INST3_SEG1 0380#define DMU_BASE__INST3_SEG2 0381#define DMU_BASE__INST3_SEG3 0382#define DMU_BASE__INST3_SEG4 0383384#define DMU_BASE__INST4_SEG0 0385#define DMU_BASE__INST4_SEG1 0386#define DMU_BASE__INST4_SEG2 0387#define DMU_BASE__INST4_SEG3 0388#define DMU_BASE__INST4_SEG4 0389390#define DMU_BASE__INST5_SEG0 0391#define DMU_BASE__INST5_SEG1 0392#define DMU_BASE__INST5_SEG2 0393#define DMU_BASE__INST5_SEG3 0394#define DMU_BASE__INST5_SEG4 0395396#define DMU_BASE__INST6_SEG0 0397#define DMU_BASE__INST6_SEG1 0398#define DMU_BASE__INST6_SEG2 0399#define DMU_BASE__INST6_SEG3 0400#define DMU_BASE__INST6_SEG4 0401402#define DPCS_BASE__INST0_SEG0 0x00000012403#define DPCS_BASE__INST0_SEG1 0x000000C0404#define DPCS_BASE__INST0_SEG2 0x000034C0405#define DPCS_BASE__INST0_SEG3 0x00009000406#define DPCS_BASE__INST0_SEG4 0x02403C00407408#define DPCS_BASE__INST1_SEG0 0409#define DPCS_BASE__INST1_SEG1 0410#define DPCS_BASE__INST1_SEG2 0411#define DPCS_BASE__INST1_SEG3 0412#define DPCS_BASE__INST1_SEG4 0413414#define DPCS_BASE__INST2_SEG0 0415#define DPCS_BASE__INST2_SEG1 0416#define DPCS_BASE__INST2_SEG2 0417#define DPCS_BASE__INST2_SEG3 0418#define DPCS_BASE__INST2_SEG4 0419420#define DPCS_BASE__INST3_SEG0 0421#define DPCS_BASE__INST3_SEG1 0422#define DPCS_BASE__INST3_SEG2 0423#define DPCS_BASE__INST3_SEG3 0424#define DPCS_BASE__INST3_SEG4 0425426#define DPCS_BASE__INST4_SEG0 0427#define DPCS_BASE__INST4_SEG1 0428#define DPCS_BASE__INST4_SEG2 0429#define DPCS_BASE__INST4_SEG3 0430#define DPCS_BASE__INST4_SEG4 0431432#define DPCS_BASE__INST5_SEG0 0433#define DPCS_BASE__INST5_SEG1 0434#define DPCS_BASE__INST5_SEG2 0435#define DPCS_BASE__INST5_SEG3 0436#define DPCS_BASE__INST5_SEG4 0437438#define DPCS_BASE__INST6_SEG0 0439#define DPCS_BASE__INST6_SEG1 0440#define DPCS_BASE__INST6_SEG2 0441#define DPCS_BASE__INST6_SEG3 0442#define DPCS_BASE__INST6_SEG4 0443444#define FUSE_BASE__INST0_SEG0 0x00017400445#define FUSE_BASE__INST0_SEG1 0x02401400446#define FUSE_BASE__INST0_SEG2 0447#define FUSE_BASE__INST0_SEG3 0448#define FUSE_BASE__INST0_SEG4 0449450#define FUSE_BASE__INST1_SEG0 0451#define FUSE_BASE__INST1_SEG1 0452#define FUSE_BASE__INST1_SEG2 0453#define FUSE_BASE__INST1_SEG3 0454#define FUSE_BASE__INST1_SEG4 0455456#define FUSE_BASE__INST2_SEG0 0457#define FUSE_BASE__INST2_SEG1 0458#define FUSE_BASE__INST2_SEG2 0459#define FUSE_BASE__INST2_SEG3 0460#define FUSE_BASE__INST2_SEG4 0461462#define FUSE_BASE__INST3_SEG0 0463#define FUSE_BASE__INST3_SEG1 0464#define FUSE_BASE__INST3_SEG2 0465#define FUSE_BASE__INST3_SEG3 0466#define FUSE_BASE__INST3_SEG4 0467468#define FUSE_BASE__INST4_SEG0 0469#define FUSE_BASE__INST4_SEG1 0470#define FUSE_BASE__INST4_SEG2 0471#define FUSE_BASE__INST4_SEG3 0472#define FUSE_BASE__INST4_SEG4 0473474#define FUSE_BASE__INST5_SEG0 0475#define FUSE_BASE__INST5_SEG1 0476#define FUSE_BASE__INST5_SEG2 0477#define FUSE_BASE__INST5_SEG3 0478#define FUSE_BASE__INST5_SEG4 0479480#define FUSE_BASE__INST6_SEG0 0481#define FUSE_BASE__INST6_SEG1 0482#define FUSE_BASE__INST6_SEG2 0483#define FUSE_BASE__INST6_SEG3 0484#define FUSE_BASE__INST6_SEG4 0485486#define GC_BASE__INST0_SEG0 0x00001260487#define GC_BASE__INST0_SEG1 0x0000A000488#define GC_BASE__INST0_SEG2 0x02402C00489#define GC_BASE__INST0_SEG3 0490#define GC_BASE__INST0_SEG4 0491492#define GC_BASE__INST1_SEG0 0493#define GC_BASE__INST1_SEG1 0494#define GC_BASE__INST1_SEG2 0495#define GC_BASE__INST1_SEG3 0496#define GC_BASE__INST1_SEG4 0497498#define GC_BASE__INST2_SEG0 0499#define GC_BASE__INST2_SEG1 0500#define GC_BASE__INST2_SEG2 0501#define GC_BASE__INST2_SEG3 0502#define GC_BASE__INST2_SEG4 0503504#define GC_BASE__INST3_SEG0 0505#define GC_BASE__INST3_SEG1 0506#define GC_BASE__INST3_SEG2 0507#define GC_BASE__INST3_SEG3 0508#define GC_BASE__INST3_SEG4 0509510#define GC_BASE__INST4_SEG0 0511#define GC_BASE__INST4_SEG1 0512#define GC_BASE__INST4_SEG2 0513#define GC_BASE__INST4_SEG3 0514#define GC_BASE__INST4_SEG4 0515516#define GC_BASE__INST5_SEG0 0517#define GC_BASE__INST5_SEG1 0518#define GC_BASE__INST5_SEG2 0519#define GC_BASE__INST5_SEG3 0520#define GC_BASE__INST5_SEG4 0521522#define GC_BASE__INST6_SEG0 0523#define GC_BASE__INST6_SEG1 0524#define GC_BASE__INST6_SEG2 0525#define GC_BASE__INST6_SEG3 0526#define GC_BASE__INST6_SEG4 0527528#define HDA_BASE__INST0_SEG0 0x004C0000529#define HDA_BASE__INST0_SEG1 0x02404800530#define HDA_BASE__INST0_SEG2 0531#define HDA_BASE__INST0_SEG3 0532#define HDA_BASE__INST0_SEG4 0533534#define HDA_BASE__INST1_SEG0 0535#define HDA_BASE__INST1_SEG1 0536#define HDA_BASE__INST1_SEG2 0537#define HDA_BASE__INST1_SEG3 0538#define HDA_BASE__INST1_SEG4 0539540#define HDA_BASE__INST2_SEG0 0541#define HDA_BASE__INST2_SEG1 0542#define HDA_BASE__INST2_SEG2 0543#define HDA_BASE__INST2_SEG3 0544#define HDA_BASE__INST2_SEG4 0545546#define HDA_BASE__INST3_SEG0 0547#define HDA_BASE__INST3_SEG1 0548#define HDA_BASE__INST3_SEG2 0549#define HDA_BASE__INST3_SEG3 0550#define HDA_BASE__INST3_SEG4 0551552#define HDA_BASE__INST4_SEG0 0553#define HDA_BASE__INST4_SEG1 0554#define HDA_BASE__INST4_SEG2 0555#define HDA_BASE__INST4_SEG3 0556#define HDA_BASE__INST4_SEG4 0557558#define HDA_BASE__INST5_SEG0 0559#define HDA_BASE__INST5_SEG1 0560#define HDA_BASE__INST5_SEG2 0561#define HDA_BASE__INST5_SEG3 0562#define HDA_BASE__INST5_SEG4 0563564#define HDA_BASE__INST6_SEG0 0565#define HDA_BASE__INST6_SEG1 0566#define HDA_BASE__INST6_SEG2 0567#define HDA_BASE__INST6_SEG3 0568#define HDA_BASE__INST6_SEG4 0569570#define HDP_BASE__INST0_SEG0 0x00000F20571#define HDP_BASE__INST0_SEG1 0x0240A400572#define HDP_BASE__INST0_SEG2 0573#define HDP_BASE__INST0_SEG3 0574#define HDP_BASE__INST0_SEG4 0575576#define HDP_BASE__INST1_SEG0 0577#define HDP_BASE__INST1_SEG1 0578#define HDP_BASE__INST1_SEG2 0579#define HDP_BASE__INST1_SEG3 0580#define HDP_BASE__INST1_SEG4 0581582#define HDP_BASE__INST2_SEG0 0583#define HDP_BASE__INST2_SEG1 0584#define HDP_BASE__INST2_SEG2 0585#define HDP_BASE__INST2_SEG3 0586#define HDP_BASE__INST2_SEG4 0587588#define HDP_BASE__INST3_SEG0 0589#define HDP_BASE__INST3_SEG1 0590#define HDP_BASE__INST3_SEG2 0591#define HDP_BASE__INST3_SEG3 0592#define HDP_BASE__INST3_SEG4 0593594#define HDP_BASE__INST4_SEG0 0595#define HDP_BASE__INST4_SEG1 0596#define HDP_BASE__INST4_SEG2 0597#define HDP_BASE__INST4_SEG3 0598#define HDP_BASE__INST4_SEG4 0599600#define HDP_BASE__INST5_SEG0 0601#define HDP_BASE__INST5_SEG1 0602#define HDP_BASE__INST5_SEG2 0603#define HDP_BASE__INST5_SEG3 0604#define HDP_BASE__INST5_SEG4 0605606#define HDP_BASE__INST6_SEG0 0607#define HDP_BASE__INST6_SEG1 0608#define HDP_BASE__INST6_SEG2 0609#define HDP_BASE__INST6_SEG3 0610#define HDP_BASE__INST6_SEG4 0611612#define MMHUB_BASE__INST0_SEG0 0x0001A000613#define MMHUB_BASE__INST0_SEG1 0x02408800614#define MMHUB_BASE__INST0_SEG2 0615#define MMHUB_BASE__INST0_SEG3 0616#define MMHUB_BASE__INST0_SEG4 0617618#define MMHUB_BASE__INST1_SEG0 0619#define MMHUB_BASE__INST1_SEG1 0620#define MMHUB_BASE__INST1_SEG2 0621#define MMHUB_BASE__INST1_SEG3 0622#define MMHUB_BASE__INST1_SEG4 0623624#define MMHUB_BASE__INST2_SEG0 0625#define MMHUB_BASE__INST2_SEG1 0626#define MMHUB_BASE__INST2_SEG2 0627#define MMHUB_BASE__INST2_SEG3 0628#define MMHUB_BASE__INST2_SEG4 0629630#define MMHUB_BASE__INST3_SEG0 0631#define MMHUB_BASE__INST3_SEG1 0632#define MMHUB_BASE__INST3_SEG2 0633#define MMHUB_BASE__INST3_SEG3 0634#define MMHUB_BASE__INST3_SEG4 0635636#define MMHUB_BASE__INST4_SEG0 0637#define MMHUB_BASE__INST4_SEG1 0638#define MMHUB_BASE__INST4_SEG2 0639#define MMHUB_BASE__INST4_SEG3 0640#define MMHUB_BASE__INST4_SEG4 0641642#define MMHUB_BASE__INST5_SEG0 0643#define MMHUB_BASE__INST5_SEG1 0644#define MMHUB_BASE__INST5_SEG2 0645#define MMHUB_BASE__INST5_SEG3 0646#define MMHUB_BASE__INST5_SEG4 0647648#define MMHUB_BASE__INST6_SEG0 0649#define MMHUB_BASE__INST6_SEG1 0650#define MMHUB_BASE__INST6_SEG2 0651#define MMHUB_BASE__INST6_SEG3 0652#define MMHUB_BASE__INST6_SEG4 0653654#define MP0_BASE__INST0_SEG0 0x00016000655#define MP0_BASE__INST0_SEG1 0x00DC0000656#define MP0_BASE__INST0_SEG2 0x00E00000657#define MP0_BASE__INST0_SEG3 0x00E40000658#define MP0_BASE__INST0_SEG4 0x0243FC00659660#define MP0_BASE__INST1_SEG0 0661#define MP0_BASE__INST1_SEG1 0662#define MP0_BASE__INST1_SEG2 0663#define MP0_BASE__INST1_SEG3 0664#define MP0_BASE__INST1_SEG4 0665666#define MP0_BASE__INST2_SEG0 0667#define MP0_BASE__INST2_SEG1 0668#define MP0_BASE__INST2_SEG2 0669#define MP0_BASE__INST2_SEG3 0670#define MP0_BASE__INST2_SEG4 0671672#define MP0_BASE__INST3_SEG0 0673#define MP0_BASE__INST3_SEG1 0674#define MP0_BASE__INST3_SEG2 0675#define MP0_BASE__INST3_SEG3 0676#define MP0_BASE__INST3_SEG4 0677678#define MP0_BASE__INST4_SEG0 0679#define MP0_BASE__INST4_SEG1 0680#define MP0_BASE__INST4_SEG2 0681#define MP0_BASE__INST4_SEG3 0682#define MP0_BASE__INST4_SEG4 0683684#define MP0_BASE__INST5_SEG0 0685#define MP0_BASE__INST5_SEG1 0686#define MP0_BASE__INST5_SEG2 0687#define MP0_BASE__INST5_SEG3 0688#define MP0_BASE__INST5_SEG4 0689690#define MP0_BASE__INST6_SEG0 0691#define MP0_BASE__INST6_SEG1 0692#define MP0_BASE__INST6_SEG2 0693#define MP0_BASE__INST6_SEG3 0694#define MP0_BASE__INST6_SEG4 0695696#define MP1_BASE__INST0_SEG0 0x00016000697#define MP1_BASE__INST0_SEG1 0x00DC0000698#define MP1_BASE__INST0_SEG2 0x00E00000699#define MP1_BASE__INST0_SEG3 0x00E40000700#define MP1_BASE__INST0_SEG4 0x0243FC00701702#define MP1_BASE__INST1_SEG0 0703#define MP1_BASE__INST1_SEG1 0704#define MP1_BASE__INST1_SEG2 0705#define MP1_BASE__INST1_SEG3 0706#define MP1_BASE__INST1_SEG4 0707708#define MP1_BASE__INST2_SEG0 0709#define MP1_BASE__INST2_SEG1 0710#define MP1_BASE__INST2_SEG2 0711#define MP1_BASE__INST2_SEG3 0712#define MP1_BASE__INST2_SEG4 0713714#define MP1_BASE__INST3_SEG0 0715#define MP1_BASE__INST3_SEG1 0716#define MP1_BASE__INST3_SEG2 0717#define MP1_BASE__INST3_SEG3 0718#define MP1_BASE__INST3_SEG4 0719720#define MP1_BASE__INST4_SEG0 0721#define MP1_BASE__INST4_SEG1 0722#define MP1_BASE__INST4_SEG2 0723#define MP1_BASE__INST4_SEG3 0724#define MP1_BASE__INST4_SEG4 0725726#define MP1_BASE__INST5_SEG0 0727#define MP1_BASE__INST5_SEG1 0728#define MP1_BASE__INST5_SEG2 0729#define MP1_BASE__INST5_SEG3 0730#define MP1_BASE__INST5_SEG4 0731732#define MP1_BASE__INST6_SEG0 0733#define MP1_BASE__INST6_SEG1 0734#define MP1_BASE__INST6_SEG2 0735#define MP1_BASE__INST6_SEG3 0736#define MP1_BASE__INST6_SEG4 0737738#define NBIF0_BASE__INST0_SEG0 0x00000000739#define NBIF0_BASE__INST0_SEG1 0x00000014740#define NBIF0_BASE__INST0_SEG2 0x00000D20741#define NBIF0_BASE__INST0_SEG3 0x00010400742#define NBIF0_BASE__INST0_SEG4 0x0241B000743744#define NBIF0_BASE__INST1_SEG0 0745#define NBIF0_BASE__INST1_SEG1 0746#define NBIF0_BASE__INST1_SEG2 0747#define NBIF0_BASE__INST1_SEG3 0748#define NBIF0_BASE__INST1_SEG4 0749750#define NBIF0_BASE__INST2_SEG0 0751#define NBIF0_BASE__INST2_SEG1 0752#define NBIF0_BASE__INST2_SEG2 0753#define NBIF0_BASE__INST2_SEG3 0754#define NBIF0_BASE__INST2_SEG4 0755756#define NBIF0_BASE__INST3_SEG0 0757#define NBIF0_BASE__INST3_SEG1 0758#define NBIF0_BASE__INST3_SEG2 0759#define NBIF0_BASE__INST3_SEG3 0760#define NBIF0_BASE__INST3_SEG4 0761762#define NBIF0_BASE__INST4_SEG0 0763#define NBIF0_BASE__INST4_SEG1 0764#define NBIF0_BASE__INST4_SEG2 0765#define NBIF0_BASE__INST4_SEG3 0766#define NBIF0_BASE__INST4_SEG4 0767768#define NBIF0_BASE__INST5_SEG0 0769#define NBIF0_BASE__INST5_SEG1 0770#define NBIF0_BASE__INST5_SEG2 0771#define NBIF0_BASE__INST5_SEG3 0772#define NBIF0_BASE__INST5_SEG4 0773774#define NBIF0_BASE__INST6_SEG0 0775#define NBIF0_BASE__INST6_SEG1 0776#define NBIF0_BASE__INST6_SEG2 0777#define NBIF0_BASE__INST6_SEG3 0778#define NBIF0_BASE__INST6_SEG4 0779780#define OSSSYS_BASE__INST0_SEG0 0x000010A0781#define OSSSYS_BASE__INST0_SEG1 0x0240A000782#define OSSSYS_BASE__INST0_SEG2 0783#define OSSSYS_BASE__INST0_SEG3 0784#define OSSSYS_BASE__INST0_SEG4 0785786#define OSSSYS_BASE__INST1_SEG0 0787#define OSSSYS_BASE__INST1_SEG1 0788#define OSSSYS_BASE__INST1_SEG2 0789#define OSSSYS_BASE__INST1_SEG3 0790#define OSSSYS_BASE__INST1_SEG4 0791792#define OSSSYS_BASE__INST2_SEG0 0793#define OSSSYS_BASE__INST2_SEG1 0794#define OSSSYS_BASE__INST2_SEG2 0795#define OSSSYS_BASE__INST2_SEG3 0796#define OSSSYS_BASE__INST2_SEG4 0797798#define OSSSYS_BASE__INST3_SEG0 0799#define OSSSYS_BASE__INST3_SEG1 0800#define OSSSYS_BASE__INST3_SEG2 0801#define OSSSYS_BASE__INST3_SEG3 0802#define OSSSYS_BASE__INST3_SEG4 0803804#define OSSSYS_BASE__INST4_SEG0 0805#define OSSSYS_BASE__INST4_SEG1 0806#define OSSSYS_BASE__INST4_SEG2 0807#define OSSSYS_BASE__INST4_SEG3 0808#define OSSSYS_BASE__INST4_SEG4 0809810#define OSSSYS_BASE__INST5_SEG0 0811#define OSSSYS_BASE__INST5_SEG1 0812#define OSSSYS_BASE__INST5_SEG2 0813#define OSSSYS_BASE__INST5_SEG3 0814#define OSSSYS_BASE__INST5_SEG4 0815816#define OSSSYS_BASE__INST6_SEG0 0817#define OSSSYS_BASE__INST6_SEG1 0818#define OSSSYS_BASE__INST6_SEG2 0819#define OSSSYS_BASE__INST6_SEG3 0820#define OSSSYS_BASE__INST6_SEG4 0821822#define PCIE0_BASE__INST0_SEG0 0x00000000823#define PCIE0_BASE__INST0_SEG1 0x00000014824#define PCIE0_BASE__INST0_SEG2 0x00000D20825#define PCIE0_BASE__INST0_SEG3 0x00010400826#define PCIE0_BASE__INST0_SEG4 0x0241B000827828#define PCIE0_BASE__INST1_SEG0 0829#define PCIE0_BASE__INST1_SEG1 0830#define PCIE0_BASE__INST1_SEG2 0831#define PCIE0_BASE__INST1_SEG3 0832#define PCIE0_BASE__INST1_SEG4 0833834#define PCIE0_BASE__INST2_SEG0 0835#define PCIE0_BASE__INST2_SEG1 0836#define PCIE0_BASE__INST2_SEG2 0837#define PCIE0_BASE__INST2_SEG3 0838#define PCIE0_BASE__INST2_SEG4 0839840#define PCIE0_BASE__INST3_SEG0 0841#define PCIE0_BASE__INST3_SEG1 0842#define PCIE0_BASE__INST3_SEG2 0843#define PCIE0_BASE__INST3_SEG3 0844#define PCIE0_BASE__INST3_SEG4 0845846#define PCIE0_BASE__INST4_SEG0 0847#define PCIE0_BASE__INST4_SEG1 0848#define PCIE0_BASE__INST4_SEG2 0849#define PCIE0_BASE__INST4_SEG3 0850#define PCIE0_BASE__INST4_SEG4 0851852#define PCIE0_BASE__INST5_SEG0 0853#define PCIE0_BASE__INST5_SEG1 0854#define PCIE0_BASE__INST5_SEG2 0855#define PCIE0_BASE__INST5_SEG3 0856#define PCIE0_BASE__INST5_SEG4 0857858#define PCIE0_BASE__INST6_SEG0 0859#define PCIE0_BASE__INST6_SEG1 0860#define PCIE0_BASE__INST6_SEG2 0861#define PCIE0_BASE__INST6_SEG3 0862#define PCIE0_BASE__INST6_SEG4 0863864#define SDMA_BASE__INST0_SEG0 0x00001260865#define SDMA_BASE__INST0_SEG1 0x0000A000866#define SDMA_BASE__INST0_SEG2 0x02402C00867#define SDMA_BASE__INST0_SEG3 0868#define SDMA_BASE__INST0_SEG4 0869870#define SDMA_BASE__INST1_SEG0 0x00001260871#define SDMA_BASE__INST1_SEG1 0x0000A000872#define SDMA_BASE__INST1_SEG2 0x02402C00873#define SDMA_BASE__INST1_SEG3 0874#define SDMA_BASE__INST1_SEG4 0875876#define SDMA_BASE__INST2_SEG0 0877#define SDMA_BASE__INST2_SEG1 0878#define SDMA_BASE__INST2_SEG2 0879#define SDMA_BASE__INST2_SEG3 0880#define SDMA_BASE__INST2_SEG4 0881882#define SDMA_BASE__INST3_SEG0 0883#define SDMA_BASE__INST3_SEG1 0884#define SDMA_BASE__INST3_SEG2 0885#define SDMA_BASE__INST3_SEG3 0886#define SDMA_BASE__INST3_SEG4 0887888#define SDMA_BASE__INST4_SEG0 0889#define SDMA_BASE__INST4_SEG1 0890#define SDMA_BASE__INST4_SEG2 0891#define SDMA_BASE__INST4_SEG3 0892#define SDMA_BASE__INST4_SEG4 0893894#define SDMA_BASE__INST5_SEG0 0895#define SDMA_BASE__INST5_SEG1 0896#define SDMA_BASE__INST5_SEG2 0897#define SDMA_BASE__INST5_SEG3 0898#define SDMA_BASE__INST5_SEG4 0899900#define SDMA_BASE__INST6_SEG0 0901#define SDMA_BASE__INST6_SEG1 0902#define SDMA_BASE__INST6_SEG2 0903#define SDMA_BASE__INST6_SEG3 0904#define SDMA_BASE__INST6_SEG4 0905906#define SMUIO_BASE__INST0_SEG0 0x00016800907#define SMUIO_BASE__INST0_SEG1 0x00016A00908#define SMUIO_BASE__INST0_SEG2 0x00440000909#define SMUIO_BASE__INST0_SEG3 0x02401000910#define SMUIO_BASE__INST0_SEG4 0911912#define SMUIO_BASE__INST1_SEG0 0913#define SMUIO_BASE__INST1_SEG1 0914#define SMUIO_BASE__INST1_SEG2 0915#define SMUIO_BASE__INST1_SEG3 0916#define SMUIO_BASE__INST1_SEG4 0917918#define SMUIO_BASE__INST2_SEG0 0919#define SMUIO_BASE__INST2_SEG1 0920#define SMUIO_BASE__INST2_SEG2 0921#define SMUIO_BASE__INST2_SEG3 0922#define SMUIO_BASE__INST2_SEG4 0923924#define SMUIO_BASE__INST3_SEG0 0925#define SMUIO_BASE__INST3_SEG1 0926#define SMUIO_BASE__INST3_SEG2 0927#define SMUIO_BASE__INST3_SEG3 0928#define SMUIO_BASE__INST3_SEG4 0929930#define SMUIO_BASE__INST4_SEG0 0931#define SMUIO_BASE__INST4_SEG1 0932#define SMUIO_BASE__INST4_SEG2 0933#define SMUIO_BASE__INST4_SEG3 0934#define SMUIO_BASE__INST4_SEG4 0935936#define SMUIO_BASE__INST5_SEG0 0937#define SMUIO_BASE__INST5_SEG1 0938#define SMUIO_BASE__INST5_SEG2 0939#define SMUIO_BASE__INST5_SEG3 0940#define SMUIO_BASE__INST5_SEG4 0941942#define SMUIO_BASE__INST6_SEG0 0943#define SMUIO_BASE__INST6_SEG1 0944#define SMUIO_BASE__INST6_SEG2 0945#define SMUIO_BASE__INST6_SEG3 0946#define SMUIO_BASE__INST6_SEG4 0947948#define THM_BASE__INST0_SEG0 0x00016600949#define THM_BASE__INST0_SEG1 0x02400C00950#define THM_BASE__INST0_SEG2 0951#define THM_BASE__INST0_SEG3 0952#define THM_BASE__INST0_SEG4 0953954#define THM_BASE__INST1_SEG0 0955#define THM_BASE__INST1_SEG1 0956#define THM_BASE__INST1_SEG2 0957#define THM_BASE__INST1_SEG3 0958#define THM_BASE__INST1_SEG4 0959960#define THM_BASE__INST2_SEG0 0961#define THM_BASE__INST2_SEG1 0962#define THM_BASE__INST2_SEG2 0963#define THM_BASE__INST2_SEG3 0964#define THM_BASE__INST2_SEG4 0965966#define THM_BASE__INST3_SEG0 0967#define THM_BASE__INST3_SEG1 0968#define THM_BASE__INST3_SEG2 0969#define THM_BASE__INST3_SEG3 0970#define THM_BASE__INST3_SEG4 0971972#define THM_BASE__INST4_SEG0 0973#define THM_BASE__INST4_SEG1 0974#define THM_BASE__INST4_SEG2 0975#define THM_BASE__INST4_SEG3 0976#define THM_BASE__INST4_SEG4 0977978#define THM_BASE__INST5_SEG0 0979#define THM_BASE__INST5_SEG1 0980#define THM_BASE__INST5_SEG2 0981#define THM_BASE__INST5_SEG3 0982#define THM_BASE__INST5_SEG4 0983984#define THM_BASE__INST6_SEG0 0985#define THM_BASE__INST6_SEG1 0986#define THM_BASE__INST6_SEG2 0987#define THM_BASE__INST6_SEG3 0988#define THM_BASE__INST6_SEG4 0989990#define UMC_BASE__INST0_SEG0 0x00014000991#define UMC_BASE__INST0_SEG1 0x02425800992#define UMC_BASE__INST0_SEG2 0993#define UMC_BASE__INST0_SEG3 0994#define UMC_BASE__INST0_SEG4 0995996#define UMC_BASE__INST1_SEG0 0x00054000997#define UMC_BASE__INST1_SEG1 0x02425C00998#define UMC_BASE__INST1_SEG2 0999#define UMC_BASE__INST1_SEG3 01000#define UMC_BASE__INST1_SEG4 010011002#define UMC_BASE__INST2_SEG0 0x000940001003#define UMC_BASE__INST2_SEG1 0x024260001004#define UMC_BASE__INST2_SEG2 01005#define UMC_BASE__INST2_SEG3 01006#define UMC_BASE__INST2_SEG4 010071008#define UMC_BASE__INST3_SEG0 0x000D40001009#define UMC_BASE__INST3_SEG1 0x024264001010#define UMC_BASE__INST3_SEG2 01011#define UMC_BASE__INST3_SEG3 01012#define UMC_BASE__INST3_SEG4 010131014#define UMC_BASE__INST4_SEG0 01015#define UMC_BASE__INST4_SEG1 01016#define UMC_BASE__INST4_SEG2 01017#define UMC_BASE__INST4_SEG3 01018#define UMC_BASE__INST4_SEG4 010191020#define UMC_BASE__INST5_SEG0 01021#define UMC_BASE__INST5_SEG1 01022#define UMC_BASE__INST5_SEG2 01023#define UMC_BASE__INST5_SEG3 01024#define UMC_BASE__INST5_SEG4 010251026#define UMC_BASE__INST6_SEG0 01027#define UMC_BASE__INST6_SEG1 01028#define UMC_BASE__INST6_SEG2 01029#define UMC_BASE__INST6_SEG3 01030#define UMC_BASE__INST6_SEG4 010311032#define USB0_BASE__INST0_SEG0 0x0242A8001033#define USB0_BASE__INST0_SEG1 0x05B000001034#define USB0_BASE__INST0_SEG2 01035#define USB0_BASE__INST0_SEG3 01036#define USB0_BASE__INST0_SEG4 010371038#define USB0_BASE__INST1_SEG0 01039#define USB0_BASE__INST1_SEG1 01040#define USB0_BASE__INST1_SEG2 01041#define USB0_BASE__INST1_SEG3 01042#define USB0_BASE__INST1_SEG4 010431044#define USB0_BASE__INST2_SEG0 01045#define USB0_BASE__INST2_SEG1 01046#define USB0_BASE__INST2_SEG2 01047#define USB0_BASE__INST2_SEG3 01048#define USB0_BASE__INST2_SEG4 010491050#define USB0_BASE__INST3_SEG0 01051#define USB0_BASE__INST3_SEG1 01052#define USB0_BASE__INST3_SEG2 01053#define USB0_BASE__INST3_SEG3 01054#define USB0_BASE__INST3_SEG4 010551056#define USB0_BASE__INST4_SEG0 01057#define USB0_BASE__INST4_SEG1 01058#define USB0_BASE__INST4_SEG2 01059#define USB0_BASE__INST4_SEG3 01060#define USB0_BASE__INST4_SEG4 010611062#define USB0_BASE__INST5_SEG0 01063#define USB0_BASE__INST5_SEG1 01064#define USB0_BASE__INST5_SEG2 01065#define USB0_BASE__INST5_SEG3 01066#define USB0_BASE__INST5_SEG4 010671068#define USB0_BASE__INST6_SEG0 01069#define USB0_BASE__INST6_SEG1 01070#define USB0_BASE__INST6_SEG2 01071#define USB0_BASE__INST6_SEG3 01072#define USB0_BASE__INST6_SEG4 010731074#define UVD0_BASE__INST0_SEG0 0x000078001075#define UVD0_BASE__INST0_SEG1 0x00007E001076#define UVD0_BASE__INST0_SEG2 0x024030001077#define UVD0_BASE__INST0_SEG3 01078#define UVD0_BASE__INST0_SEG4 010791080#define UVD0_BASE__INST1_SEG0 01081#define UVD0_BASE__INST1_SEG1 01082#define UVD0_BASE__INST1_SEG2 01083#define UVD0_BASE__INST1_SEG3 01084#define UVD0_BASE__INST1_SEG4 010851086#define UVD0_BASE__INST2_SEG0 01087#define UVD0_BASE__INST2_SEG1 01088#define UVD0_BASE__INST2_SEG2 01089#define UVD0_BASE__INST2_SEG3 01090#define UVD0_BASE__INST2_SEG4 010911092#define UVD0_BASE__INST3_SEG0 01093#define UVD0_BASE__INST3_SEG1 01094#define UVD0_BASE__INST3_SEG2 01095#define UVD0_BASE__INST3_SEG3 01096#define UVD0_BASE__INST3_SEG4 010971098#define UVD0_BASE__INST4_SEG0 01099#define UVD0_BASE__INST4_SEG1 01100#define UVD0_BASE__INST4_SEG2 01101#define UVD0_BASE__INST4_SEG3 01102#define UVD0_BASE__INST4_SEG4 011031104#define UVD0_BASE__INST5_SEG0 01105#define UVD0_BASE__INST5_SEG1 01106#define UVD0_BASE__INST5_SEG2 01107#define UVD0_BASE__INST5_SEG3 01108#define UVD0_BASE__INST5_SEG4 011091110#define UVD0_BASE__INST6_SEG0 01111#define UVD0_BASE__INST6_SEG1 01112#define UVD0_BASE__INST6_SEG2 01113#define UVD0_BASE__INST6_SEG3 01114#define UVD0_BASE__INST6_SEG4 011151116#endif111711181119