Path: blob/master/drivers/gpu/drm/amd/include/renoir_ip_offset.h
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/*1* Copyright (C) 2019 Advanced Micro Devices, Inc.2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice shall be included11* in all copies or substantial portions of the Software.12*13* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS14* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,15* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL16* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN17* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN18* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.19*/20#ifndef _renoir_ip_offset_HEADER21#define _renoir_ip_offset_HEADER2223#define MAX_INSTANCE 724#define MAX_SEGMENT 5252627struct IP_BASE_INSTANCE {28unsigned int segment[MAX_SEGMENT];29};3031struct IP_BASE {32struct IP_BASE_INSTANCE instance[MAX_INSTANCE];33} __maybe_unused;343536static const struct IP_BASE ACP_BASE ={ { { { 0x02403800, 0x00480000, 0, 0, 0 } },37{ { 0, 0, 0, 0, 0 } },38{ { 0, 0, 0, 0, 0 } },39{ { 0, 0, 0, 0, 0 } },40{ { 0, 0, 0, 0, 0 } },41{ { 0, 0, 0, 0, 0 } },42{ { 0, 0, 0, 0, 0 } } } };43static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x02408C00, 0, 0, 0 } },44{ { 0, 0, 0, 0, 0 } },45{ { 0, 0, 0, 0, 0 } },46{ { 0, 0, 0, 0, 0 } },47{ { 0, 0, 0, 0, 0 } },48{ { 0, 0, 0, 0, 0 } },49{ { 0, 0, 0, 0, 0 } } } };50static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017E00, 0 } },51{ { 0, 0, 0, 0, 0 } },52{ { 0, 0, 0, 0, 0 } },53{ { 0, 0, 0, 0, 0 } },54{ { 0, 0, 0, 0, 0 } },55{ { 0, 0, 0, 0, 0 } },56{ { 0, 0, 0, 0, 0 } } } };57static const struct IP_BASE DBGU_IO0_BASE ={ { { { 0x000001E0, 0x0240B400, 0, 0, 0 } },58{ { 0, 0, 0, 0, 0 } },59{ { 0, 0, 0, 0, 0 } },60{ { 0, 0, 0, 0, 0 } },61{ { 0, 0, 0, 0, 0 } },62{ { 0, 0, 0, 0, 0 } },63{ { 0, 0, 0, 0, 0 } } } };64static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } },65{ { 0, 0, 0, 0, 0 } },66{ { 0, 0, 0, 0, 0 } },67{ { 0, 0, 0, 0, 0 } },68{ { 0, 0, 0, 0, 0 } },69{ { 0, 0, 0, 0, 0 } },70{ { 0, 0, 0, 0, 0 } } } };71static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } },72{ { 0, 0, 0, 0, 0 } },73{ { 0, 0, 0, 0, 0 } },74{ { 0, 0, 0, 0, 0 } },75{ { 0, 0, 0, 0, 0 } },76{ { 0, 0, 0, 0, 0 } },77{ { 0, 0, 0, 0, 0 } } } };78static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },79{ { 0, 0, 0, 0, 0 } },80{ { 0, 0, 0, 0, 0 } },81{ { 0, 0, 0, 0, 0 } },82{ { 0, 0, 0, 0, 0 } },83{ { 0, 0, 0, 0, 0 } },84{ { 0, 0, 0, 0, 0 } } } };85static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },86{ { 0, 0, 0, 0, 0 } },87{ { 0, 0, 0, 0, 0 } },88{ { 0, 0, 0, 0, 0 } },89{ { 0, 0, 0, 0, 0 } },90{ { 0, 0, 0, 0, 0 } },91{ { 0, 0, 0, 0, 0 } } } };92static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } },93{ { 0, 0, 0, 0, 0 } },94{ { 0, 0, 0, 0, 0 } },95{ { 0, 0, 0, 0, 0 } },96{ { 0, 0, 0, 0, 0 } },97{ { 0, 0, 0, 0, 0 } },98{ { 0, 0, 0, 0, 0 } } } };99static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0x02402C00, 0, 0 } },100{ { 0, 0, 0, 0, 0 } },101{ { 0, 0, 0, 0, 0 } },102{ { 0, 0, 0, 0, 0 } },103{ { 0, 0, 0, 0, 0 } },104{ { 0, 0, 0, 0, 0 } },105{ { 0, 0, 0, 0, 0 } } } };106static const struct IP_BASE HDA_BASE ={ { { { 0x02404800, 0x004C0000, 0, 0, 0 } },107{ { 0, 0, 0, 0, 0 } },108{ { 0, 0, 0, 0, 0 } },109{ { 0, 0, 0, 0, 0 } },110{ { 0, 0, 0, 0, 0 } },111{ { 0, 0, 0, 0, 0 } },112{ { 0, 0, 0, 0, 0 } } } };113static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },114{ { 0, 0, 0, 0, 0 } },115{ { 0, 0, 0, 0, 0 } },116{ { 0, 0, 0, 0, 0 } },117{ { 0, 0, 0, 0, 0 } },118{ { 0, 0, 0, 0, 0 } },119{ { 0, 0, 0, 0, 0 } } } };120static const struct IP_BASE IOHC0_BASE ={ { { { 0x00010000, 0x02406000, 0x04EC0000, 0, 0 } },121{ { 0, 0, 0, 0, 0 } },122{ { 0, 0, 0, 0, 0 } },123{ { 0, 0, 0, 0, 0 } },124{ { 0, 0, 0, 0, 0 } },125{ { 0, 0, 0, 0, 0 } },126{ { 0, 0, 0, 0, 0 } } } };127static const struct IP_BASE ISP_BASE ={ { { { 0x00018000, 0x0240B000, 0, 0, 0 } },128{ { 0, 0, 0, 0, 0 } },129{ { 0, 0, 0, 0, 0 } },130{ { 0, 0, 0, 0, 0 } },131{ { 0, 0, 0, 0, 0 } },132{ { 0, 0, 0, 0, 0 } },133{ { 0, 0, 0, 0, 0 } } } };134static const struct IP_BASE L2IMU0_BASE ={ { { { 0x00007DC0, 0x02407000, 0x00900000, 0x04FC0000, 0x055C0000 } },135{ { 0, 0, 0, 0, 0 } },136{ { 0, 0, 0, 0, 0 } },137{ { 0, 0, 0, 0, 0 } },138{ { 0, 0, 0, 0, 0 } },139{ { 0, 0, 0, 0, 0 } },140{ { 0, 0, 0, 0, 0 } } } };141static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } },142{ { 0, 0, 0, 0, 0 } },143{ { 0, 0, 0, 0, 0 } },144{ { 0, 0, 0, 0, 0 } },145{ { 0, 0, 0, 0, 0 } },146{ { 0, 0, 0, 0, 0 } },147{ { 0, 0, 0, 0, 0 } } } };148static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000 } },149{ { 0, 0, 0, 0, 0 } },150{ { 0, 0, 0, 0, 0 } },151{ { 0, 0, 0, 0, 0 } },152{ { 0, 0, 0, 0, 0 } },153{ { 0, 0, 0, 0, 0 } },154{ { 0, 0, 0, 0, 0 } } } };155static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x02400400, 0x00E80000, 0x00EC0000, 0x00F00000 } },156{ { 0, 0, 0, 0, 0 } },157{ { 0, 0, 0, 0, 0 } },158{ { 0, 0, 0, 0, 0 } },159{ { 0, 0, 0, 0, 0 } },160{ { 0, 0, 0, 0, 0 } },161{ { 0, 0, 0, 0, 0 } } } };162static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },163{ { 0, 0, 0, 0, 0 } },164{ { 0, 0, 0, 0, 0 } },165{ { 0, 0, 0, 0, 0 } },166{ { 0, 0, 0, 0, 0 } },167{ { 0, 0, 0, 0, 0 } },168{ { 0, 0, 0, 0, 0 } } } };169static const struct IP_BASE DCN_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },170{ { 0, 0, 0, 0, 0 } },171{ { 0, 0, 0, 0, 0 } },172{ { 0, 0, 0, 0, 0 } },173{ { 0, 0, 0, 0, 0 } } } };174static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } },175{ { 0, 0, 0, 0, 0 } },176{ { 0, 0, 0, 0, 0 } },177{ { 0, 0, 0, 0, 0 } },178{ { 0, 0, 0, 0, 0 } },179{ { 0, 0, 0, 0, 0 } },180{ { 0, 0, 0, 0, 0 } } } };181static const struct IP_BASE PCIE0_BASE ={ { { { 0x02411800, 0x04440000, 0, 0, 0 } },182{ { 0, 0, 0, 0, 0 } },183{ { 0, 0, 0, 0, 0 } },184{ { 0, 0, 0, 0, 0 } },185{ { 0, 0, 0, 0, 0 } },186{ { 0, 0, 0, 0, 0 } },187{ { 0, 0, 0, 0, 0 } } } };188static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x0240A800, 0, 0, 0 } },189{ { 0, 0, 0, 0, 0 } },190{ { 0, 0, 0, 0, 0 } },191{ { 0, 0, 0, 0, 0 } },192{ { 0, 0, 0, 0, 0 } },193{ { 0, 0, 0, 0, 0 } },194{ { 0, 0, 0, 0, 0 } } } };195static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0 } },196{ { 0, 0, 0, 0, 0 } },197{ { 0, 0, 0, 0, 0 } },198{ { 0, 0, 0, 0, 0 } },199{ { 0, 0, 0, 0, 0 } },200{ { 0, 0, 0, 0, 0 } },201{ { 0, 0, 0, 0, 0 } } } };202static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } },203{ { 0, 0, 0, 0, 0 } },204{ { 0, 0, 0, 0, 0 } },205{ { 0, 0, 0, 0, 0 } },206{ { 0, 0, 0, 0, 0 } },207{ { 0, 0, 0, 0, 0 } },208{ { 0, 0, 0, 0, 0 } } } };209static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } },210{ { 0x00054000, 0x02425C00, 0, 0, 0 } },211{ { 0, 0, 0, 0, 0 } },212{ { 0, 0, 0, 0, 0 } },213{ { 0, 0, 0, 0, 0 } },214{ { 0, 0, 0, 0, 0 } },215{ { 0, 0, 0, 0, 0 } } } };216static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } },217{ { 0, 0, 0, 0, 0 } },218{ { 0, 0, 0, 0, 0 } },219{ { 0, 0, 0, 0, 0 } },220{ { 0, 0, 0, 0, 0 } },221{ { 0, 0, 0, 0, 0 } },222{ { 0, 0, 0, 0, 0 } } } };223static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },224{ { 0, 0, 0, 0, 0 } },225{ { 0, 0, 0, 0, 0 } },226{ { 0, 0, 0, 0, 0 } },227{ { 0, 0, 0, 0, 0 } },228{ { 0, 0, 0, 0, 0 } },229{ { 0, 0, 0, 0, 0 } } } };230231232#define ACP_BASE__INST0_SEG0 0x02403800233#define ACP_BASE__INST0_SEG1 0x00480000234#define ACP_BASE__INST0_SEG2 0235#define ACP_BASE__INST0_SEG3 0236#define ACP_BASE__INST0_SEG4 0237238#define ACP_BASE__INST1_SEG0 0239#define ACP_BASE__INST1_SEG1 0240#define ACP_BASE__INST1_SEG2 0241#define ACP_BASE__INST1_SEG3 0242#define ACP_BASE__INST1_SEG4 0243244#define ACP_BASE__INST2_SEG0 0245#define ACP_BASE__INST2_SEG1 0246#define ACP_BASE__INST2_SEG2 0247#define ACP_BASE__INST2_SEG3 0248#define ACP_BASE__INST2_SEG4 0249250#define ACP_BASE__INST3_SEG0 0251#define ACP_BASE__INST3_SEG1 0252#define ACP_BASE__INST3_SEG2 0253#define ACP_BASE__INST3_SEG3 0254#define ACP_BASE__INST3_SEG4 0255256#define ACP_BASE__INST4_SEG0 0257#define ACP_BASE__INST4_SEG1 0258#define ACP_BASE__INST4_SEG2 0259#define ACP_BASE__INST4_SEG3 0260#define ACP_BASE__INST4_SEG4 0261262#define ACP_BASE__INST5_SEG0 0263#define ACP_BASE__INST5_SEG1 0264#define ACP_BASE__INST5_SEG2 0265#define ACP_BASE__INST5_SEG3 0266#define ACP_BASE__INST5_SEG4 0267268#define ACP_BASE__INST6_SEG0 0269#define ACP_BASE__INST6_SEG1 0270#define ACP_BASE__INST6_SEG2 0271#define ACP_BASE__INST6_SEG3 0272#define ACP_BASE__INST6_SEG4 0273274#define ATHUB_BASE__INST0_SEG0 0x00000C20275#define ATHUB_BASE__INST0_SEG1 0x02408C00276#define ATHUB_BASE__INST0_SEG2 0277#define ATHUB_BASE__INST0_SEG3 0278#define ATHUB_BASE__INST0_SEG4 0279280#define ATHUB_BASE__INST1_SEG0 0281#define ATHUB_BASE__INST1_SEG1 0282#define ATHUB_BASE__INST1_SEG2 0283#define ATHUB_BASE__INST1_SEG3 0284#define ATHUB_BASE__INST1_SEG4 0285286#define ATHUB_BASE__INST2_SEG0 0287#define ATHUB_BASE__INST2_SEG1 0288#define ATHUB_BASE__INST2_SEG2 0289#define ATHUB_BASE__INST2_SEG3 0290#define ATHUB_BASE__INST2_SEG4 0291292#define ATHUB_BASE__INST3_SEG0 0293#define ATHUB_BASE__INST3_SEG1 0294#define ATHUB_BASE__INST3_SEG2 0295#define ATHUB_BASE__INST3_SEG3 0296#define ATHUB_BASE__INST3_SEG4 0297298#define ATHUB_BASE__INST4_SEG0 0299#define ATHUB_BASE__INST4_SEG1 0300#define ATHUB_BASE__INST4_SEG2 0301#define ATHUB_BASE__INST4_SEG3 0302#define ATHUB_BASE__INST4_SEG4 0303304#define ATHUB_BASE__INST5_SEG0 0305#define ATHUB_BASE__INST5_SEG1 0306#define ATHUB_BASE__INST5_SEG2 0307#define ATHUB_BASE__INST5_SEG3 0308#define ATHUB_BASE__INST5_SEG4 0309310#define ATHUB_BASE__INST6_SEG0 0311#define ATHUB_BASE__INST6_SEG1 0312#define ATHUB_BASE__INST6_SEG2 0313#define ATHUB_BASE__INST6_SEG3 0314#define ATHUB_BASE__INST6_SEG4 0315316#define CLK_BASE__INST0_SEG0 0x00016C00317#define CLK_BASE__INST0_SEG1 0x00016E00318#define CLK_BASE__INST0_SEG2 0x00017000319#define CLK_BASE__INST0_SEG3 0x00017E00320#define CLK_BASE__INST0_SEG4 0321322#define CLK_BASE__INST1_SEG0 0323#define CLK_BASE__INST1_SEG1 0324#define CLK_BASE__INST1_SEG2 0325#define CLK_BASE__INST1_SEG3 0326#define CLK_BASE__INST1_SEG4 0327328#define CLK_BASE__INST2_SEG0 0329#define CLK_BASE__INST2_SEG1 0330#define CLK_BASE__INST2_SEG2 0331#define CLK_BASE__INST2_SEG3 0332#define CLK_BASE__INST2_SEG4 0333334#define CLK_BASE__INST3_SEG0 0335#define CLK_BASE__INST3_SEG1 0336#define CLK_BASE__INST3_SEG2 0337#define CLK_BASE__INST3_SEG3 0338#define CLK_BASE__INST3_SEG4 0339340#define CLK_BASE__INST4_SEG0 0341#define CLK_BASE__INST4_SEG1 0342#define CLK_BASE__INST4_SEG2 0343#define CLK_BASE__INST4_SEG3 0344#define CLK_BASE__INST4_SEG4 0345346#define CLK_BASE__INST5_SEG0 0347#define CLK_BASE__INST5_SEG1 0348#define CLK_BASE__INST5_SEG2 0349#define CLK_BASE__INST5_SEG3 0350#define CLK_BASE__INST5_SEG4 0351352#define CLK_BASE__INST6_SEG0 0353#define CLK_BASE__INST6_SEG1 0354#define CLK_BASE__INST6_SEG2 0355#define CLK_BASE__INST6_SEG3 0356#define CLK_BASE__INST6_SEG4 0357358#define DBGU_IO0_BASE__INST0_SEG0 0x000001E0359#define DBGU_IO0_BASE__INST0_SEG1 0x0240B400360#define DBGU_IO0_BASE__INST0_SEG2 0361#define DBGU_IO0_BASE__INST0_SEG3 0362#define DBGU_IO0_BASE__INST0_SEG4 0363364#define DBGU_IO0_BASE__INST1_SEG0 0365#define DBGU_IO0_BASE__INST1_SEG1 0366#define DBGU_IO0_BASE__INST1_SEG2 0367#define DBGU_IO0_BASE__INST1_SEG3 0368#define DBGU_IO0_BASE__INST1_SEG4 0369370#define DBGU_IO0_BASE__INST2_SEG0 0371#define DBGU_IO0_BASE__INST2_SEG1 0372#define DBGU_IO0_BASE__INST2_SEG2 0373#define DBGU_IO0_BASE__INST2_SEG3 0374#define DBGU_IO0_BASE__INST2_SEG4 0375376#define DBGU_IO0_BASE__INST3_SEG0 0377#define DBGU_IO0_BASE__INST3_SEG1 0378#define DBGU_IO0_BASE__INST3_SEG2 0379#define DBGU_IO0_BASE__INST3_SEG3 0380#define DBGU_IO0_BASE__INST3_SEG4 0381382#define DBGU_IO0_BASE__INST4_SEG0 0383#define DBGU_IO0_BASE__INST4_SEG1 0384#define DBGU_IO0_BASE__INST4_SEG2 0385#define DBGU_IO0_BASE__INST4_SEG3 0386#define DBGU_IO0_BASE__INST4_SEG4 0387388#define DBGU_IO0_BASE__INST5_SEG0 0389#define DBGU_IO0_BASE__INST5_SEG1 0390#define DBGU_IO0_BASE__INST5_SEG2 0391#define DBGU_IO0_BASE__INST5_SEG3 0392#define DBGU_IO0_BASE__INST5_SEG4 0393394#define DBGU_IO0_BASE__INST6_SEG0 0395#define DBGU_IO0_BASE__INST6_SEG1 0396#define DBGU_IO0_BASE__INST6_SEG2 0397#define DBGU_IO0_BASE__INST6_SEG3 0398#define DBGU_IO0_BASE__INST6_SEG4 0399400#define DF_BASE__INST0_SEG0 0x00007000401#define DF_BASE__INST0_SEG1 0x0240B800402#define DF_BASE__INST0_SEG2 0403#define DF_BASE__INST0_SEG3 0404#define DF_BASE__INST0_SEG4 0405406#define DF_BASE__INST1_SEG0 0407#define DF_BASE__INST1_SEG1 0408#define DF_BASE__INST1_SEG2 0409#define DF_BASE__INST1_SEG3 0410#define DF_BASE__INST1_SEG4 0411412#define DF_BASE__INST2_SEG0 0413#define DF_BASE__INST2_SEG1 0414#define DF_BASE__INST2_SEG2 0415#define DF_BASE__INST2_SEG3 0416#define DF_BASE__INST2_SEG4 0417418#define DF_BASE__INST3_SEG0 0419#define DF_BASE__INST3_SEG1 0420#define DF_BASE__INST3_SEG2 0421#define DF_BASE__INST3_SEG3 0422#define DF_BASE__INST3_SEG4 0423424#define DF_BASE__INST4_SEG0 0425#define DF_BASE__INST4_SEG1 0426#define DF_BASE__INST4_SEG2 0427#define DF_BASE__INST4_SEG3 0428#define DF_BASE__INST4_SEG4 0429430#define DF_BASE__INST5_SEG0 0431#define DF_BASE__INST5_SEG1 0432#define DF_BASE__INST5_SEG2 0433#define DF_BASE__INST5_SEG3 0434#define DF_BASE__INST5_SEG4 0435436#define DF_BASE__INST6_SEG0 0437#define DF_BASE__INST6_SEG1 0438#define DF_BASE__INST6_SEG2 0439#define DF_BASE__INST6_SEG3 0440#define DF_BASE__INST6_SEG4 0441442#define DIO_BASE__INST0_SEG0 0x02404000443#define DIO_BASE__INST0_SEG1 0444#define DIO_BASE__INST0_SEG2 0445#define DIO_BASE__INST0_SEG3 0446#define DIO_BASE__INST0_SEG4 0447448#define DIO_BASE__INST1_SEG0 0449#define DIO_BASE__INST1_SEG1 0450#define DIO_BASE__INST1_SEG2 0451#define DIO_BASE__INST1_SEG3 0452#define DIO_BASE__INST1_SEG4 0453454#define DIO_BASE__INST2_SEG0 0455#define DIO_BASE__INST2_SEG1 0456#define DIO_BASE__INST2_SEG2 0457#define DIO_BASE__INST2_SEG3 0458#define DIO_BASE__INST2_SEG4 0459460#define DIO_BASE__INST3_SEG0 0461#define DIO_BASE__INST3_SEG1 0462#define DIO_BASE__INST3_SEG2 0463#define DIO_BASE__INST3_SEG3 0464#define DIO_BASE__INST3_SEG4 0465466#define DIO_BASE__INST4_SEG0 0467#define DIO_BASE__INST4_SEG1 0468#define DIO_BASE__INST4_SEG2 0469#define DIO_BASE__INST4_SEG3 0470#define DIO_BASE__INST4_SEG4 0471472#define DIO_BASE__INST5_SEG0 0473#define DIO_BASE__INST5_SEG1 0474#define DIO_BASE__INST5_SEG2 0475#define DIO_BASE__INST5_SEG3 0476#define DIO_BASE__INST5_SEG4 0477478#define DIO_BASE__INST6_SEG0 0479#define DIO_BASE__INST6_SEG1 0480#define DIO_BASE__INST6_SEG2 0481#define DIO_BASE__INST6_SEG3 0482#define DIO_BASE__INST6_SEG4 0483484#define DMU_BASE__INST0_SEG0 0x00000012485#define DMU_BASE__INST0_SEG1 0x000000C0486#define DMU_BASE__INST0_SEG2 0x000034C0487#define DMU_BASE__INST0_SEG3 0x00009000488#define DMU_BASE__INST0_SEG4 0x02403C00489490#define DMU_BASE__INST1_SEG0 0491#define DMU_BASE__INST1_SEG1 0492#define DMU_BASE__INST1_SEG2 0493#define DMU_BASE__INST1_SEG3 0494#define DMU_BASE__INST1_SEG4 0495496#define DMU_BASE__INST2_SEG0 0497#define DMU_BASE__INST2_SEG1 0498#define DMU_BASE__INST2_SEG2 0499#define DMU_BASE__INST2_SEG3 0500#define DMU_BASE__INST2_SEG4 0501502#define DMU_BASE__INST3_SEG0 0503#define DMU_BASE__INST3_SEG1 0504#define DMU_BASE__INST3_SEG2 0505#define DMU_BASE__INST3_SEG3 0506#define DMU_BASE__INST3_SEG4 0507508#define DMU_BASE__INST4_SEG0 0509#define DMU_BASE__INST4_SEG1 0510#define DMU_BASE__INST4_SEG2 0511#define DMU_BASE__INST4_SEG3 0512#define DMU_BASE__INST4_SEG4 0513514#define DMU_BASE__INST5_SEG0 0515#define DMU_BASE__INST5_SEG1 0516#define DMU_BASE__INST5_SEG2 0517#define DMU_BASE__INST5_SEG3 0518#define DMU_BASE__INST5_SEG4 0519520#define DMU_BASE__INST6_SEG0 0521#define DMU_BASE__INST6_SEG1 0522#define DMU_BASE__INST6_SEG2 0523#define DMU_BASE__INST6_SEG3 0524#define DMU_BASE__INST6_SEG4 0525526#define DPCS_BASE__INST0_SEG0 0x00000012527#define DPCS_BASE__INST0_SEG1 0x000000C0528#define DPCS_BASE__INST0_SEG2 0x000034C0529#define DPCS_BASE__INST0_SEG3 0x00009000530#define DPCS_BASE__INST0_SEG4 0x02403C00531532#define DPCS_BASE__INST1_SEG0 0533#define DPCS_BASE__INST1_SEG1 0534#define DPCS_BASE__INST1_SEG2 0535#define DPCS_BASE__INST1_SEG3 0536#define DPCS_BASE__INST1_SEG4 0537538#define DPCS_BASE__INST2_SEG0 0539#define DPCS_BASE__INST2_SEG1 0540#define DPCS_BASE__INST2_SEG2 0541#define DPCS_BASE__INST2_SEG3 0542#define DPCS_BASE__INST2_SEG4 0543544#define DPCS_BASE__INST3_SEG0 0545#define DPCS_BASE__INST3_SEG1 0546#define DPCS_BASE__INST3_SEG2 0547#define DPCS_BASE__INST3_SEG3 0548#define DPCS_BASE__INST3_SEG4 0549550#define DPCS_BASE__INST4_SEG0 0551#define DPCS_BASE__INST4_SEG1 0552#define DPCS_BASE__INST4_SEG2 0553#define DPCS_BASE__INST4_SEG3 0554#define DPCS_BASE__INST4_SEG4 0555556#define DPCS_BASE__INST5_SEG0 0557#define DPCS_BASE__INST5_SEG1 0558#define DPCS_BASE__INST5_SEG2 0559#define DPCS_BASE__INST5_SEG3 0560#define DPCS_BASE__INST5_SEG4 0561562#define DPCS_BASE__INST6_SEG0 0563#define DPCS_BASE__INST6_SEG1 0564#define DPCS_BASE__INST6_SEG2 0565#define DPCS_BASE__INST6_SEG3 0566#define DPCS_BASE__INST6_SEG4 0567568#define FUSE_BASE__INST0_SEG0 0x00017400569#define FUSE_BASE__INST0_SEG1 0x02401400570#define FUSE_BASE__INST0_SEG2 0571#define FUSE_BASE__INST0_SEG3 0572#define FUSE_BASE__INST0_SEG4 0573574#define FUSE_BASE__INST1_SEG0 0575#define FUSE_BASE__INST1_SEG1 0576#define FUSE_BASE__INST1_SEG2 0577#define FUSE_BASE__INST1_SEG3 0578#define FUSE_BASE__INST1_SEG4 0579580#define FUSE_BASE__INST2_SEG0 0581#define FUSE_BASE__INST2_SEG1 0582#define FUSE_BASE__INST2_SEG2 0583#define FUSE_BASE__INST2_SEG3 0584#define FUSE_BASE__INST2_SEG4 0585586#define FUSE_BASE__INST3_SEG0 0587#define FUSE_BASE__INST3_SEG1 0588#define FUSE_BASE__INST3_SEG2 0589#define FUSE_BASE__INST3_SEG3 0590#define FUSE_BASE__INST3_SEG4 0591592#define FUSE_BASE__INST4_SEG0 0593#define FUSE_BASE__INST4_SEG1 0594#define FUSE_BASE__INST4_SEG2 0595#define FUSE_BASE__INST4_SEG3 0596#define FUSE_BASE__INST4_SEG4 0597598#define FUSE_BASE__INST5_SEG0 0599#define FUSE_BASE__INST5_SEG1 0600#define FUSE_BASE__INST5_SEG2 0601#define FUSE_BASE__INST5_SEG3 0602#define FUSE_BASE__INST5_SEG4 0603604#define FUSE_BASE__INST6_SEG0 0605#define FUSE_BASE__INST6_SEG1 0606#define FUSE_BASE__INST6_SEG2 0607#define FUSE_BASE__INST6_SEG3 0608#define FUSE_BASE__INST6_SEG4 0609610#define GC_BASE__INST0_SEG0 0x00002000611#define GC_BASE__INST0_SEG1 0x0000A000612#define GC_BASE__INST0_SEG2 0x02402C00613#define GC_BASE__INST0_SEG3 0614#define GC_BASE__INST0_SEG4 0615616#define GC_BASE__INST1_SEG0 0617#define GC_BASE__INST1_SEG1 0618#define GC_BASE__INST1_SEG2 0619#define GC_BASE__INST1_SEG3 0620#define GC_BASE__INST1_SEG4 0621622#define GC_BASE__INST2_SEG0 0623#define GC_BASE__INST2_SEG1 0624#define GC_BASE__INST2_SEG2 0625#define GC_BASE__INST2_SEG3 0626#define GC_BASE__INST2_SEG4 0627628#define GC_BASE__INST3_SEG0 0629#define GC_BASE__INST3_SEG1 0630#define GC_BASE__INST3_SEG2 0631#define GC_BASE__INST3_SEG3 0632#define GC_BASE__INST3_SEG4 0633634#define GC_BASE__INST4_SEG0 0635#define GC_BASE__INST4_SEG1 0636#define GC_BASE__INST4_SEG2 0637#define GC_BASE__INST4_SEG3 0638#define GC_BASE__INST4_SEG4 0639640#define GC_BASE__INST5_SEG0 0641#define GC_BASE__INST5_SEG1 0642#define GC_BASE__INST5_SEG2 0643#define GC_BASE__INST5_SEG3 0644#define GC_BASE__INST5_SEG4 0645646#define GC_BASE__INST6_SEG0 0647#define GC_BASE__INST6_SEG1 0648#define GC_BASE__INST6_SEG2 0649#define GC_BASE__INST6_SEG3 0650#define GC_BASE__INST6_SEG4 0651652#define HDA_BASE__INST0_SEG0 0x02404800653#define HDA_BASE__INST0_SEG1 0x004C0000654#define HDA_BASE__INST0_SEG2 0655#define HDA_BASE__INST0_SEG3 0656#define HDA_BASE__INST0_SEG4 0657658#define HDA_BASE__INST1_SEG0 0659#define HDA_BASE__INST1_SEG1 0660#define HDA_BASE__INST1_SEG2 0661#define HDA_BASE__INST1_SEG3 0662#define HDA_BASE__INST1_SEG4 0663664#define HDA_BASE__INST2_SEG0 0665#define HDA_BASE__INST2_SEG1 0666#define HDA_BASE__INST2_SEG2 0667#define HDA_BASE__INST2_SEG3 0668#define HDA_BASE__INST2_SEG4 0669670#define HDA_BASE__INST3_SEG0 0671#define HDA_BASE__INST3_SEG1 0672#define HDA_BASE__INST3_SEG2 0673#define HDA_BASE__INST3_SEG3 0674#define HDA_BASE__INST3_SEG4 0675676#define HDA_BASE__INST4_SEG0 0677#define HDA_BASE__INST4_SEG1 0678#define HDA_BASE__INST4_SEG2 0679#define HDA_BASE__INST4_SEG3 0680#define HDA_BASE__INST4_SEG4 0681682#define HDA_BASE__INST5_SEG0 0683#define HDA_BASE__INST5_SEG1 0684#define HDA_BASE__INST5_SEG2 0685#define HDA_BASE__INST5_SEG3 0686#define HDA_BASE__INST5_SEG4 0687688#define HDA_BASE__INST6_SEG0 0689#define HDA_BASE__INST6_SEG1 0690#define HDA_BASE__INST6_SEG2 0691#define HDA_BASE__INST6_SEG3 0692#define HDA_BASE__INST6_SEG4 0693694#define HDP_BASE__INST0_SEG0 0x00000F20695#define HDP_BASE__INST0_SEG1 0x0240A400696#define HDP_BASE__INST0_SEG2 0697#define HDP_BASE__INST0_SEG3 0698#define HDP_BASE__INST0_SEG4 0699700#define HDP_BASE__INST1_SEG0 0701#define HDP_BASE__INST1_SEG1 0702#define HDP_BASE__INST1_SEG2 0703#define HDP_BASE__INST1_SEG3 0704#define HDP_BASE__INST1_SEG4 0705706#define HDP_BASE__INST2_SEG0 0707#define HDP_BASE__INST2_SEG1 0708#define HDP_BASE__INST2_SEG2 0709#define HDP_BASE__INST2_SEG3 0710#define HDP_BASE__INST2_SEG4 0711712#define HDP_BASE__INST3_SEG0 0713#define HDP_BASE__INST3_SEG1 0714#define HDP_BASE__INST3_SEG2 0715#define HDP_BASE__INST3_SEG3 0716#define HDP_BASE__INST3_SEG4 0717718#define HDP_BASE__INST4_SEG0 0719#define HDP_BASE__INST4_SEG1 0720#define HDP_BASE__INST4_SEG2 0721#define HDP_BASE__INST4_SEG3 0722#define HDP_BASE__INST4_SEG4 0723724#define HDP_BASE__INST5_SEG0 0725#define HDP_BASE__INST5_SEG1 0726#define HDP_BASE__INST5_SEG2 0727#define HDP_BASE__INST5_SEG3 0728#define HDP_BASE__INST5_SEG4 0729730#define HDP_BASE__INST6_SEG0 0731#define HDP_BASE__INST6_SEG1 0732#define HDP_BASE__INST6_SEG2 0733#define HDP_BASE__INST6_SEG3 0734#define HDP_BASE__INST6_SEG4 0735736#define IOHC0_BASE__INST0_SEG0 0x00010000737#define IOHC0_BASE__INST0_SEG1 0x02406000738#define IOHC0_BASE__INST0_SEG2 0x04EC0000739#define IOHC0_BASE__INST0_SEG3 0740#define IOHC0_BASE__INST0_SEG4 0741742#define IOHC0_BASE__INST1_SEG0 0743#define IOHC0_BASE__INST1_SEG1 0744#define IOHC0_BASE__INST1_SEG2 0745#define IOHC0_BASE__INST1_SEG3 0746#define IOHC0_BASE__INST1_SEG4 0747748#define IOHC0_BASE__INST2_SEG0 0749#define IOHC0_BASE__INST2_SEG1 0750#define IOHC0_BASE__INST2_SEG2 0751#define IOHC0_BASE__INST2_SEG3 0752#define IOHC0_BASE__INST2_SEG4 0753754#define IOHC0_BASE__INST3_SEG0 0755#define IOHC0_BASE__INST3_SEG1 0756#define IOHC0_BASE__INST3_SEG2 0757#define IOHC0_BASE__INST3_SEG3 0758#define IOHC0_BASE__INST3_SEG4 0759760#define IOHC0_BASE__INST4_SEG0 0761#define IOHC0_BASE__INST4_SEG1 0762#define IOHC0_BASE__INST4_SEG2 0763#define IOHC0_BASE__INST4_SEG3 0764#define IOHC0_BASE__INST4_SEG4 0765766#define IOHC0_BASE__INST5_SEG0 0767#define IOHC0_BASE__INST5_SEG1 0768#define IOHC0_BASE__INST5_SEG2 0769#define IOHC0_BASE__INST5_SEG3 0770#define IOHC0_BASE__INST5_SEG4 0771772#define IOHC0_BASE__INST6_SEG0 0773#define IOHC0_BASE__INST6_SEG1 0774#define IOHC0_BASE__INST6_SEG2 0775#define IOHC0_BASE__INST6_SEG3 0776#define IOHC0_BASE__INST6_SEG4 0777778#define ISP_BASE__INST0_SEG0 0x00018000779#define ISP_BASE__INST0_SEG1 0x0240B000780#define ISP_BASE__INST0_SEG2 0781#define ISP_BASE__INST0_SEG3 0782#define ISP_BASE__INST0_SEG4 0783784#define ISP_BASE__INST1_SEG0 0785#define ISP_BASE__INST1_SEG1 0786#define ISP_BASE__INST1_SEG2 0787#define ISP_BASE__INST1_SEG3 0788#define ISP_BASE__INST1_SEG4 0789790#define ISP_BASE__INST2_SEG0 0791#define ISP_BASE__INST2_SEG1 0792#define ISP_BASE__INST2_SEG2 0793#define ISP_BASE__INST2_SEG3 0794#define ISP_BASE__INST2_SEG4 0795796#define ISP_BASE__INST3_SEG0 0797#define ISP_BASE__INST3_SEG1 0798#define ISP_BASE__INST3_SEG2 0799#define ISP_BASE__INST3_SEG3 0800#define ISP_BASE__INST3_SEG4 0801802#define ISP_BASE__INST4_SEG0 0803#define ISP_BASE__INST4_SEG1 0804#define ISP_BASE__INST4_SEG2 0805#define ISP_BASE__INST4_SEG3 0806#define ISP_BASE__INST4_SEG4 0807808#define ISP_BASE__INST5_SEG0 0809#define ISP_BASE__INST5_SEG1 0810#define ISP_BASE__INST5_SEG2 0811#define ISP_BASE__INST5_SEG3 0812#define ISP_BASE__INST5_SEG4 0813814#define ISP_BASE__INST6_SEG0 0815#define ISP_BASE__INST6_SEG1 0816#define ISP_BASE__INST6_SEG2 0817#define ISP_BASE__INST6_SEG3 0818#define ISP_BASE__INST6_SEG4 0819820#define L2IMU0_BASE__INST0_SEG0 0x00007DC0821#define L2IMU0_BASE__INST0_SEG1 0x02407000822#define L2IMU0_BASE__INST0_SEG2 0x00900000823#define L2IMU0_BASE__INST0_SEG3 0x04FC0000824#define L2IMU0_BASE__INST0_SEG4 0x055C0000825826#define L2IMU0_BASE__INST1_SEG0 0827#define L2IMU0_BASE__INST1_SEG1 0828#define L2IMU0_BASE__INST1_SEG2 0829#define L2IMU0_BASE__INST1_SEG3 0830#define L2IMU0_BASE__INST1_SEG4 0831832#define L2IMU0_BASE__INST2_SEG0 0833#define L2IMU0_BASE__INST2_SEG1 0834#define L2IMU0_BASE__INST2_SEG2 0835#define L2IMU0_BASE__INST2_SEG3 0836#define L2IMU0_BASE__INST2_SEG4 0837838#define L2IMU0_BASE__INST3_SEG0 0839#define L2IMU0_BASE__INST3_SEG1 0840#define L2IMU0_BASE__INST3_SEG2 0841#define L2IMU0_BASE__INST3_SEG3 0842#define L2IMU0_BASE__INST3_SEG4 0843844#define L2IMU0_BASE__INST4_SEG0 0845#define L2IMU0_BASE__INST4_SEG1 0846#define L2IMU0_BASE__INST4_SEG2 0847#define L2IMU0_BASE__INST4_SEG3 0848#define L2IMU0_BASE__INST4_SEG4 0849850#define L2IMU0_BASE__INST5_SEG0 0851#define L2IMU0_BASE__INST5_SEG1 0852#define L2IMU0_BASE__INST5_SEG2 0853#define L2IMU0_BASE__INST5_SEG3 0854#define L2IMU0_BASE__INST5_SEG4 0855856#define L2IMU0_BASE__INST6_SEG0 0857#define L2IMU0_BASE__INST6_SEG1 0858#define L2IMU0_BASE__INST6_SEG2 0859#define L2IMU0_BASE__INST6_SEG3 0860#define L2IMU0_BASE__INST6_SEG4 0861862#define MMHUB_BASE__INST0_SEG0 0x0001A000863#define MMHUB_BASE__INST0_SEG1 0x02408800864#define MMHUB_BASE__INST0_SEG2 0865#define MMHUB_BASE__INST0_SEG3 0866#define MMHUB_BASE__INST0_SEG4 0867868#define MMHUB_BASE__INST1_SEG0 0869#define MMHUB_BASE__INST1_SEG1 0870#define MMHUB_BASE__INST1_SEG2 0871#define MMHUB_BASE__INST1_SEG3 0872#define MMHUB_BASE__INST1_SEG4 0873874#define MMHUB_BASE__INST2_SEG0 0875#define MMHUB_BASE__INST2_SEG1 0876#define MMHUB_BASE__INST2_SEG2 0877#define MMHUB_BASE__INST2_SEG3 0878#define MMHUB_BASE__INST2_SEG4 0879880#define MMHUB_BASE__INST3_SEG0 0881#define MMHUB_BASE__INST3_SEG1 0882#define MMHUB_BASE__INST3_SEG2 0883#define MMHUB_BASE__INST3_SEG3 0884#define MMHUB_BASE__INST3_SEG4 0885886#define MMHUB_BASE__INST4_SEG0 0887#define MMHUB_BASE__INST4_SEG1 0888#define MMHUB_BASE__INST4_SEG2 0889#define MMHUB_BASE__INST4_SEG3 0890#define MMHUB_BASE__INST4_SEG4 0891892#define MMHUB_BASE__INST5_SEG0 0893#define MMHUB_BASE__INST5_SEG1 0894#define MMHUB_BASE__INST5_SEG2 0895#define MMHUB_BASE__INST5_SEG3 0896#define MMHUB_BASE__INST5_SEG4 0897898#define MMHUB_BASE__INST6_SEG0 0899#define MMHUB_BASE__INST6_SEG1 0900#define MMHUB_BASE__INST6_SEG2 0901#define MMHUB_BASE__INST6_SEG3 0902#define MMHUB_BASE__INST6_SEG4 0903904#define MP0_BASE__INST0_SEG0 0x00016000905#define MP0_BASE__INST0_SEG1 0x0243FC00906#define MP0_BASE__INST0_SEG2 0x00DC0000907#define MP0_BASE__INST0_SEG3 0x00E00000908#define MP0_BASE__INST0_SEG4 0x00E40000909910#define MP0_BASE__INST1_SEG0 0911#define MP0_BASE__INST1_SEG1 0912#define MP0_BASE__INST1_SEG2 0913#define MP0_BASE__INST1_SEG3 0914#define MP0_BASE__INST1_SEG4 0915916#define MP0_BASE__INST2_SEG0 0917#define MP0_BASE__INST2_SEG1 0918#define MP0_BASE__INST2_SEG2 0919#define MP0_BASE__INST2_SEG3 0920#define MP0_BASE__INST2_SEG4 0921922#define MP0_BASE__INST3_SEG0 0923#define MP0_BASE__INST3_SEG1 0924#define MP0_BASE__INST3_SEG2 0925#define MP0_BASE__INST3_SEG3 0926#define MP0_BASE__INST3_SEG4 0927928#define MP0_BASE__INST4_SEG0 0929#define MP0_BASE__INST4_SEG1 0930#define MP0_BASE__INST4_SEG2 0931#define MP0_BASE__INST4_SEG3 0932#define MP0_BASE__INST4_SEG4 0933934#define MP0_BASE__INST5_SEG0 0935#define MP0_BASE__INST5_SEG1 0936#define MP0_BASE__INST5_SEG2 0937#define MP0_BASE__INST5_SEG3 0938#define MP0_BASE__INST5_SEG4 0939940#define MP0_BASE__INST6_SEG0 0941#define MP0_BASE__INST6_SEG1 0942#define MP0_BASE__INST6_SEG2 0943#define MP0_BASE__INST6_SEG3 0944#define MP0_BASE__INST6_SEG4 0945946#define MP1_BASE__INST0_SEG0 0x00016200947#define MP1_BASE__INST0_SEG1 0x02400400948#define MP1_BASE__INST0_SEG2 0x00E80000949#define MP1_BASE__INST0_SEG3 0x00EC0000950#define MP1_BASE__INST0_SEG4 0x00F00000951952#define MP1_BASE__INST1_SEG0 0953#define MP1_BASE__INST1_SEG1 0954#define MP1_BASE__INST1_SEG2 0955#define MP1_BASE__INST1_SEG3 0956#define MP1_BASE__INST1_SEG4 0957958#define MP1_BASE__INST2_SEG0 0959#define MP1_BASE__INST2_SEG1 0960#define MP1_BASE__INST2_SEG2 0961#define MP1_BASE__INST2_SEG3 0962#define MP1_BASE__INST2_SEG4 0963964#define MP1_BASE__INST3_SEG0 0965#define MP1_BASE__INST3_SEG1 0966#define MP1_BASE__INST3_SEG2 0967#define MP1_BASE__INST3_SEG3 0968#define MP1_BASE__INST3_SEG4 0969970#define MP1_BASE__INST4_SEG0 0971#define MP1_BASE__INST4_SEG1 0972#define MP1_BASE__INST4_SEG2 0973#define MP1_BASE__INST4_SEG3 0974#define MP1_BASE__INST4_SEG4 0975976#define MP1_BASE__INST5_SEG0 0977#define MP1_BASE__INST5_SEG1 0978#define MP1_BASE__INST5_SEG2 0979#define MP1_BASE__INST5_SEG3 0980#define MP1_BASE__INST5_SEG4 0981982#define MP1_BASE__INST6_SEG0 0983#define MP1_BASE__INST6_SEG1 0984#define MP1_BASE__INST6_SEG2 0985#define MP1_BASE__INST6_SEG3 0986#define MP1_BASE__INST6_SEG4 0987988#define NBIF0_BASE__INST0_SEG0 0x00000000989#define NBIF0_BASE__INST0_SEG1 0x00000014990#define NBIF0_BASE__INST0_SEG2 0x00000D20991#define NBIF0_BASE__INST0_SEG3 0x00010400992#define NBIF0_BASE__INST0_SEG4 0x0241B000993994#define NBIF0_BASE__INST1_SEG0 0995#define NBIF0_BASE__INST1_SEG1 0996#define NBIF0_BASE__INST1_SEG2 0997#define NBIF0_BASE__INST1_SEG3 0998#define NBIF0_BASE__INST1_SEG4 09991000#define NBIF0_BASE__INST2_SEG0 01001#define NBIF0_BASE__INST2_SEG1 01002#define NBIF0_BASE__INST2_SEG2 01003#define NBIF0_BASE__INST2_SEG3 01004#define NBIF0_BASE__INST2_SEG4 010051006#define NBIF0_BASE__INST3_SEG0 01007#define NBIF0_BASE__INST3_SEG1 01008#define NBIF0_BASE__INST3_SEG2 01009#define NBIF0_BASE__INST3_SEG3 01010#define NBIF0_BASE__INST3_SEG4 010111012#define NBIF0_BASE__INST4_SEG0 01013#define NBIF0_BASE__INST4_SEG1 01014#define NBIF0_BASE__INST4_SEG2 01015#define NBIF0_BASE__INST4_SEG3 01016#define NBIF0_BASE__INST4_SEG4 010171018#define NBIF0_BASE__INST5_SEG0 01019#define NBIF0_BASE__INST5_SEG1 01020#define NBIF0_BASE__INST5_SEG2 01021#define NBIF0_BASE__INST5_SEG3 01022#define NBIF0_BASE__INST5_SEG4 010231024#define NBIF0_BASE__INST6_SEG0 01025#define NBIF0_BASE__INST6_SEG1 01026#define NBIF0_BASE__INST6_SEG2 01027#define NBIF0_BASE__INST6_SEG3 01028#define NBIF0_BASE__INST6_SEG4 010291030#define OSSSYS_BASE__INST0_SEG0 0x000010A01031#define OSSSYS_BASE__INST0_SEG1 0x0240A0001032#define OSSSYS_BASE__INST0_SEG2 01033#define OSSSYS_BASE__INST0_SEG3 01034#define OSSSYS_BASE__INST0_SEG4 010351036#define OSSSYS_BASE__INST1_SEG0 01037#define OSSSYS_BASE__INST1_SEG1 01038#define OSSSYS_BASE__INST1_SEG2 01039#define OSSSYS_BASE__INST1_SEG3 01040#define OSSSYS_BASE__INST1_SEG4 010411042#define OSSSYS_BASE__INST2_SEG0 01043#define OSSSYS_BASE__INST2_SEG1 01044#define OSSSYS_BASE__INST2_SEG2 01045#define OSSSYS_BASE__INST2_SEG3 01046#define OSSSYS_BASE__INST2_SEG4 010471048#define OSSSYS_BASE__INST3_SEG0 01049#define OSSSYS_BASE__INST3_SEG1 01050#define OSSSYS_BASE__INST3_SEG2 01051#define OSSSYS_BASE__INST3_SEG3 01052#define OSSSYS_BASE__INST3_SEG4 010531054#define OSSSYS_BASE__INST4_SEG0 01055#define OSSSYS_BASE__INST4_SEG1 01056#define OSSSYS_BASE__INST4_SEG2 01057#define OSSSYS_BASE__INST4_SEG3 01058#define OSSSYS_BASE__INST4_SEG4 010591060#define OSSSYS_BASE__INST5_SEG0 01061#define OSSSYS_BASE__INST5_SEG1 01062#define OSSSYS_BASE__INST5_SEG2 01063#define OSSSYS_BASE__INST5_SEG3 01064#define OSSSYS_BASE__INST5_SEG4 010651066#define OSSSYS_BASE__INST6_SEG0 01067#define OSSSYS_BASE__INST6_SEG1 01068#define OSSSYS_BASE__INST6_SEG2 01069#define OSSSYS_BASE__INST6_SEG3 01070#define OSSSYS_BASE__INST6_SEG4 010711072#define PCIE0_BASE__INST0_SEG0 0x024118001073#define PCIE0_BASE__INST0_SEG1 0x044400001074#define PCIE0_BASE__INST0_SEG2 01075#define PCIE0_BASE__INST0_SEG3 01076#define PCIE0_BASE__INST0_SEG4 010771078#define PCIE0_BASE__INST1_SEG0 01079#define PCIE0_BASE__INST1_SEG1 01080#define PCIE0_BASE__INST1_SEG2 01081#define PCIE0_BASE__INST1_SEG3 01082#define PCIE0_BASE__INST1_SEG4 010831084#define PCIE0_BASE__INST2_SEG0 01085#define PCIE0_BASE__INST2_SEG1 01086#define PCIE0_BASE__INST2_SEG2 01087#define PCIE0_BASE__INST2_SEG3 01088#define PCIE0_BASE__INST2_SEG4 010891090#define PCIE0_BASE__INST3_SEG0 01091#define PCIE0_BASE__INST3_SEG1 01092#define PCIE0_BASE__INST3_SEG2 01093#define PCIE0_BASE__INST3_SEG3 01094#define PCIE0_BASE__INST3_SEG4 010951096#define PCIE0_BASE__INST4_SEG0 01097#define PCIE0_BASE__INST4_SEG1 01098#define PCIE0_BASE__INST4_SEG2 01099#define PCIE0_BASE__INST4_SEG3 01100#define PCIE0_BASE__INST4_SEG4 011011102#define PCIE0_BASE__INST5_SEG0 01103#define PCIE0_BASE__INST5_SEG1 01104#define PCIE0_BASE__INST5_SEG2 01105#define PCIE0_BASE__INST5_SEG3 01106#define PCIE0_BASE__INST5_SEG4 011071108#define PCIE0_BASE__INST6_SEG0 01109#define PCIE0_BASE__INST6_SEG1 01110#define PCIE0_BASE__INST6_SEG2 01111#define PCIE0_BASE__INST6_SEG3 01112#define PCIE0_BASE__INST6_SEG4 011131114#define SDMA0_BASE__INST0_SEG0 0x000012601115#define SDMA0_BASE__INST0_SEG1 0x0240A8001116#define SDMA0_BASE__INST0_SEG2 01117#define SDMA0_BASE__INST0_SEG3 01118#define SDMA0_BASE__INST0_SEG4 011191120#define SDMA0_BASE__INST1_SEG0 01121#define SDMA0_BASE__INST1_SEG1 01122#define SDMA0_BASE__INST1_SEG2 01123#define SDMA0_BASE__INST1_SEG3 01124#define SDMA0_BASE__INST1_SEG4 011251126#define SDMA0_BASE__INST2_SEG0 01127#define SDMA0_BASE__INST2_SEG1 01128#define SDMA0_BASE__INST2_SEG2 01129#define SDMA0_BASE__INST2_SEG3 01130#define SDMA0_BASE__INST2_SEG4 011311132#define SDMA0_BASE__INST3_SEG0 01133#define SDMA0_BASE__INST3_SEG1 01134#define SDMA0_BASE__INST3_SEG2 01135#define SDMA0_BASE__INST3_SEG3 01136#define SDMA0_BASE__INST3_SEG4 011371138#define SDMA0_BASE__INST4_SEG0 01139#define SDMA0_BASE__INST4_SEG1 01140#define SDMA0_BASE__INST4_SEG2 01141#define SDMA0_BASE__INST4_SEG3 01142#define SDMA0_BASE__INST4_SEG4 011431144#define SDMA0_BASE__INST5_SEG0 01145#define SDMA0_BASE__INST5_SEG1 01146#define SDMA0_BASE__INST5_SEG2 01147#define SDMA0_BASE__INST5_SEG3 01148#define SDMA0_BASE__INST5_SEG4 011491150#define SDMA0_BASE__INST6_SEG0 01151#define SDMA0_BASE__INST6_SEG1 01152#define SDMA0_BASE__INST6_SEG2 01153#define SDMA0_BASE__INST6_SEG3 01154#define SDMA0_BASE__INST6_SEG4 011551156#define SMUIO_BASE__INST0_SEG0 0x000168001157#define SMUIO_BASE__INST0_SEG1 0x00016A001158#define SMUIO_BASE__INST0_SEG2 0x024010001159#define SMUIO_BASE__INST0_SEG3 0x004400001160#define SMUIO_BASE__INST0_SEG4 011611162#define SMUIO_BASE__INST1_SEG0 01163#define SMUIO_BASE__INST1_SEG1 01164#define SMUIO_BASE__INST1_SEG2 01165#define SMUIO_BASE__INST1_SEG3 01166#define SMUIO_BASE__INST1_SEG4 011671168#define SMUIO_BASE__INST2_SEG0 01169#define SMUIO_BASE__INST2_SEG1 01170#define SMUIO_BASE__INST2_SEG2 01171#define SMUIO_BASE__INST2_SEG3 01172#define SMUIO_BASE__INST2_SEG4 011731174#define SMUIO_BASE__INST3_SEG0 01175#define SMUIO_BASE__INST3_SEG1 01176#define SMUIO_BASE__INST3_SEG2 01177#define SMUIO_BASE__INST3_SEG3 01178#define SMUIO_BASE__INST3_SEG4 011791180#define SMUIO_BASE__INST4_SEG0 01181#define SMUIO_BASE__INST4_SEG1 01182#define SMUIO_BASE__INST4_SEG2 01183#define SMUIO_BASE__INST4_SEG3 01184#define SMUIO_BASE__INST4_SEG4 011851186#define SMUIO_BASE__INST5_SEG0 01187#define SMUIO_BASE__INST5_SEG1 01188#define SMUIO_BASE__INST5_SEG2 01189#define SMUIO_BASE__INST5_SEG3 01190#define SMUIO_BASE__INST5_SEG4 011911192#define SMUIO_BASE__INST6_SEG0 01193#define SMUIO_BASE__INST6_SEG1 01194#define SMUIO_BASE__INST6_SEG2 01195#define SMUIO_BASE__INST6_SEG3 01196#define SMUIO_BASE__INST6_SEG4 011971198#define THM_BASE__INST0_SEG0 0x000166001199#define THM_BASE__INST0_SEG1 0x02400C001200#define THM_BASE__INST0_SEG2 01201#define THM_BASE__INST0_SEG3 01202#define THM_BASE__INST0_SEG4 012031204#define THM_BASE__INST1_SEG0 01205#define THM_BASE__INST1_SEG1 01206#define THM_BASE__INST1_SEG2 01207#define THM_BASE__INST1_SEG3 01208#define THM_BASE__INST1_SEG4 012091210#define THM_BASE__INST2_SEG0 01211#define THM_BASE__INST2_SEG1 01212#define THM_BASE__INST2_SEG2 01213#define THM_BASE__INST2_SEG3 01214#define THM_BASE__INST2_SEG4 012151216#define THM_BASE__INST3_SEG0 01217#define THM_BASE__INST3_SEG1 01218#define THM_BASE__INST3_SEG2 01219#define THM_BASE__INST3_SEG3 01220#define THM_BASE__INST3_SEG4 012211222#define THM_BASE__INST4_SEG0 01223#define THM_BASE__INST4_SEG1 01224#define THM_BASE__INST4_SEG2 01225#define THM_BASE__INST4_SEG3 01226#define THM_BASE__INST4_SEG4 012271228#define THM_BASE__INST5_SEG0 01229#define THM_BASE__INST5_SEG1 01230#define THM_BASE__INST5_SEG2 01231#define THM_BASE__INST5_SEG3 01232#define THM_BASE__INST5_SEG4 012331234#define THM_BASE__INST6_SEG0 01235#define THM_BASE__INST6_SEG1 01236#define THM_BASE__INST6_SEG2 01237#define THM_BASE__INST6_SEG3 01238#define THM_BASE__INST6_SEG4 012391240#define UMC_BASE__INST0_SEG0 0x000140001241#define UMC_BASE__INST0_SEG1 0x024258001242#define UMC_BASE__INST0_SEG2 01243#define UMC_BASE__INST0_SEG3 01244#define UMC_BASE__INST0_SEG4 012451246#define UMC_BASE__INST1_SEG0 0x000540001247#define UMC_BASE__INST1_SEG1 0x02425C001248#define UMC_BASE__INST1_SEG2 01249#define UMC_BASE__INST1_SEG3 01250#define UMC_BASE__INST1_SEG4 012511252#define UMC_BASE__INST2_SEG0 01253#define UMC_BASE__INST2_SEG1 01254#define UMC_BASE__INST2_SEG2 01255#define UMC_BASE__INST2_SEG3 01256#define UMC_BASE__INST2_SEG4 012571258#define UMC_BASE__INST3_SEG0 01259#define UMC_BASE__INST3_SEG1 01260#define UMC_BASE__INST3_SEG2 01261#define UMC_BASE__INST3_SEG3 01262#define UMC_BASE__INST3_SEG4 012631264#define UMC_BASE__INST4_SEG0 01265#define UMC_BASE__INST4_SEG1 01266#define UMC_BASE__INST4_SEG2 01267#define UMC_BASE__INST4_SEG3 01268#define UMC_BASE__INST4_SEG4 012691270#define UMC_BASE__INST5_SEG0 01271#define UMC_BASE__INST5_SEG1 01272#define UMC_BASE__INST5_SEG2 01273#define UMC_BASE__INST5_SEG3 01274#define UMC_BASE__INST5_SEG4 012751276#define UMC_BASE__INST6_SEG0 01277#define UMC_BASE__INST6_SEG1 01278#define UMC_BASE__INST6_SEG2 01279#define UMC_BASE__INST6_SEG3 01280#define UMC_BASE__INST6_SEG4 012811282#define USB0_BASE__INST0_SEG0 0x0242A8001283#define USB0_BASE__INST0_SEG1 0x05B000001284#define USB0_BASE__INST0_SEG2 01285#define USB0_BASE__INST0_SEG3 01286#define USB0_BASE__INST0_SEG4 012871288#define USB0_BASE__INST1_SEG0 01289#define USB0_BASE__INST1_SEG1 01290#define USB0_BASE__INST1_SEG2 01291#define USB0_BASE__INST1_SEG3 01292#define USB0_BASE__INST1_SEG4 012931294#define USB0_BASE__INST2_SEG0 01295#define USB0_BASE__INST2_SEG1 01296#define USB0_BASE__INST2_SEG2 01297#define USB0_BASE__INST2_SEG3 01298#define USB0_BASE__INST2_SEG4 012991300#define USB0_BASE__INST3_SEG0 01301#define USB0_BASE__INST3_SEG1 01302#define USB0_BASE__INST3_SEG2 01303#define USB0_BASE__INST3_SEG3 01304#define USB0_BASE__INST3_SEG4 013051306#define USB0_BASE__INST4_SEG0 01307#define USB0_BASE__INST4_SEG1 01308#define USB0_BASE__INST4_SEG2 01309#define USB0_BASE__INST4_SEG3 01310#define USB0_BASE__INST4_SEG4 013111312#define USB0_BASE__INST5_SEG0 01313#define USB0_BASE__INST5_SEG1 01314#define USB0_BASE__INST5_SEG2 01315#define USB0_BASE__INST5_SEG3 01316#define USB0_BASE__INST5_SEG4 013171318#define USB0_BASE__INST6_SEG0 01319#define USB0_BASE__INST6_SEG1 01320#define USB0_BASE__INST6_SEG2 01321#define USB0_BASE__INST6_SEG3 01322#define USB0_BASE__INST6_SEG4 013231324#define UVD0_BASE__INST0_SEG0 0x000078001325#define UVD0_BASE__INST0_SEG1 0x00007E001326#define UVD0_BASE__INST0_SEG2 0x024030001327#define UVD0_BASE__INST0_SEG3 01328#define UVD0_BASE__INST0_SEG4 013291330#define UVD0_BASE__INST1_SEG0 01331#define UVD0_BASE__INST1_SEG1 01332#define UVD0_BASE__INST1_SEG2 01333#define UVD0_BASE__INST1_SEG3 01334#define UVD0_BASE__INST1_SEG4 013351336#define UVD0_BASE__INST2_SEG0 01337#define UVD0_BASE__INST2_SEG1 01338#define UVD0_BASE__INST2_SEG2 01339#define UVD0_BASE__INST2_SEG3 01340#define UVD0_BASE__INST2_SEG4 013411342#define UVD0_BASE__INST3_SEG0 01343#define UVD0_BASE__INST3_SEG1 01344#define UVD0_BASE__INST3_SEG2 01345#define UVD0_BASE__INST3_SEG3 01346#define UVD0_BASE__INST3_SEG4 013471348#define UVD0_BASE__INST4_SEG0 01349#define UVD0_BASE__INST4_SEG1 01350#define UVD0_BASE__INST4_SEG2 01351#define UVD0_BASE__INST4_SEG3 01352#define UVD0_BASE__INST4_SEG4 013531354#define UVD0_BASE__INST5_SEG0 01355#define UVD0_BASE__INST5_SEG1 01356#define UVD0_BASE__INST5_SEG2 01357#define UVD0_BASE__INST5_SEG3 01358#define UVD0_BASE__INST5_SEG4 013591360#define UVD0_BASE__INST6_SEG0 01361#define UVD0_BASE__INST6_SEG1 01362#define UVD0_BASE__INST6_SEG2 01363#define UVD0_BASE__INST6_SEG3 01364#define UVD0_BASE__INST6_SEG4 013651366#define DCN_BASE__INST0_SEG0 0x000000121367#define DCN_BASE__INST0_SEG1 0x000000C01368#define DCN_BASE__INST0_SEG2 0x000034C01369#define DCN_BASE__INST0_SEG3 01370#define DCN_BASE__INST0_SEG4 013711372#define DCN_BASE__INST1_SEG0 01373#define DCN_BASE__INST1_SEG1 01374#define DCN_BASE__INST1_SEG2 01375#define DCN_BASE__INST1_SEG3 01376#define DCN_BASE__INST1_SEG4 013771378#define DCN_BASE__INST2_SEG0 01379#define DCN_BASE__INST2_SEG1 01380#define DCN_BASE__INST2_SEG2 01381#define DCN_BASE__INST2_SEG3 01382#define DCN_BASE__INST2_SEG4 013831384#define DCN_BASE__INST3_SEG0 01385#define DCN_BASE__INST3_SEG1 01386#define DCN_BASE__INST3_SEG2 01387#define DCN_BASE__INST3_SEG3 01388#define DCN_BASE__INST3_SEG4 013891390#define DCN_BASE__INST4_SEG0 01391#define DCN_BASE__INST4_SEG1 01392#define DCN_BASE__INST4_SEG2 01393#define DCN_BASE__INST4_SEG3 01394#define DCN_BASE__INST4_SEG4 01395#endif139613971398