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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/drivers/gpu/drm/amd/include/soc15_ih_clientid.h
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/*

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 * Copyright 2018 Advanced Micro Devices, Inc.

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 *

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 * Permission is hereby granted, free of charge, to any person obtaining a

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 * copy of this software and associated documentation files (the "Software"),

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 * to deal in the Software without restriction, including without limitation

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 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

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 * and/or sell copies of the Software, and to permit persons to whom the

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 * Software is furnished to do so, subject to the following conditions:

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 *

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 * The above copyright notice and this permission notice shall be included in

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 * all copies or substantial portions of the Software.

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 *

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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

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 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

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 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

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 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

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 * OTHER DEALINGS IN THE SOFTWARE.

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 *

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 */

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#ifndef __SOC15_IH_CLIENTID_H__

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#define __SOC15_IH_CLIENTID_H__

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/*

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 * Vega10+ IH clients

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 * Whenever this structure is updated, which should not happen, make sure

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 * soc15_ih_clientid_name in the below is also updated accordingly.

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 */

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enum soc15_ih_clientid {

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	SOC15_IH_CLIENTID_IH		= 0x00,

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	SOC15_IH_CLIENTID_ACP		= 0x01,

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	SOC15_IH_CLIENTID_ATHUB		= 0x02,

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	SOC15_IH_CLIENTID_BIF		= 0x03,

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	SOC15_IH_CLIENTID_DCE		= 0x04,

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	SOC15_IH_CLIENTID_ISP		= 0x05,

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	SOC15_IH_CLIENTID_PCIE0		= 0x06,

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	SOC15_IH_CLIENTID_RLC		= 0x07,

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	SOC15_IH_CLIENTID_SDMA0		= 0x08,

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	SOC15_IH_CLIENTID_SDMA1		= 0x09,

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	SOC15_IH_CLIENTID_SE0SH		= 0x0a,

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	SOC15_IH_CLIENTID_SE1SH		= 0x0b,

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	SOC15_IH_CLIENTID_SE2SH		= 0x0c,

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	SOC15_IH_CLIENTID_SE3SH		= 0x0d,

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	SOC15_IH_CLIENTID_UVD1		= 0x0e,

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	SOC15_IH_CLIENTID_THM		= 0x0f,

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	SOC15_IH_CLIENTID_UVD		= 0x10,

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	SOC15_IH_CLIENTID_VCE0		= 0x11,

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	SOC15_IH_CLIENTID_VMC		= 0x12,

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	SOC15_IH_CLIENTID_XDMA		= 0x13,

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	SOC15_IH_CLIENTID_GRBM_CP	= 0x14,

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	SOC15_IH_CLIENTID_ATS		= 0x15,

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	SOC15_IH_CLIENTID_ROM_SMUIO	= 0x16,

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	SOC15_IH_CLIENTID_DF		= 0x17,

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	SOC15_IH_CLIENTID_VCE1		= 0x18,

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	SOC15_IH_CLIENTID_PWR		= 0x19,

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	SOC15_IH_CLIENTID_RESERVED	= 0x1a,

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	SOC15_IH_CLIENTID_UTCL2		= 0x1b,

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	SOC15_IH_CLIENTID_EA		= 0x1c,

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	SOC15_IH_CLIENTID_UTCL2LOG	= 0x1d,

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	SOC15_IH_CLIENTID_MP0		= 0x1e,

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	SOC15_IH_CLIENTID_MP1		= 0x1f,

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	SOC15_IH_CLIENTID_MAX,

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	SOC15_IH_CLIENTID_VCN		= SOC15_IH_CLIENTID_UVD,

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	SOC15_IH_CLIENTID_VCN1		= SOC15_IH_CLIENTID_UVD1,

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	SOC15_IH_CLIENTID_SDMA2		= SOC15_IH_CLIENTID_ACP,

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	SOC15_IH_CLIENTID_SDMA3		= SOC15_IH_CLIENTID_DCE,

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	SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid    = SOC15_IH_CLIENTID_ISP,

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	SOC15_IH_CLIENTID_SDMA4		= SOC15_IH_CLIENTID_ISP,

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	SOC15_IH_CLIENTID_SDMA5		= SOC15_IH_CLIENTID_VCE0,

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	SOC15_IH_CLIENTID_SDMA6		= SOC15_IH_CLIENTID_XDMA,

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	SOC15_IH_CLIENTID_SDMA7		= SOC15_IH_CLIENTID_VCE1,

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	SOC15_IH_CLIENTID_VMC1		= SOC15_IH_CLIENTID_PCIE0,

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};

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extern const char *soc15_ih_clientid_name[];

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/*

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 * soc21 IH clients

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 */

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enum soc21_ih_clientid {

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	SOC21_IH_CLIENTID_IH		= 0x00,

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	SOC21_IH_CLIENTID_ATHUB		= 0x02,

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	SOC21_IH_CLIENTID_BIF		= 0x03,

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	SOC21_IH_CLIENTID_DCN		= 0x04,

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	SOC21_IH_CLIENTID_ISP		= 0x05,

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	SOC21_IH_CLIENTID_MP3		= 0x06,

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	SOC21_IH_CLIENTID_RLC		= 0x07,

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	SOC21_IH_CLIENTID_GFX		= 0x0a,

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	SOC21_IH_CLIENTID_IMU		= 0x0b,

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	SOC21_IH_CLIENTID_VCN1		= 0x0e,

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	SOC21_IH_CLIENTID_THM		= 0x0f,

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	SOC21_IH_CLIENTID_VCN		= 0x10,

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	SOC21_IH_CLIENTID_VPE1		= 0x11,

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	SOC21_IH_CLIENTID_VMC		= 0x12,

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	SOC21_IH_CLIENTID_GRBM_CP	= 0x14,

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	SOC21_IH_CLIENTID_ROM_SMUIO	= 0x16,

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	SOC21_IH_CLIENTID_DF		= 0x17,

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	SOC21_IH_CLIENTID_VPE		= 0x18,

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	SOC21_IH_CLIENTID_PWR		= 0x19,

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	SOC21_IH_CLIENTID_LSDMA		= 0x1a,

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	SOC21_IH_CLIENTID_MP0		= 0x1e,

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	SOC21_IH_CLIENTID_MP1		= 0x1f,

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	SOC21_IH_CLIENTID_MAX,

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};

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#endif

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