Path: blob/master/drivers/gpu/drm/amd/include/v10_structs.h
26517 views
/*1* Copyright 2019 Advanced Micro Devices, Inc.2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice shall be included in11* all copies or substantial portions of the Software.12*13* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR14* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,15* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL16* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR17* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,18* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR19* OTHER DEALINGS IN THE SOFTWARE.20*21*/2223#ifndef V10_STRUCTS_H_24#define V10_STRUCTS_H_2526struct v10_gfx_mqd {27uint32_t reserved_0; // offset: 0 (0x0)28uint32_t reserved_1; // offset: 1 (0x1)29uint32_t reserved_2; // offset: 2 (0x2)30uint32_t reserved_3; // offset: 3 (0x3)31uint32_t reserved_4; // offset: 4 (0x4)32uint32_t reserved_5; // offset: 5 (0x5)33uint32_t reserved_6; // offset: 6 (0x6)34uint32_t reserved_7; // offset: 7 (0x7)35uint32_t reserved_8; // offset: 8 (0x8)36uint32_t reserved_9; // offset: 9 (0x9)37uint32_t reserved_10; // offset: 10 (0xA)38uint32_t reserved_11; // offset: 11 (0xB)39uint32_t reserved_12; // offset: 12 (0xC)40uint32_t reserved_13; // offset: 13 (0xD)41uint32_t reserved_14; // offset: 14 (0xE)42uint32_t reserved_15; // offset: 15 (0xF)43uint32_t reserved_16; // offset: 16 (0x10)44uint32_t reserved_17; // offset: 17 (0x11)45uint32_t reserved_18; // offset: 18 (0x12)46uint32_t reserved_19; // offset: 19 (0x13)47uint32_t reserved_20; // offset: 20 (0x14)48uint32_t reserved_21; // offset: 21 (0x15)49uint32_t reserved_22; // offset: 22 (0x16)50uint32_t reserved_23; // offset: 23 (0x17)51uint32_t reserved_24; // offset: 24 (0x18)52uint32_t reserved_25; // offset: 25 (0x19)53uint32_t reserved_26; // offset: 26 (0x1A)54uint32_t reserved_27; // offset: 27 (0x1B)55uint32_t reserved_28; // offset: 28 (0x1C)56uint32_t reserved_29; // offset: 29 (0x1D)57uint32_t reserved_30; // offset: 30 (0x1E)58uint32_t reserved_31; // offset: 31 (0x1F)59uint32_t reserved_32; // offset: 32 (0x20)60uint32_t reserved_33; // offset: 33 (0x21)61uint32_t reserved_34; // offset: 34 (0x22)62uint32_t reserved_35; // offset: 35 (0x23)63uint32_t reserved_36; // offset: 36 (0x24)64uint32_t reserved_37; // offset: 37 (0x25)65uint32_t reserved_38; // offset: 38 (0x26)66uint32_t reserved_39; // offset: 39 (0x27)67uint32_t reserved_40; // offset: 40 (0x28)68uint32_t reserved_41; // offset: 41 (0x29)69uint32_t reserved_42; // offset: 42 (0x2A)70uint32_t reserved_43; // offset: 43 (0x2B)71uint32_t reserved_44; // offset: 44 (0x2C)72uint32_t reserved_45; // offset: 45 (0x2D)73uint32_t reserved_46; // offset: 46 (0x2E)74uint32_t reserved_47; // offset: 47 (0x2F)75uint32_t reserved_48; // offset: 48 (0x30)76uint32_t reserved_49; // offset: 49 (0x31)77uint32_t reserved_50; // offset: 50 (0x32)78uint32_t reserved_51; // offset: 51 (0x33)79uint32_t reserved_52; // offset: 52 (0x34)80uint32_t reserved_53; // offset: 53 (0x35)81uint32_t reserved_54; // offset: 54 (0x36)82uint32_t reserved_55; // offset: 55 (0x37)83uint32_t reserved_56; // offset: 56 (0x38)84uint32_t reserved_57; // offset: 57 (0x39)85uint32_t reserved_58; // offset: 58 (0x3A)86uint32_t reserved_59; // offset: 59 (0x3B)87uint32_t reserved_60; // offset: 60 (0x3C)88uint32_t reserved_61; // offset: 61 (0x3D)89uint32_t reserved_62; // offset: 62 (0x3E)90uint32_t reserved_63; // offset: 63 (0x3F)91uint32_t reserved_64; // offset: 64 (0x40)92uint32_t reserved_65; // offset: 65 (0x41)93uint32_t reserved_66; // offset: 66 (0x42)94uint32_t reserved_67; // offset: 67 (0x43)95uint32_t reserved_68; // offset: 68 (0x44)96uint32_t reserved_69; // offset: 69 (0x45)97uint32_t reserved_70; // offset: 70 (0x46)98uint32_t reserved_71; // offset: 71 (0x47)99uint32_t reserved_72; // offset: 72 (0x48)100uint32_t reserved_73; // offset: 73 (0x49)101uint32_t reserved_74; // offset: 74 (0x4A)102uint32_t reserved_75; // offset: 75 (0x4B)103uint32_t reserved_76; // offset: 76 (0x4C)104uint32_t reserved_77; // offset: 77 (0x4D)105uint32_t reserved_78; // offset: 78 (0x4E)106uint32_t reserved_79; // offset: 79 (0x4F)107uint32_t reserved_80; // offset: 80 (0x50)108uint32_t reserved_81; // offset: 81 (0x51)109uint32_t reserved_82; // offset: 82 (0x52)110uint32_t reserved_83; // offset: 83 (0x53)111uint32_t reserved_84; // offset: 84 (0x54)112uint32_t reserved_85; // offset: 85 (0x55)113uint32_t reserved_86; // offset: 86 (0x56)114uint32_t reserved_87; // offset: 87 (0x57)115uint32_t reserved_88; // offset: 88 (0x58)116uint32_t reserved_89; // offset: 89 (0x59)117uint32_t reserved_90; // offset: 90 (0x5A)118uint32_t reserved_91; // offset: 91 (0x5B)119uint32_t reserved_92; // offset: 92 (0x5C)120uint32_t reserved_93; // offset: 93 (0x5D)121uint32_t reserved_94; // offset: 94 (0x5E)122uint32_t reserved_95; // offset: 95 (0x5F)123uint32_t reserved_96; // offset: 96 (0x60)124uint32_t reserved_97; // offset: 97 (0x61)125uint32_t reserved_98; // offset: 98 (0x62)126uint32_t reserved_99; // offset: 99 (0x63)127uint32_t reserved_100; // offset: 100 (0x64)128uint32_t reserved_101; // offset: 101 (0x65)129uint32_t reserved_102; // offset: 102 (0x66)130uint32_t reserved_103; // offset: 103 (0x67)131uint32_t reserved_104; // offset: 104 (0x68)132uint32_t reserved_105; // offset: 105 (0x69)133uint32_t disable_queue; // offset: 106 (0x6A)134uint32_t reserved_107; // offset: 107 (0x6B)135uint32_t reserved_108; // offset: 108 (0x6C)136uint32_t reserved_109; // offset: 109 (0x6D)137uint32_t reserved_110; // offset: 110 (0x6E)138uint32_t reserved_111; // offset: 111 (0x6F)139uint32_t reserved_112; // offset: 112 (0x70)140uint32_t reserved_113; // offset: 113 (0x71)141uint32_t reserved_114; // offset: 114 (0x72)142uint32_t reserved_115; // offset: 115 (0x73)143uint32_t reserved_116; // offset: 116 (0x74)144uint32_t reserved_117; // offset: 117 (0x75)145uint32_t reserved_118; // offset: 118 (0x76)146uint32_t reserved_119; // offset: 119 (0x77)147uint32_t reserved_120; // offset: 120 (0x78)148uint32_t reserved_121; // offset: 121 (0x79)149uint32_t reserved_122; // offset: 122 (0x7A)150uint32_t reserved_123; // offset: 123 (0x7B)151uint32_t reserved_124; // offset: 124 (0x7C)152uint32_t reserved_125; // offset: 125 (0x7D)153uint32_t reserved_126; // offset: 126 (0x7E)154uint32_t reserved_127; // offset: 127 (0x7F)155uint32_t cp_mqd_base_addr; // offset: 128 (0x80)156uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81)157uint32_t cp_gfx_hqd_active; // offset: 130 (0x82)158uint32_t cp_gfx_hqd_vmid; // offset: 131 (0x83)159uint32_t reserved_131; // offset: 132 (0x84)160uint32_t reserved_132; // offset: 133 (0x85)161uint32_t cp_gfx_hqd_queue_priority; // offset: 134 (0x86)162uint32_t cp_gfx_hqd_quantum; // offset: 135 (0x87)163uint32_t cp_gfx_hqd_base; // offset: 136 (0x88)164uint32_t cp_gfx_hqd_base_hi; // offset: 137 (0x89)165uint32_t cp_gfx_hqd_rptr; // offset: 138 (0x8A)166uint32_t cp_gfx_hqd_rptr_addr; // offset: 139 (0x8B)167uint32_t cp_gfx_hqd_rptr_addr_hi; // offset: 140 (0x8C)168uint32_t cp_rb_wptr_poll_addr_lo; // offset: 141 (0x8D)169uint32_t cp_rb_wptr_poll_addr_hi; // offset: 142 (0x8E)170uint32_t cp_rb_doorbell_control; // offset: 143 (0x8F)171uint32_t cp_gfx_hqd_offset; // offset: 144 (0x90)172uint32_t cp_gfx_hqd_cntl; // offset: 145 (0x91)173uint32_t reserved_146; // offset: 146 (0x92)174uint32_t reserved_147; // offset: 147 (0x93)175uint32_t cp_gfx_hqd_csmd_rptr; // offset: 148 (0x94)176uint32_t cp_gfx_hqd_wptr; // offset: 149 (0x95)177uint32_t cp_gfx_hqd_wptr_hi; // offset: 150 (0x96)178uint32_t reserved_151; // offset: 151 (0x97)179uint32_t reserved_152; // offset: 152 (0x98)180uint32_t reserved_153; // offset: 153 (0x99)181uint32_t reserved_154; // offset: 154 (0x9A)182uint32_t reserved_155; // offset: 155 (0x9B)183uint32_t cp_gfx_hqd_mapped; // offset: 156 (0x9C)184uint32_t cp_gfx_hqd_que_mgr_control; // offset: 157 (0x9D)185uint32_t reserved_158; // offset: 158 (0x9E)186uint32_t reserved_159; // offset: 159 (0x9F)187uint32_t cp_gfx_hqd_hq_status0; // offset: 160 (0xA0)188uint32_t cp_gfx_hqd_hq_control0; // offset: 161 (0xA1)189uint32_t cp_gfx_mqd_control; // offset: 162 (0xA2)190uint32_t reserved_163; // offset: 163 (0xA3)191uint32_t reserved_164; // offset: 164 (0xA4)192uint32_t reserved_165; // offset: 165 (0xA5)193uint32_t reserved_166; // offset: 166 (0xA6)194uint32_t reserved_167; // offset: 167 (0xA7)195uint32_t reserved_168; // offset: 168 (0xA8)196uint32_t reserved_169; // offset: 169 (0xA9)197uint32_t cp_num_prim_needed_count0_lo; // offset: 170 (0xAA)198uint32_t cp_num_prim_needed_count0_hi; // offset: 171 (0xAB)199uint32_t cp_num_prim_needed_count1_lo; // offset: 172 (0xAC)200uint32_t cp_num_prim_needed_count1_hi; // offset: 173 (0xAD)201uint32_t cp_num_prim_needed_count2_lo; // offset: 174 (0xAE)202uint32_t cp_num_prim_needed_count2_hi; // offset: 175 (0xAF)203uint32_t cp_num_prim_needed_count3_lo; // offset: 176 (0xB0)204uint32_t cp_num_prim_needed_count3_hi; // offset: 177 (0xB1)205uint32_t cp_num_prim_written_count0_lo; // offset: 178 (0xB2)206uint32_t cp_num_prim_written_count0_hi; // offset: 179 (0xB3)207uint32_t cp_num_prim_written_count1_lo; // offset: 180 (0xB4)208uint32_t cp_num_prim_written_count1_hi; // offset: 181 (0xB5)209uint32_t cp_num_prim_written_count2_lo; // offset: 182 (0xB6)210uint32_t cp_num_prim_written_count2_hi; // offset: 183 (0xB7)211uint32_t cp_num_prim_written_count3_lo; // offset: 184 (0xB8)212uint32_t cp_num_prim_written_count3_hi; // offset: 185 (0xB9)213uint32_t reserved_186; // offset: 186 (0xBA)214uint32_t reserved_187; // offset: 187 (0xBB)215uint32_t reserved_188; // offset: 188 (0xBC)216uint32_t reserved_189; // offset: 189 (0xBD)217uint32_t mp1_smn_fps_cnt; // offset: 190 (0xBE)218uint32_t sq_thread_trace_buf0_base; // offset: 191 (0xBF)219uint32_t sq_thread_trace_buf0_size; // offset: 192 (0xC0)220uint32_t sq_thread_trace_buf1_base; // offset: 193 (0xC1)221uint32_t sq_thread_trace_buf1_size; // offset: 194 (0xC2)222uint32_t sq_thread_trace_wptr; // offset: 195 (0xC3)223uint32_t sq_thread_trace_mask; // offset: 196 (0xC4)224uint32_t sq_thread_trace_token_mask; // offset: 197 (0xC5)225uint32_t sq_thread_trace_ctrl; // offset: 198 (0xC6)226uint32_t sq_thread_trace_status; // offset: 199 (0xC7)227uint32_t sq_thread_trace_dropped_cntr; // offset: 200 (0xC8)228uint32_t sq_thread_trace_finish_done_debug; // offset: 201 (0xC9)229uint32_t sq_thread_trace_gfx_draw_cntr; // offset: 202 (0xCA)230uint32_t sq_thread_trace_gfx_marker_cntr; // offset: 203 (0xCB)231uint32_t sq_thread_trace_hp3d_draw_cntr; // offset: 204 (0xCC)232uint32_t sq_thread_trace_hp3d_marker_cntr; // offset: 205 (0xCD)233uint32_t reserved_206; // offset: 206 (0xCE)234uint32_t reserved_207; // offset: 207 (0xCF)235uint32_t cp_sc_psinvoc_count0_lo; // offset: 208 (0xD0)236uint32_t cp_sc_psinvoc_count0_hi; // offset: 209 (0xD1)237uint32_t cp_pa_cprim_count_lo; // offset: 210 (0xD2)238uint32_t cp_pa_cprim_count_hi; // offset: 211 (0xD3)239uint32_t cp_pa_cinvoc_count_lo; // offset: 212 (0xD4)240uint32_t cp_pa_cinvoc_count_hi; // offset: 213 (0xD5)241uint32_t cp_vgt_vsinvoc_count_lo; // offset: 214 (0xD6)242uint32_t cp_vgt_vsinvoc_count_hi; // offset: 215 (0xD7)243uint32_t cp_vgt_gsinvoc_count_lo; // offset: 216 (0xD8)244uint32_t cp_vgt_gsinvoc_count_hi; // offset: 217 (0xD9)245uint32_t cp_vgt_gsprim_count_lo; // offset: 218 (0xDA)246uint32_t cp_vgt_gsprim_count_hi; // offset: 219 (0xDB)247uint32_t cp_vgt_iaprim_count_lo; // offset: 220 (0xDC)248uint32_t cp_vgt_iaprim_count_hi; // offset: 221 (0xDD)249uint32_t cp_vgt_iavert_count_lo; // offset: 222 (0xDE)250uint32_t cp_vgt_iavert_count_hi; // offset: 223 (0xDF)251uint32_t cp_vgt_hsinvoc_count_lo; // offset: 224 (0xE0)252uint32_t cp_vgt_hsinvoc_count_hi; // offset: 225 (0xE1)253uint32_t cp_vgt_dsinvoc_count_lo; // offset: 226 (0xE2)254uint32_t cp_vgt_dsinvoc_count_hi; // offset: 227 (0xE3)255uint32_t cp_vgt_csinvoc_count_lo; // offset: 228 (0xE4)256uint32_t cp_vgt_csinvoc_count_hi; // offset: 229 (0xE5)257uint32_t reserved_230; // offset: 230 (0xE6)258uint32_t reserved_231; // offset: 231 (0xE7)259uint32_t reserved_232; // offset: 232 (0xE8)260uint32_t reserved_233; // offset: 233 (0xE9)261uint32_t reserved_234; // offset: 234 (0xEA)262uint32_t reserved_235; // offset: 235 (0xEB)263uint32_t reserved_236; // offset: 236 (0xEC)264uint32_t reserved_237; // offset: 237 (0xED)265uint32_t reserved_238; // offset: 238 (0xEE)266uint32_t reserved_239; // offset: 239 (0xEF)267uint32_t reserved_240; // offset: 240 (0xF0)268uint32_t reserved_241; // offset: 241 (0xF1)269uint32_t reserved_242; // offset: 242 (0xF2)270uint32_t reserved_243; // offset: 243 (0xF3)271uint32_t reserved_244; // offset: 244 (0xF4)272uint32_t reserved_245; // offset: 245 (0xF5)273uint32_t reserved_246; // offset: 246 (0xF6)274uint32_t reserved_247; // offset: 247 (0xF7)275uint32_t reserved_248; // offset: 248 (0xF8)276uint32_t reserved_249; // offset: 249 (0xF9)277uint32_t reserved_250; // offset: 250 (0xFA)278uint32_t reserved_251; // offset: 251 (0xFB)279uint32_t reserved_252; // offset: 252 (0xFC)280uint32_t reserved_253; // offset: 253 (0xFD)281uint32_t reserved_254; // offset: 254 (0xFE)282uint32_t reserved_255; // offset: 255 (0xFF)283uint32_t reserved_256; // offset: 256 (0x100)284uint32_t reserved_257; // offset: 257 (0x101)285uint32_t reserved_258; // offset: 258 (0x102)286uint32_t reserved_259; // offset: 259 (0x103)287uint32_t reserved_260; // offset: 260 (0x104)288uint32_t reserved_261; // offset: 261 (0x105)289uint32_t reserved_262; // offset: 262 (0x106)290uint32_t reserved_263; // offset: 263 (0x107)291uint32_t reserved_264; // offset: 264 (0x108)292uint32_t reserved_265; // offset: 265 (0x109)293uint32_t reserved_266; // offset: 266 (0x10A)294uint32_t reserved_267; // offset: 267 (0x10B)295uint32_t vgt_strmout_buffer_filled_size_0; // offset: 268 (0x10C)296uint32_t vgt_strmout_buffer_filled_size_1; // offset: 269 (0x10D)297uint32_t vgt_strmout_buffer_filled_size_2; // offset: 270 (0x10E)298uint32_t vgt_strmout_buffer_filled_size_3; // offset: 271 (0x10F)299uint32_t reserved_272; // offset: 272 (0x110)300uint32_t reserved_273; // offset: 273 (0x111)301uint32_t reserved_274; // offset: 274 (0x112)302uint32_t reserved_275; // offset: 275 (0x113)303uint32_t vgt_dma_max_size; // offset: 276 (0x114)304uint32_t vgt_dma_num_instances; // offset: 277 (0x115)305uint32_t reserved_278; // offset: 278 (0x116)306uint32_t reserved_279; // offset: 279 (0x117)307uint32_t reserved_280; // offset: 280 (0x118)308uint32_t reserved_281; // offset: 281 (0x119)309uint32_t reserved_282; // offset: 282 (0x11A)310uint32_t reserved_283; // offset: 283 (0x11B)311uint32_t reserved_284; // offset: 284 (0x11C)312uint32_t reserved_285; // offset: 285 (0x11D)313uint32_t reserved_286; // offset: 286 (0x11E)314uint32_t reserved_287; // offset: 287 (0x11F)315uint32_t it_set_base_ib_addr_lo; // offset: 288 (0x120)316uint32_t it_set_base_ib_addr_hi; // offset: 289 (0x121)317uint32_t reserved_290; // offset: 290 (0x122)318uint32_t reserved_291; // offset: 291 (0x123)319uint32_t reserved_292; // offset: 292 (0x124)320uint32_t reserved_293; // offset: 293 (0x125)321uint32_t reserved_294; // offset: 294 (0x126)322uint32_t reserved_295; // offset: 295 (0x127)323uint32_t reserved_296; // offset: 296 (0x128)324uint32_t reserved_297; // offset: 297 (0x129)325uint32_t reserved_298; // offset: 298 (0x12A)326uint32_t reserved_299; // offset: 299 (0x12B)327uint32_t reserved_300; // offset: 300 (0x12C)328uint32_t reserved_301; // offset: 301 (0x12D)329uint32_t reserved_302; // offset: 302 (0x12E)330uint32_t reserved_303; // offset: 303 (0x12F)331uint32_t reserved_304; // offset: 304 (0x130)332uint32_t reserved_305; // offset: 305 (0x131)333uint32_t reserved_306; // offset: 306 (0x132)334uint32_t reserved_307; // offset: 307 (0x133)335uint32_t reserved_308; // offset: 308 (0x134)336uint32_t reserved_309; // offset: 309 (0x135)337uint32_t reserved_310; // offset: 310 (0x136)338uint32_t reserved_311; // offset: 311 (0x137)339uint32_t reserved_312; // offset: 312 (0x138)340uint32_t reserved_313; // offset: 313 (0x139)341uint32_t reserved_314; // offset: 314 (0x13A)342uint32_t reserved_315; // offset: 315 (0x13B)343uint32_t reserved_316; // offset: 316 (0x13C)344uint32_t reserved_317; // offset: 317 (0x13D)345uint32_t reserved_318; // offset: 318 (0x13E)346uint32_t reserved_319; // offset: 319 (0x13F)347uint32_t reserved_320; // offset: 320 (0x140)348uint32_t reserved_321; // offset: 321 (0x141)349uint32_t reserved_322; // offset: 322 (0x142)350uint32_t reserved_323; // offset: 323 (0x143)351uint32_t reserved_324; // offset: 324 (0x144)352uint32_t reserved_325; // offset: 325 (0x145)353uint32_t reserved_326; // offset: 326 (0x146)354uint32_t reserved_327; // offset: 327 (0x147)355uint32_t reserved_328; // offset: 328 (0x148)356uint32_t reserved_329; // offset: 329 (0x149)357uint32_t reserved_330; // offset: 330 (0x14A)358uint32_t reserved_331; // offset: 331 (0x14B)359uint32_t reserved_332; // offset: 332 (0x14C)360uint32_t reserved_333; // offset: 333 (0x14D)361uint32_t reserved_334; // offset: 334 (0x14E)362uint32_t reserved_335; // offset: 335 (0x14F)363uint32_t reserved_336; // offset: 336 (0x150)364uint32_t reserved_337; // offset: 337 (0x151)365uint32_t reserved_338; // offset: 338 (0x152)366uint32_t reserved_339; // offset: 339 (0x153)367uint32_t reserved_340; // offset: 340 (0x154)368uint32_t reserved_341; // offset: 341 (0x155)369uint32_t reserved_342; // offset: 342 (0x156)370uint32_t reserved_343; // offset: 343 (0x157)371uint32_t reserved_344; // offset: 344 (0x158)372uint32_t reserved_345; // offset: 345 (0x159)373uint32_t reserved_346; // offset: 346 (0x15A)374uint32_t reserved_347; // offset: 347 (0x15B)375uint32_t reserved_348; // offset: 348 (0x15C)376uint32_t reserved_349; // offset: 349 (0x15D)377uint32_t reserved_350; // offset: 350 (0x15E)378uint32_t reserved_351; // offset: 351 (0x15F)379uint32_t reserved_352; // offset: 352 (0x160)380uint32_t reserved_353; // offset: 353 (0x161)381uint32_t reserved_354; // offset: 354 (0x162)382uint32_t reserved_355; // offset: 355 (0x163)383uint32_t spi_shader_pgm_rsrc3_ps; // offset: 356 (0x164)384uint32_t spi_shader_pgm_rsrc3_vs; // offset: 357 (0x165)385uint32_t spi_shader_pgm_rsrc3_gs; // offset: 358 (0x166)386uint32_t spi_shader_pgm_rsrc3_hs; // offset: 359 (0x167)387uint32_t spi_shader_pgm_rsrc4_ps; // offset: 360 (0x168)388uint32_t spi_shader_pgm_rsrc4_vs; // offset: 361 (0x169)389uint32_t spi_shader_pgm_rsrc4_gs; // offset: 362 (0x16A)390uint32_t spi_shader_pgm_rsrc4_hs; // offset: 363 (0x16B)391uint32_t db_occlusion_count0_low_00; // offset: 364 (0x16C)392uint32_t db_occlusion_count0_hi_00; // offset: 365 (0x16D)393uint32_t db_occlusion_count1_low_00; // offset: 366 (0x16E)394uint32_t db_occlusion_count1_hi_00; // offset: 367 (0x16F)395uint32_t db_occlusion_count2_low_00; // offset: 368 (0x170)396uint32_t db_occlusion_count2_hi_00; // offset: 369 (0x171)397uint32_t db_occlusion_count3_low_00; // offset: 370 (0x172)398uint32_t db_occlusion_count3_hi_00; // offset: 371 (0x173)399uint32_t db_occlusion_count0_low_01; // offset: 372 (0x174)400uint32_t db_occlusion_count0_hi_01; // offset: 373 (0x175)401uint32_t db_occlusion_count1_low_01; // offset: 374 (0x176)402uint32_t db_occlusion_count1_hi_01; // offset: 375 (0x177)403uint32_t db_occlusion_count2_low_01; // offset: 376 (0x178)404uint32_t db_occlusion_count2_hi_01; // offset: 377 (0x179)405uint32_t db_occlusion_count3_low_01; // offset: 378 (0x17A)406uint32_t db_occlusion_count3_hi_01; // offset: 379 (0x17B)407uint32_t db_occlusion_count0_low_02; // offset: 380 (0x17C)408uint32_t db_occlusion_count0_hi_02; // offset: 381 (0x17D)409uint32_t db_occlusion_count1_low_02; // offset: 382 (0x17E)410uint32_t db_occlusion_count1_hi_02; // offset: 383 (0x17F)411uint32_t db_occlusion_count2_low_02; // offset: 384 (0x180)412uint32_t db_occlusion_count2_hi_02; // offset: 385 (0x181)413uint32_t db_occlusion_count3_low_02; // offset: 386 (0x182)414uint32_t db_occlusion_count3_hi_02; // offset: 387 (0x183)415uint32_t db_occlusion_count0_low_03; // offset: 388 (0x184)416uint32_t db_occlusion_count0_hi_03; // offset: 389 (0x185)417uint32_t db_occlusion_count1_low_03; // offset: 390 (0x186)418uint32_t db_occlusion_count1_hi_03; // offset: 391 (0x187)419uint32_t db_occlusion_count2_low_03; // offset: 392 (0x188)420uint32_t db_occlusion_count2_hi_03; // offset: 393 (0x189)421uint32_t db_occlusion_count3_low_03; // offset: 394 (0x18A)422uint32_t db_occlusion_count3_hi_03; // offset: 395 (0x18B)423uint32_t db_occlusion_count0_low_04; // offset: 396 (0x18C)424uint32_t db_occlusion_count0_hi_04; // offset: 397 (0x18D)425uint32_t db_occlusion_count1_low_04; // offset: 398 (0x18E)426uint32_t db_occlusion_count1_hi_04; // offset: 399 (0x18F)427uint32_t db_occlusion_count2_low_04; // offset: 400 (0x190)428uint32_t db_occlusion_count2_hi_04; // offset: 401 (0x191)429uint32_t db_occlusion_count3_low_04; // offset: 402 (0x192)430uint32_t db_occlusion_count3_hi_04; // offset: 403 (0x193)431uint32_t db_occlusion_count0_low_05; // offset: 404 (0x194)432uint32_t db_occlusion_count0_hi_05; // offset: 405 (0x195)433uint32_t db_occlusion_count1_low_05; // offset: 406 (0x196)434uint32_t db_occlusion_count1_hi_05; // offset: 407 (0x197)435uint32_t db_occlusion_count2_low_05; // offset: 408 (0x198)436uint32_t db_occlusion_count2_hi_05; // offset: 409 (0x199)437uint32_t db_occlusion_count3_low_05; // offset: 410 (0x19A)438uint32_t db_occlusion_count3_hi_05; // offset: 411 (0x19B)439uint32_t db_occlusion_count0_low_06; // offset: 412 (0x19C)440uint32_t db_occlusion_count0_hi_06; // offset: 413 (0x19D)441uint32_t db_occlusion_count1_low_06; // offset: 414 (0x19E)442uint32_t db_occlusion_count1_hi_06; // offset: 415 (0x19F)443uint32_t db_occlusion_count2_low_06; // offset: 416 (0x1A0)444uint32_t db_occlusion_count2_hi_06; // offset: 417 (0x1A1)445uint32_t db_occlusion_count3_low_06; // offset: 418 (0x1A2)446uint32_t db_occlusion_count3_hi_06; // offset: 419 (0x1A3)447uint32_t db_occlusion_count0_low_07; // offset: 420 (0x1A4)448uint32_t db_occlusion_count0_hi_07; // offset: 421 (0x1A5)449uint32_t db_occlusion_count1_low_07; // offset: 422 (0x1A6)450uint32_t db_occlusion_count1_hi_07; // offset: 423 (0x1A7)451uint32_t db_occlusion_count2_low_07; // offset: 424 (0x1A8)452uint32_t db_occlusion_count2_hi_07; // offset: 425 (0x1A9)453uint32_t db_occlusion_count3_low_07; // offset: 426 (0x1AA)454uint32_t db_occlusion_count3_hi_07; // offset: 427 (0x1AB)455uint32_t db_occlusion_count0_low_10; // offset: 428 (0x1AC)456uint32_t db_occlusion_count0_hi_10; // offset: 429 (0x1AD)457uint32_t db_occlusion_count1_low_10; // offset: 430 (0x1AE)458uint32_t db_occlusion_count1_hi_10; // offset: 431 (0x1AF)459uint32_t db_occlusion_count2_low_10; // offset: 432 (0x1B0)460uint32_t db_occlusion_count2_hi_10; // offset: 433 (0x1B1)461uint32_t db_occlusion_count3_low_10; // offset: 434 (0x1B2)462uint32_t db_occlusion_count3_hi_10; // offset: 435 (0x1B3)463uint32_t db_occlusion_count0_low_11; // offset: 436 (0x1B4)464uint32_t db_occlusion_count0_hi_11; // offset: 437 (0x1B5)465uint32_t db_occlusion_count1_low_11; // offset: 438 (0x1B6)466uint32_t db_occlusion_count1_hi_11; // offset: 439 (0x1B7)467uint32_t db_occlusion_count2_low_11; // offset: 440 (0x1B8)468uint32_t db_occlusion_count2_hi_11; // offset: 441 (0x1B9)469uint32_t db_occlusion_count3_low_11; // offset: 442 (0x1BA)470uint32_t db_occlusion_count3_hi_11; // offset: 443 (0x1BB)471uint32_t db_occlusion_count0_low_12; // offset: 444 (0x1BC)472uint32_t db_occlusion_count0_hi_12; // offset: 445 (0x1BD)473uint32_t db_occlusion_count1_low_12; // offset: 446 (0x1BE)474uint32_t db_occlusion_count1_hi_12; // offset: 447 (0x1BF)475uint32_t db_occlusion_count2_low_12; // offset: 448 (0x1C0)476uint32_t db_occlusion_count2_hi_12; // offset: 449 (0x1C1)477uint32_t db_occlusion_count3_low_12; // offset: 450 (0x1C2)478uint32_t db_occlusion_count3_hi_12; // offset: 451 (0x1C3)479uint32_t db_occlusion_count0_low_13; // offset: 452 (0x1C4)480uint32_t db_occlusion_count0_hi_13; // offset: 453 (0x1C5)481uint32_t db_occlusion_count1_low_13; // offset: 454 (0x1C6)482uint32_t db_occlusion_count1_hi_13; // offset: 455 (0x1C7)483uint32_t db_occlusion_count2_low_13; // offset: 456 (0x1C8)484uint32_t db_occlusion_count2_hi_13; // offset: 457 (0x1C9)485uint32_t db_occlusion_count3_low_13; // offset: 458 (0x1CA)486uint32_t db_occlusion_count3_hi_13; // offset: 459 (0x1CB)487uint32_t db_occlusion_count0_low_14; // offset: 460 (0x1CC)488uint32_t db_occlusion_count0_hi_14; // offset: 461 (0x1CD)489uint32_t db_occlusion_count1_low_14; // offset: 462 (0x1CE)490uint32_t db_occlusion_count1_hi_14; // offset: 463 (0x1CF)491uint32_t db_occlusion_count2_low_14; // offset: 464 (0x1D0)492uint32_t db_occlusion_count2_hi_14; // offset: 465 (0x1D1)493uint32_t db_occlusion_count3_low_14; // offset: 466 (0x1D2)494uint32_t db_occlusion_count3_hi_14; // offset: 467 (0x1D3)495uint32_t db_occlusion_count0_low_15; // offset: 468 (0x1D4)496uint32_t db_occlusion_count0_hi_15; // offset: 469 (0x1D5)497uint32_t db_occlusion_count1_low_15; // offset: 470 (0x1D6)498uint32_t db_occlusion_count1_hi_15; // offset: 471 (0x1D7)499uint32_t db_occlusion_count2_low_15; // offset: 472 (0x1D8)500uint32_t db_occlusion_count2_hi_15; // offset: 473 (0x1D9)501uint32_t db_occlusion_count3_low_15; // offset: 474 (0x1DA)502uint32_t db_occlusion_count3_hi_15; // offset: 475 (0x1DB)503uint32_t db_occlusion_count0_low_16; // offset: 476 (0x1DC)504uint32_t db_occlusion_count0_hi_16; // offset: 477 (0x1DD)505uint32_t db_occlusion_count1_low_16; // offset: 478 (0x1DE)506uint32_t db_occlusion_count1_hi_16; // offset: 479 (0x1DF)507uint32_t db_occlusion_count2_low_16; // offset: 480 (0x1E0)508uint32_t db_occlusion_count2_hi_16; // offset: 481 (0x1E1)509uint32_t db_occlusion_count3_low_16; // offset: 482 (0x1E2)510uint32_t db_occlusion_count3_hi_16; // offset: 483 (0x1E3)511uint32_t db_occlusion_count0_low_17; // offset: 484 (0x1E4)512uint32_t db_occlusion_count0_hi_17; // offset: 485 (0x1E5)513uint32_t db_occlusion_count1_low_17; // offset: 486 (0x1E6)514uint32_t db_occlusion_count1_hi_17; // offset: 487 (0x1E7)515uint32_t db_occlusion_count2_low_17; // offset: 488 (0x1E8)516uint32_t db_occlusion_count2_hi_17; // offset: 489 (0x1E9)517uint32_t db_occlusion_count3_low_17; // offset: 490 (0x1EA)518uint32_t db_occlusion_count3_hi_17; // offset: 491 (0x1EB)519uint32_t reserved_492; // offset: 492 (0x1EC)520uint32_t reserved_493; // offset: 493 (0x1ED)521uint32_t reserved_494; // offset: 494 (0x1EE)522uint32_t reserved_495; // offset: 495 (0x1EF)523uint32_t reserved_496; // offset: 496 (0x1F0)524uint32_t reserved_497; // offset: 497 (0x1F1)525uint32_t reserved_498; // offset: 498 (0x1F2)526uint32_t reserved_499; // offset: 499 (0x1F3)527uint32_t reserved_500; // offset: 500 (0x1F4)528uint32_t reserved_501; // offset: 501 (0x1F5)529uint32_t reserved_502; // offset: 502 (0x1F6)530uint32_t reserved_503; // offset: 503 (0x1F7)531uint32_t reserved_504; // offset: 504 (0x1F8)532uint32_t reserved_505; // offset: 505 (0x1F9)533uint32_t reserved_506; // offset: 506 (0x1FA)534uint32_t reserved_507; // offset: 507 (0x1FB)535uint32_t reserved_508; // offset: 508 (0x1FC)536uint32_t reserved_509; // offset: 509 (0x1FD)537uint32_t reserved_510; // offset: 510 (0x1FE)538uint32_t reserved_511; // offset: 511 (0x1FF)539};540541struct v10_sdma_mqd {542uint32_t sdmax_rlcx_rb_cntl;543uint32_t sdmax_rlcx_rb_base;544uint32_t sdmax_rlcx_rb_base_hi;545uint32_t sdmax_rlcx_rb_rptr;546uint32_t sdmax_rlcx_rb_rptr_hi;547uint32_t sdmax_rlcx_rb_wptr;548uint32_t sdmax_rlcx_rb_wptr_hi;549uint32_t sdmax_rlcx_rb_wptr_poll_cntl;550uint32_t sdmax_rlcx_rb_rptr_addr_hi;551uint32_t sdmax_rlcx_rb_rptr_addr_lo;552uint32_t sdmax_rlcx_ib_cntl;553uint32_t sdmax_rlcx_ib_rptr;554uint32_t sdmax_rlcx_ib_offset;555uint32_t sdmax_rlcx_ib_base_lo;556uint32_t sdmax_rlcx_ib_base_hi;557uint32_t sdmax_rlcx_ib_size;558uint32_t sdmax_rlcx_skip_cntl;559uint32_t sdmax_rlcx_context_status;560uint32_t sdmax_rlcx_doorbell;561uint32_t sdmax_rlcx_status;562uint32_t sdmax_rlcx_doorbell_log;563uint32_t sdmax_rlcx_watermark;564uint32_t sdmax_rlcx_doorbell_offset;565uint32_t sdmax_rlcx_csa_addr_lo;566uint32_t sdmax_rlcx_csa_addr_hi;567uint32_t sdmax_rlcx_ib_sub_remain;568uint32_t sdmax_rlcx_preempt;569uint32_t sdmax_rlcx_dummy_reg;570uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi;571uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo;572uint32_t sdmax_rlcx_rb_aql_cntl;573uint32_t sdmax_rlcx_minor_ptr_update;574uint32_t sdmax_rlcx_midcmd_data0;575uint32_t sdmax_rlcx_midcmd_data1;576uint32_t sdmax_rlcx_midcmd_data2;577uint32_t sdmax_rlcx_midcmd_data3;578uint32_t sdmax_rlcx_midcmd_data4;579uint32_t sdmax_rlcx_midcmd_data5;580uint32_t sdmax_rlcx_midcmd_data6;581uint32_t sdmax_rlcx_midcmd_data7;582uint32_t sdmax_rlcx_midcmd_data8;583uint32_t sdmax_rlcx_midcmd_cntl;584uint32_t reserved_42;585uint32_t reserved_43;586uint32_t reserved_44;587uint32_t reserved_45;588uint32_t reserved_46;589uint32_t reserved_47;590uint32_t reserved_48;591uint32_t reserved_49;592uint32_t reserved_50;593uint32_t reserved_51;594uint32_t reserved_52;595uint32_t reserved_53;596uint32_t reserved_54;597uint32_t reserved_55;598uint32_t reserved_56;599uint32_t reserved_57;600uint32_t reserved_58;601uint32_t reserved_59;602uint32_t reserved_60;603uint32_t reserved_61;604uint32_t reserved_62;605uint32_t reserved_63;606uint32_t reserved_64;607uint32_t reserved_65;608uint32_t reserved_66;609uint32_t reserved_67;610uint32_t reserved_68;611uint32_t reserved_69;612uint32_t reserved_70;613uint32_t reserved_71;614uint32_t reserved_72;615uint32_t reserved_73;616uint32_t reserved_74;617uint32_t reserved_75;618uint32_t reserved_76;619uint32_t reserved_77;620uint32_t reserved_78;621uint32_t reserved_79;622uint32_t reserved_80;623uint32_t reserved_81;624uint32_t reserved_82;625uint32_t reserved_83;626uint32_t reserved_84;627uint32_t reserved_85;628uint32_t reserved_86;629uint32_t reserved_87;630uint32_t reserved_88;631uint32_t reserved_89;632uint32_t reserved_90;633uint32_t reserved_91;634uint32_t reserved_92;635uint32_t reserved_93;636uint32_t reserved_94;637uint32_t reserved_95;638uint32_t reserved_96;639uint32_t reserved_97;640uint32_t reserved_98;641uint32_t reserved_99;642uint32_t reserved_100;643uint32_t reserved_101;644uint32_t reserved_102;645uint32_t reserved_103;646uint32_t reserved_104;647uint32_t reserved_105;648uint32_t reserved_106;649uint32_t reserved_107;650uint32_t reserved_108;651uint32_t reserved_109;652uint32_t reserved_110;653uint32_t reserved_111;654uint32_t reserved_112;655uint32_t reserved_113;656uint32_t reserved_114;657uint32_t reserved_115;658uint32_t reserved_116;659uint32_t reserved_117;660uint32_t reserved_118;661uint32_t reserved_119;662uint32_t reserved_120;663uint32_t reserved_121;664uint32_t reserved_122;665uint32_t reserved_123;666uint32_t reserved_124;667uint32_t reserved_125;668uint32_t reserved_126;669uint32_t reserved_127;670uint32_t sdma_engine_id;671uint32_t sdma_queue_id;672};673674struct v10_compute_mqd {675uint32_t header;676uint32_t compute_dispatch_initiator;677uint32_t compute_dim_x;678uint32_t compute_dim_y;679uint32_t compute_dim_z;680uint32_t compute_start_x;681uint32_t compute_start_y;682uint32_t compute_start_z;683uint32_t compute_num_thread_x;684uint32_t compute_num_thread_y;685uint32_t compute_num_thread_z;686uint32_t compute_pipelinestat_enable;687uint32_t compute_perfcount_enable;688uint32_t compute_pgm_lo;689uint32_t compute_pgm_hi;690uint32_t compute_tba_lo;691uint32_t compute_tba_hi;692uint32_t compute_tma_lo;693uint32_t compute_tma_hi;694uint32_t compute_pgm_rsrc1;695uint32_t compute_pgm_rsrc2;696uint32_t compute_vmid;697uint32_t compute_resource_limits;698uint32_t compute_static_thread_mgmt_se0;699uint32_t compute_static_thread_mgmt_se1;700uint32_t compute_tmpring_size;701uint32_t compute_static_thread_mgmt_se2;702uint32_t compute_static_thread_mgmt_se3;703uint32_t compute_restart_x;704uint32_t compute_restart_y;705uint32_t compute_restart_z;706uint32_t compute_thread_trace_enable;707uint32_t compute_misc_reserved;708uint32_t compute_dispatch_id;709uint32_t compute_threadgroup_id;710uint32_t compute_relaunch;711uint32_t compute_wave_restore_addr_lo;712uint32_t compute_wave_restore_addr_hi;713uint32_t compute_wave_restore_control;714uint32_t reserved_39;715uint32_t reserved_40;716uint32_t reserved_41;717uint32_t reserved_42;718uint32_t reserved_43;719uint32_t reserved_44;720uint32_t reserved_45;721uint32_t reserved_46;722uint32_t reserved_47;723uint32_t reserved_48;724uint32_t reserved_49;725uint32_t reserved_50;726uint32_t reserved_51;727uint32_t reserved_52;728uint32_t reserved_53;729uint32_t reserved_54;730uint32_t reserved_55;731uint32_t reserved_56;732uint32_t reserved_57;733uint32_t reserved_58;734uint32_t reserved_59;735uint32_t reserved_60;736uint32_t reserved_61;737uint32_t reserved_62;738uint32_t reserved_63;739uint32_t reserved_64;740uint32_t compute_user_data_0;741uint32_t compute_user_data_1;742uint32_t compute_user_data_2;743uint32_t compute_user_data_3;744uint32_t compute_user_data_4;745uint32_t compute_user_data_5;746uint32_t compute_user_data_6;747uint32_t compute_user_data_7;748uint32_t compute_user_data_8;749uint32_t compute_user_data_9;750uint32_t compute_user_data_10;751uint32_t compute_user_data_11;752uint32_t compute_user_data_12;753uint32_t compute_user_data_13;754uint32_t compute_user_data_14;755uint32_t compute_user_data_15;756uint32_t cp_compute_csinvoc_count_lo;757uint32_t cp_compute_csinvoc_count_hi;758uint32_t reserved_83;759uint32_t reserved_84;760uint32_t reserved_85;761uint32_t cp_mqd_query_time_lo;762uint32_t cp_mqd_query_time_hi;763uint32_t cp_mqd_connect_start_time_lo;764uint32_t cp_mqd_connect_start_time_hi;765uint32_t cp_mqd_connect_end_time_lo;766uint32_t cp_mqd_connect_end_time_hi;767uint32_t cp_mqd_connect_end_wf_count;768uint32_t cp_mqd_connect_end_pq_rptr;769uint32_t cp_mqd_connect_end_pq_wptr;770uint32_t cp_mqd_connect_end_ib_rptr;771uint32_t cp_mqd_readindex_lo;772uint32_t cp_mqd_readindex_hi;773uint32_t cp_mqd_save_start_time_lo;774uint32_t cp_mqd_save_start_time_hi;775uint32_t cp_mqd_save_end_time_lo;776uint32_t cp_mqd_save_end_time_hi;777uint32_t cp_mqd_restore_start_time_lo;778uint32_t cp_mqd_restore_start_time_hi;779uint32_t cp_mqd_restore_end_time_lo;780uint32_t cp_mqd_restore_end_time_hi;781uint32_t disable_queue;782uint32_t reserved_107;783uint32_t gds_cs_ctxsw_cnt0;784uint32_t gds_cs_ctxsw_cnt1;785uint32_t gds_cs_ctxsw_cnt2;786uint32_t gds_cs_ctxsw_cnt3;787uint32_t reserved_112;788uint32_t reserved_113;789uint32_t cp_pq_exe_status_lo;790uint32_t cp_pq_exe_status_hi;791uint32_t cp_packet_id_lo;792uint32_t cp_packet_id_hi;793uint32_t cp_packet_exe_status_lo;794uint32_t cp_packet_exe_status_hi;795uint32_t gds_save_base_addr_lo;796uint32_t gds_save_base_addr_hi;797uint32_t gds_save_mask_lo;798uint32_t gds_save_mask_hi;799uint32_t ctx_save_base_addr_lo;800uint32_t ctx_save_base_addr_hi;801uint32_t reserved_126;802uint32_t reserved_127;803uint32_t cp_mqd_base_addr_lo;804uint32_t cp_mqd_base_addr_hi;805uint32_t cp_hqd_active;806uint32_t cp_hqd_vmid;807uint32_t cp_hqd_persistent_state;808uint32_t cp_hqd_pipe_priority;809uint32_t cp_hqd_queue_priority;810uint32_t cp_hqd_quantum;811uint32_t cp_hqd_pq_base_lo;812uint32_t cp_hqd_pq_base_hi;813uint32_t cp_hqd_pq_rptr;814uint32_t cp_hqd_pq_rptr_report_addr_lo;815uint32_t cp_hqd_pq_rptr_report_addr_hi;816uint32_t cp_hqd_pq_wptr_poll_addr_lo;817uint32_t cp_hqd_pq_wptr_poll_addr_hi;818uint32_t cp_hqd_pq_doorbell_control;819uint32_t reserved_144;820uint32_t cp_hqd_pq_control;821uint32_t cp_hqd_ib_base_addr_lo;822uint32_t cp_hqd_ib_base_addr_hi;823uint32_t cp_hqd_ib_rptr;824uint32_t cp_hqd_ib_control;825uint32_t cp_hqd_iq_timer;826uint32_t cp_hqd_iq_rptr;827uint32_t cp_hqd_dequeue_request;828uint32_t cp_hqd_dma_offload;829uint32_t cp_hqd_sema_cmd;830uint32_t cp_hqd_msg_type;831uint32_t cp_hqd_atomic0_preop_lo;832uint32_t cp_hqd_atomic0_preop_hi;833uint32_t cp_hqd_atomic1_preop_lo;834uint32_t cp_hqd_atomic1_preop_hi;835uint32_t cp_hqd_hq_scheduler0;836uint32_t cp_hqd_hq_scheduler1;837uint32_t cp_mqd_control;838uint32_t cp_hqd_hq_status1;839uint32_t cp_hqd_hq_control1;840uint32_t cp_hqd_eop_base_addr_lo;841uint32_t cp_hqd_eop_base_addr_hi;842uint32_t cp_hqd_eop_control;843uint32_t cp_hqd_eop_rptr;844uint32_t cp_hqd_eop_wptr;845uint32_t cp_hqd_eop_done_events;846uint32_t cp_hqd_ctx_save_base_addr_lo;847uint32_t cp_hqd_ctx_save_base_addr_hi;848uint32_t cp_hqd_ctx_save_control;849uint32_t cp_hqd_cntl_stack_offset;850uint32_t cp_hqd_cntl_stack_size;851uint32_t cp_hqd_wg_state_offset;852uint32_t cp_hqd_ctx_save_size;853uint32_t cp_hqd_gds_resource_state;854uint32_t cp_hqd_error;855uint32_t cp_hqd_eop_wptr_mem;856uint32_t cp_hqd_aql_control;857uint32_t cp_hqd_pq_wptr_lo;858uint32_t cp_hqd_pq_wptr_hi;859uint32_t cp_hqd_suspend_cntl_stack_offset;860uint32_t cp_hqd_suspend_cntl_stack_dw_cnt;861uint32_t cp_hqd_suspend_wg_state_offset;862uint32_t reserved_187;863uint32_t reserved_188;864uint32_t reserved_189;865uint32_t reserved_190;866uint32_t reserved_191;867uint32_t iqtimer_pkt_header;868uint32_t iqtimer_pkt_dw0;869uint32_t iqtimer_pkt_dw1;870uint32_t iqtimer_pkt_dw2;871uint32_t iqtimer_pkt_dw3;872uint32_t iqtimer_pkt_dw4;873uint32_t iqtimer_pkt_dw5;874uint32_t iqtimer_pkt_dw6;875uint32_t iqtimer_pkt_dw7;876uint32_t iqtimer_pkt_dw8;877uint32_t iqtimer_pkt_dw9;878uint32_t iqtimer_pkt_dw10;879uint32_t iqtimer_pkt_dw11;880uint32_t iqtimer_pkt_dw12;881uint32_t iqtimer_pkt_dw13;882uint32_t iqtimer_pkt_dw14;883uint32_t iqtimer_pkt_dw15;884uint32_t iqtimer_pkt_dw16;885uint32_t iqtimer_pkt_dw17;886uint32_t iqtimer_pkt_dw18;887uint32_t iqtimer_pkt_dw19;888uint32_t iqtimer_pkt_dw20;889uint32_t iqtimer_pkt_dw21;890uint32_t iqtimer_pkt_dw22;891uint32_t iqtimer_pkt_dw23;892uint32_t iqtimer_pkt_dw24;893uint32_t iqtimer_pkt_dw25;894uint32_t iqtimer_pkt_dw26;895uint32_t iqtimer_pkt_dw27;896uint32_t iqtimer_pkt_dw28;897uint32_t iqtimer_pkt_dw29;898uint32_t iqtimer_pkt_dw30;899uint32_t iqtimer_pkt_dw31;900uint32_t reserved_225;901uint32_t reserved_226;902uint32_t reserved_227;903uint32_t set_resources_header;904uint32_t set_resources_dw1;905uint32_t set_resources_dw2;906uint32_t set_resources_dw3;907uint32_t set_resources_dw4;908uint32_t set_resources_dw5;909uint32_t set_resources_dw6;910uint32_t set_resources_dw7;911uint32_t reserved_236;912uint32_t reserved_237;913uint32_t reserved_238;914uint32_t reserved_239;915uint32_t queue_doorbell_id0;916uint32_t queue_doorbell_id1;917uint32_t queue_doorbell_id2;918uint32_t queue_doorbell_id3;919uint32_t queue_doorbell_id4;920uint32_t queue_doorbell_id5;921uint32_t queue_doorbell_id6;922uint32_t queue_doorbell_id7;923uint32_t queue_doorbell_id8;924uint32_t queue_doorbell_id9;925uint32_t queue_doorbell_id10;926uint32_t queue_doorbell_id11;927uint32_t queue_doorbell_id12;928uint32_t queue_doorbell_id13;929uint32_t queue_doorbell_id14;930uint32_t queue_doorbell_id15;931uint32_t reserved_256;932uint32_t reserved_257;933uint32_t reserved_258;934uint32_t reserved_259;935uint32_t reserved_260;936uint32_t reserved_261;937uint32_t reserved_262;938uint32_t reserved_263;939uint32_t reserved_264;940uint32_t reserved_265;941uint32_t reserved_266;942uint32_t reserved_267;943uint32_t reserved_268;944uint32_t reserved_269;945uint32_t reserved_270;946uint32_t reserved_271;947uint32_t reserved_272;948uint32_t reserved_273;949uint32_t reserved_274;950uint32_t reserved_275;951uint32_t reserved_276;952uint32_t reserved_277;953uint32_t reserved_278;954uint32_t reserved_279;955uint32_t reserved_280;956uint32_t reserved_281;957uint32_t reserved_282;958uint32_t reserved_283;959uint32_t reserved_284;960uint32_t reserved_285;961uint32_t reserved_286;962uint32_t reserved_287;963uint32_t reserved_288;964uint32_t reserved_289;965uint32_t reserved_290;966uint32_t reserved_291;967uint32_t reserved_292;968uint32_t reserved_293;969uint32_t reserved_294;970uint32_t reserved_295;971uint32_t reserved_296;972uint32_t reserved_297;973uint32_t reserved_298;974uint32_t reserved_299;975uint32_t reserved_300;976uint32_t reserved_301;977uint32_t reserved_302;978uint32_t reserved_303;979uint32_t reserved_304;980uint32_t reserved_305;981uint32_t reserved_306;982uint32_t reserved_307;983uint32_t reserved_308;984uint32_t reserved_309;985uint32_t reserved_310;986uint32_t reserved_311;987uint32_t reserved_312;988uint32_t reserved_313;989uint32_t reserved_314;990uint32_t reserved_315;991uint32_t reserved_316;992uint32_t reserved_317;993uint32_t reserved_318;994uint32_t reserved_319;995uint32_t reserved_320;996uint32_t reserved_321;997uint32_t reserved_322;998uint32_t reserved_323;999uint32_t reserved_324;1000uint32_t reserved_325;1001uint32_t reserved_326;1002uint32_t reserved_327;1003uint32_t reserved_328;1004uint32_t reserved_329;1005uint32_t reserved_330;1006uint32_t reserved_331;1007uint32_t reserved_332;1008uint32_t reserved_333;1009uint32_t reserved_334;1010uint32_t reserved_335;1011uint32_t reserved_336;1012uint32_t reserved_337;1013uint32_t reserved_338;1014uint32_t reserved_339;1015uint32_t reserved_340;1016uint32_t reserved_341;1017uint32_t reserved_342;1018uint32_t reserved_343;1019uint32_t reserved_344;1020uint32_t reserved_345;1021uint32_t reserved_346;1022uint32_t reserved_347;1023uint32_t reserved_348;1024uint32_t reserved_349;1025uint32_t reserved_350;1026uint32_t reserved_351;1027uint32_t reserved_352;1028uint32_t reserved_353;1029uint32_t reserved_354;1030uint32_t reserved_355;1031uint32_t reserved_356;1032uint32_t reserved_357;1033uint32_t reserved_358;1034uint32_t reserved_359;1035uint32_t reserved_360;1036uint32_t reserved_361;1037uint32_t reserved_362;1038uint32_t reserved_363;1039uint32_t reserved_364;1040uint32_t reserved_365;1041uint32_t reserved_366;1042uint32_t reserved_367;1043uint32_t reserved_368;1044uint32_t reserved_369;1045uint32_t reserved_370;1046uint32_t reserved_371;1047uint32_t reserved_372;1048uint32_t reserved_373;1049uint32_t reserved_374;1050uint32_t reserved_375;1051uint32_t reserved_376;1052uint32_t reserved_377;1053uint32_t reserved_378;1054uint32_t reserved_379;1055uint32_t reserved_380;1056uint32_t reserved_381;1057uint32_t reserved_382;1058uint32_t reserved_383;1059uint32_t reserved_384;1060uint32_t reserved_385;1061uint32_t reserved_386;1062uint32_t reserved_387;1063uint32_t reserved_388;1064uint32_t reserved_389;1065uint32_t reserved_390;1066uint32_t reserved_391;1067uint32_t reserved_392;1068uint32_t reserved_393;1069uint32_t reserved_394;1070uint32_t reserved_395;1071uint32_t reserved_396;1072uint32_t reserved_397;1073uint32_t reserved_398;1074uint32_t reserved_399;1075uint32_t reserved_400;1076uint32_t reserved_401;1077uint32_t reserved_402;1078uint32_t reserved_403;1079uint32_t reserved_404;1080uint32_t reserved_405;1081uint32_t reserved_406;1082uint32_t reserved_407;1083uint32_t reserved_408;1084uint32_t reserved_409;1085uint32_t reserved_410;1086uint32_t reserved_411;1087uint32_t reserved_412;1088uint32_t reserved_413;1089uint32_t reserved_414;1090uint32_t reserved_415;1091uint32_t reserved_416;1092uint32_t reserved_417;1093uint32_t reserved_418;1094uint32_t reserved_419;1095uint32_t reserved_420;1096uint32_t reserved_421;1097uint32_t reserved_422;1098uint32_t reserved_423;1099uint32_t reserved_424;1100uint32_t reserved_425;1101uint32_t reserved_426;1102uint32_t reserved_427;1103uint32_t reserved_428;1104uint32_t reserved_429;1105uint32_t reserved_430;1106uint32_t reserved_431;1107uint32_t reserved_432;1108uint32_t reserved_433;1109uint32_t reserved_434;1110uint32_t reserved_435;1111uint32_t reserved_436;1112uint32_t reserved_437;1113uint32_t reserved_438;1114uint32_t reserved_439;1115uint32_t reserved_440;1116uint32_t reserved_441;1117uint32_t reserved_442;1118uint32_t reserved_443;1119uint32_t reserved_444;1120uint32_t reserved_445;1121uint32_t reserved_446;1122uint32_t reserved_447;1123uint32_t reserved_448;1124uint32_t reserved_449;1125uint32_t reserved_450;1126uint32_t reserved_451;1127uint32_t reserved_452;1128uint32_t reserved_453;1129uint32_t reserved_454;1130uint32_t reserved_455;1131uint32_t reserved_456;1132uint32_t reserved_457;1133uint32_t reserved_458;1134uint32_t reserved_459;1135uint32_t reserved_460;1136uint32_t reserved_461;1137uint32_t reserved_462;1138uint32_t reserved_463;1139uint32_t reserved_464;1140uint32_t reserved_465;1141uint32_t reserved_466;1142uint32_t reserved_467;1143uint32_t reserved_468;1144uint32_t reserved_469;1145uint32_t reserved_470;1146uint32_t reserved_471;1147uint32_t reserved_472;1148uint32_t reserved_473;1149uint32_t reserved_474;1150uint32_t reserved_475;1151uint32_t reserved_476;1152uint32_t reserved_477;1153uint32_t reserved_478;1154uint32_t reserved_479;1155uint32_t reserved_480;1156uint32_t reserved_481;1157uint32_t reserved_482;1158uint32_t reserved_483;1159uint32_t reserved_484;1160uint32_t reserved_485;1161uint32_t reserved_486;1162uint32_t reserved_487;1163uint32_t reserved_488;1164uint32_t reserved_489;1165uint32_t reserved_490;1166uint32_t reserved_491;1167uint32_t reserved_492;1168uint32_t reserved_493;1169uint32_t reserved_494;1170uint32_t reserved_495;1171uint32_t reserved_496;1172uint32_t reserved_497;1173uint32_t reserved_498;1174uint32_t reserved_499;1175uint32_t reserved_500;1176uint32_t reserved_501;1177uint32_t reserved_502;1178uint32_t reserved_503;1179uint32_t reserved_504;1180uint32_t reserved_505;1181uint32_t reserved_506;1182uint32_t reserved_507;1183uint32_t reserved_508;1184uint32_t reserved_509;1185uint32_t reserved_510;1186uint32_t reserved_511;1187};11881189struct v10_ce_ib_state {1190/* section of non chained ib part */1191uint32_t ce_ib_completion_status;1192uint32_t ce_constegnine_count;1193uint32_t ce_ibOffset_ib1;1194uint32_t ce_ibOffset_ib2;11951196/* section of chained ib */1197uint32_t ce_chainib_addrlo_ib1;1198uint32_t ce_chainib_addrlo_ib2;1199uint32_t ce_chainib_addrhi_ib1;1200uint32_t ce_chainib_addrhi_ib2;1201uint32_t ce_chainib_size_ib1;1202uint32_t ce_chainib_size_ib2;1203}; /* total 10 DWORD */12041205struct v10_de_ib_state {1206/* section of non chained ib part */1207uint32_t ib_completion_status;1208uint32_t de_constEngine_count;1209uint32_t ib_offset_ib1;1210uint32_t ib_offset_ib2;12111212/* section of chained ib */1213uint32_t chain_ib_addrlo_ib1;1214uint32_t chain_ib_addrlo_ib2;1215uint32_t chain_ib_addrhi_ib1;1216uint32_t chain_ib_addrhi_ib2;1217uint32_t chain_ib_size_ib1;1218uint32_t chain_ib_size_ib2;12191220/* section of non chained ib part */1221uint32_t preamble_begin_ib1;1222uint32_t preamble_begin_ib2;1223uint32_t preamble_end_ib1;1224uint32_t preamble_end_ib2;12251226/* section of chained ib */1227uint32_t chain_ib_pream_addrlo_ib1;1228uint32_t chain_ib_pream_addrlo_ib2;1229uint32_t chain_ib_pream_addrhi_ib1;1230uint32_t chain_ib_pream_addrhi_ib2;12311232/* section of non chained ib part */1233uint32_t draw_indirect_baseLo;1234uint32_t draw_indirect_baseHi;1235uint32_t disp_indirect_baseLo;1236uint32_t disp_indirect_baseHi;1237uint32_t gds_backup_addrlo;1238uint32_t gds_backup_addrhi;1239uint32_t index_base_addrlo;1240uint32_t index_base_addrhi;1241uint32_t sample_cntl;1242}; /* Total of 27 DWORD */12431244struct v10_gfx_meta_data {1245/* 10 DWORD, address must be 4KB aligned */1246struct v10_ce_ib_state ce_payload;1247uint32_t reserved1[54];1248/* 27 DWORD, address must be 64B aligned */1249struct v10_de_ib_state de_payload;1250/* PFP IB base address which get pre-empted */1251uint32_t DeIbBaseAddrLo;1252uint32_t DeIbBaseAddrHi;1253uint32_t reserved2[931];1254}; /* Total of 4K Bytes */12551256#endif /* V10_STRUCTS_H_ */125712581259