Path: blob/master/drivers/gpu/drm/amd/include/vega10_ip_offset.h
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/*1* Copyright (C) 2018 Advanced Micro Devices, Inc.2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice shall be included11* in all copies or substantial portions of the Software.12*13* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS14* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,15* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL16* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN17* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN18* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.19*/20#ifndef _vega10_ip_offset_HEADER21#define _vega10_ip_offset_HEADER2223#define MAX_INSTANCE 524#define MAX_SEGMENT 52526struct IP_BASE_INSTANCE {27unsigned int segment[MAX_SEGMENT];28};2930struct IP_BASE {31struct IP_BASE_INSTANCE instance[MAX_INSTANCE];32};333435static const struct IP_BASE __maybe_unused NBIF_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },36{ { 0, 0, 0, 0, 0 } },37{ { 0, 0, 0, 0, 0 } },38{ { 0, 0, 0, 0, 0 } },39{ { 0, 0, 0, 0, 0 } } } };40static const struct IP_BASE __maybe_unused NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },41{ { 0, 0, 0, 0, 0 } },42{ { 0, 0, 0, 0, 0 } },43{ { 0, 0, 0, 0, 0 } },44{ { 0, 0, 0, 0, 0 } } } };45static const struct IP_BASE __maybe_unused DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },46{ { 0, 0, 0, 0, 0 } },47{ { 0, 0, 0, 0, 0 } },48{ { 0, 0, 0, 0, 0 } },49{ { 0, 0, 0, 0, 0 } } } };50static const struct IP_BASE __maybe_unused DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },51{ { 0, 0, 0, 0, 0 } },52{ { 0, 0, 0, 0, 0 } },53{ { 0, 0, 0, 0, 0 } },54{ { 0, 0, 0, 0, 0 } } } };55static const struct IP_BASE __maybe_unused MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },56{ { 0, 0, 0, 0, 0 } },57{ { 0, 0, 0, 0, 0 } },58{ { 0, 0, 0, 0, 0 } },59{ { 0, 0, 0, 0, 0 } } } };60static const struct IP_BASE __maybe_unused MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },61{ { 0, 0, 0, 0, 0 } },62{ { 0, 0, 0, 0, 0 } },63{ { 0, 0, 0, 0, 0 } },64{ { 0, 0, 0, 0, 0 } } } };65static const struct IP_BASE __maybe_unused MP2_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },66{ { 0, 0, 0, 0, 0 } },67{ { 0, 0, 0, 0, 0 } },68{ { 0, 0, 0, 0, 0 } },69{ { 0, 0, 0, 0, 0 } } } };70static const struct IP_BASE __maybe_unused DF_BASE = { { { { 0x00007000, 0, 0, 0, 0 } },71{ { 0, 0, 0, 0, 0 } },72{ { 0, 0, 0, 0, 0 } },73{ { 0, 0, 0, 0, 0 } },74{ { 0, 0, 0, 0, 0 } } } };75static const struct IP_BASE __maybe_unused UVD_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },76{ { 0, 0, 0, 0, 0 } },77{ { 0, 0, 0, 0, 0 } },78{ { 0, 0, 0, 0, 0 } },79{ { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment80static const struct IP_BASE __maybe_unused VCN_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },81{ { 0, 0, 0, 0, 0 } },82{ { 0, 0, 0, 0, 0 } },83{ { 0, 0, 0, 0, 0 } },84{ { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment85static const struct IP_BASE __maybe_unused DBGU_BASE = { { { { 0x00000180, 0x000001A0, 0, 0, 0 } },86{ { 0, 0, 0, 0, 0 } },87{ { 0, 0, 0, 0, 0 } },88{ { 0, 0, 0, 0, 0 } },89{ { 0, 0, 0, 0, 0 } } } }; // not exist90static const struct IP_BASE __maybe_unused DBGU_NBIO_BASE = { { { { 0x000001C0, 0, 0, 0, 0 } },91{ { 0, 0, 0, 0, 0 } },92{ { 0, 0, 0, 0, 0 } },93{ { 0, 0, 0, 0, 0 } },94{ { 0, 0, 0, 0, 0 } } } }; // not exist95static const struct IP_BASE __maybe_unused DBGU_IO_BASE = { { { { 0x000001E0, 0, 0, 0, 0 } },96{ { 0, 0, 0, 0, 0 } },97{ { 0, 0, 0, 0, 0 } },98{ { 0, 0, 0, 0, 0 } },99{ { 0, 0, 0, 0, 0 } } } }; // not exist100static const struct IP_BASE __maybe_unused DFX_DAP_BASE = { { { { 0x000005A0, 0, 0, 0, 0 } },101{ { 0, 0, 0, 0, 0 } },102{ { 0, 0, 0, 0, 0 } },103{ { 0, 0, 0, 0, 0 } },104{ { 0, 0, 0, 0, 0 } } } }; // not exist105static const struct IP_BASE __maybe_unused DFX_BASE = { { { { 0x00000580, 0, 0, 0, 0 } },106{ { 0, 0, 0, 0, 0 } },107{ { 0, 0, 0, 0, 0 } },108{ { 0, 0, 0, 0, 0 } },109{ { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers110static const struct IP_BASE __maybe_unused ISP_BASE = { { { { 0x00018000, 0, 0, 0, 0 } },111{ { 0, 0, 0, 0, 0 } },112{ { 0, 0, 0, 0, 0 } },113{ { 0, 0, 0, 0, 0 } },114{ { 0, 0, 0, 0, 0 } } } }; // not exist115static const struct IP_BASE __maybe_unused SYSTEMHUB_BASE = { { { { 0x00000EA0, 0, 0, 0, 0 } },116{ { 0, 0, 0, 0, 0 } },117{ { 0, 0, 0, 0, 0 } },118{ { 0, 0, 0, 0, 0 } },119{ { 0, 0, 0, 0, 0 } } } }; // not exist120static const struct IP_BASE __maybe_unused L2IMU_BASE = { { { { 0x00007DC0, 0, 0, 0, 0 } },121{ { 0, 0, 0, 0, 0 } },122{ { 0, 0, 0, 0, 0 } },123{ { 0, 0, 0, 0, 0 } },124{ { 0, 0, 0, 0, 0 } } } };125static const struct IP_BASE __maybe_unused IOHC_BASE = { { { { 0x00010000, 0, 0, 0, 0 } },126{ { 0, 0, 0, 0, 0 } },127{ { 0, 0, 0, 0, 0 } },128{ { 0, 0, 0, 0, 0 } },129{ { 0, 0, 0, 0, 0 } } } };130static const struct IP_BASE __maybe_unused ATHUB_BASE = { { { { 0x00000C20, 0, 0, 0, 0 } },131{ { 0, 0, 0, 0, 0 } },132{ { 0, 0, 0, 0, 0 } },133{ { 0, 0, 0, 0, 0 } },134{ { 0, 0, 0, 0, 0 } } } };135static const struct IP_BASE __maybe_unused VCE_BASE = { { { { 0x00007E00, 0x00048800, 0, 0, 0 } },136{ { 0, 0, 0, 0, 0 } },137{ { 0, 0, 0, 0, 0 } },138{ { 0, 0, 0, 0, 0 } },139{ { 0, 0, 0, 0, 0 } } } };140static const struct IP_BASE __maybe_unused GC_BASE = { { { { 0x00002000, 0x0000A000, 0, 0, 0 } },141{ { 0, 0, 0, 0, 0 } },142{ { 0, 0, 0, 0, 0 } },143{ { 0, 0, 0, 0, 0 } },144{ { 0, 0, 0, 0, 0 } } } };145static const struct IP_BASE __maybe_unused MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0 } },146{ { 0, 0, 0, 0, 0 } },147{ { 0, 0, 0, 0, 0 } },148{ { 0, 0, 0, 0, 0 } },149{ { 0, 0, 0, 0, 0 } } } };150static const struct IP_BASE __maybe_unused RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0 } },151{ { 0, 0, 0, 0, 0 } },152{ { 0, 0, 0, 0, 0 } },153{ { 0, 0, 0, 0, 0 } },154{ { 0, 0, 0, 0, 0 } } } };155static const struct IP_BASE __maybe_unused HDP_BASE = { { { { 0x00000F20, 0, 0, 0, 0 } },156{ { 0, 0, 0, 0, 0 } },157{ { 0, 0, 0, 0, 0 } },158{ { 0, 0, 0, 0, 0 } },159{ { 0, 0, 0, 0, 0 } } } };160static const struct IP_BASE __maybe_unused OSSSYS_BASE = { { { { 0x000010A0, 0, 0, 0, 0 } },161{ { 0, 0, 0, 0, 0 } },162{ { 0, 0, 0, 0, 0 } },163{ { 0, 0, 0, 0, 0 } },164{ { 0, 0, 0, 0, 0 } } } };165static const struct IP_BASE __maybe_unused SDMA0_BASE = { { { { 0x00001260, 0, 0, 0, 0 } },166{ { 0, 0, 0, 0, 0 } },167{ { 0, 0, 0, 0, 0 } },168{ { 0, 0, 0, 0, 0 } },169{ { 0, 0, 0, 0, 0 } } } };170static const struct IP_BASE __maybe_unused SDMA1_BASE = { { { { 0x00001460, 0, 0, 0, 0 } },171{ { 0, 0, 0, 0, 0 } },172{ { 0, 0, 0, 0, 0 } },173{ { 0, 0, 0, 0, 0 } },174{ { 0, 0, 0, 0, 0 } } } };175static const struct IP_BASE __maybe_unused XDMA_BASE = { { { { 0x00003400, 0, 0, 0, 0 } },176{ { 0, 0, 0, 0, 0 } },177{ { 0, 0, 0, 0, 0 } },178{ { 0, 0, 0, 0, 0 } },179{ { 0, 0, 0, 0, 0 } } } };180static const struct IP_BASE __maybe_unused UMC_BASE = { { { { 0x00014000, 0, 0, 0, 0 } },181{ { 0, 0, 0, 0, 0 } },182{ { 0, 0, 0, 0, 0 } },183{ { 0, 0, 0, 0, 0 } },184{ { 0, 0, 0, 0, 0 } } } };185static const struct IP_BASE __maybe_unused THM_BASE = { { { { 0x00016600, 0, 0, 0, 0 } },186{ { 0, 0, 0, 0, 0 } },187{ { 0, 0, 0, 0, 0 } },188{ { 0, 0, 0, 0, 0 } },189{ { 0, 0, 0, 0, 0 } } } };190static const struct IP_BASE __maybe_unused SMUIO_BASE = { { { { 0x00016800, 0, 0, 0, 0 } },191{ { 0, 0, 0, 0, 0 } },192{ { 0, 0, 0, 0, 0 } },193{ { 0, 0, 0, 0, 0 } },194{ { 0, 0, 0, 0, 0 } } } };195static const struct IP_BASE __maybe_unused PWR_BASE = { { { { 0x00016A00, 0, 0, 0, 0 } },196{ { 0, 0, 0, 0, 0 } },197{ { 0, 0, 0, 0, 0 } },198{ { 0, 0, 0, 0, 0 } },199{ { 0, 0, 0, 0, 0 } } } };200static const struct IP_BASE __maybe_unused CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } },201{ { 0x00016E00, 0, 0, 0, 0 } },202{ { 0x00017000, 0, 0, 0, 0 } },203{ { 0x00017200, 0, 0, 0, 0 } },204{ { 0x00017E00, 0, 0, 0, 0 } } } };205static const struct IP_BASE __maybe_unused FUSE_BASE = { { { { 0x00017400, 0, 0, 0, 0 } },206{ { 0, 0, 0, 0, 0 } },207{ { 0, 0, 0, 0, 0 } },208{ { 0, 0, 0, 0, 0 } },209{ { 0, 0, 0, 0, 0 } } } };210211212#define NBIF_BASE__INST0_SEG0 0x00000000213#define NBIF_BASE__INST0_SEG1 0x00000014214#define NBIF_BASE__INST0_SEG2 0x00000D20215#define NBIF_BASE__INST0_SEG3 0x00010400216#define NBIF_BASE__INST0_SEG4 0217218#define NBIF_BASE__INST1_SEG0 0219#define NBIF_BASE__INST1_SEG1 0220#define NBIF_BASE__INST1_SEG2 0221#define NBIF_BASE__INST1_SEG3 0222#define NBIF_BASE__INST1_SEG4 0223224#define NBIF_BASE__INST2_SEG0 0225#define NBIF_BASE__INST2_SEG1 0226#define NBIF_BASE__INST2_SEG2 0227#define NBIF_BASE__INST2_SEG3 0228#define NBIF_BASE__INST2_SEG4 0229230#define NBIF_BASE__INST3_SEG0 0231#define NBIF_BASE__INST3_SEG1 0232#define NBIF_BASE__INST3_SEG2 0233#define NBIF_BASE__INST3_SEG3 0234#define NBIF_BASE__INST3_SEG4 0235236#define NBIF_BASE__INST4_SEG0 0237#define NBIF_BASE__INST4_SEG1 0238#define NBIF_BASE__INST4_SEG2 0239#define NBIF_BASE__INST4_SEG3 0240#define NBIF_BASE__INST4_SEG4 0241242#define NBIO_BASE__INST0_SEG0 0x00000000243#define NBIO_BASE__INST0_SEG1 0x00000014244#define NBIO_BASE__INST0_SEG2 0x00000D20245#define NBIO_BASE__INST0_SEG3 0x00010400246#define NBIO_BASE__INST0_SEG4 0247248#define NBIO_BASE__INST1_SEG0 0249#define NBIO_BASE__INST1_SEG1 0250#define NBIO_BASE__INST1_SEG2 0251#define NBIO_BASE__INST1_SEG3 0252#define NBIO_BASE__INST1_SEG4 0253254#define NBIO_BASE__INST2_SEG0 0255#define NBIO_BASE__INST2_SEG1 0256#define NBIO_BASE__INST2_SEG2 0257#define NBIO_BASE__INST2_SEG3 0258#define NBIO_BASE__INST2_SEG4 0259260#define NBIO_BASE__INST3_SEG0 0261#define NBIO_BASE__INST3_SEG1 0262#define NBIO_BASE__INST3_SEG2 0263#define NBIO_BASE__INST3_SEG3 0264#define NBIO_BASE__INST3_SEG4 0265266#define NBIO_BASE__INST4_SEG0 0267#define NBIO_BASE__INST4_SEG1 0268#define NBIO_BASE__INST4_SEG2 0269#define NBIO_BASE__INST4_SEG3 0270#define NBIO_BASE__INST4_SEG4 0271272#define DCE_BASE__INST0_SEG0 0x00000012273#define DCE_BASE__INST0_SEG1 0x000000C0274#define DCE_BASE__INST0_SEG2 0x000034C0275#define DCE_BASE__INST0_SEG3 0276#define DCE_BASE__INST0_SEG4 0277278#define DCE_BASE__INST1_SEG0 0279#define DCE_BASE__INST1_SEG1 0280#define DCE_BASE__INST1_SEG2 0281#define DCE_BASE__INST1_SEG3 0282#define DCE_BASE__INST1_SEG4 0283284#define DCE_BASE__INST2_SEG0 0285#define DCE_BASE__INST2_SEG1 0286#define DCE_BASE__INST2_SEG2 0287#define DCE_BASE__INST2_SEG3 0288#define DCE_BASE__INST2_SEG4 0289290#define DCE_BASE__INST3_SEG0 0291#define DCE_BASE__INST3_SEG1 0292#define DCE_BASE__INST3_SEG2 0293#define DCE_BASE__INST3_SEG3 0294#define DCE_BASE__INST3_SEG4 0295296#define DCE_BASE__INST4_SEG0 0297#define DCE_BASE__INST4_SEG1 0298#define DCE_BASE__INST4_SEG2 0299#define DCE_BASE__INST4_SEG3 0300#define DCE_BASE__INST4_SEG4 0301302#define DCN_BASE__INST0_SEG0 0x00000012303#define DCN_BASE__INST0_SEG1 0x000000C0304#define DCN_BASE__INST0_SEG2 0x000034C0305#define DCN_BASE__INST0_SEG3 0306#define DCN_BASE__INST0_SEG4 0307308#define DCN_BASE__INST1_SEG0 0309#define DCN_BASE__INST1_SEG1 0310#define DCN_BASE__INST1_SEG2 0311#define DCN_BASE__INST1_SEG3 0312#define DCN_BASE__INST1_SEG4 0313314#define DCN_BASE__INST2_SEG0 0315#define DCN_BASE__INST2_SEG1 0316#define DCN_BASE__INST2_SEG2 0317#define DCN_BASE__INST2_SEG3 0318#define DCN_BASE__INST2_SEG4 0319320#define DCN_BASE__INST3_SEG0 0321#define DCN_BASE__INST3_SEG1 0322#define DCN_BASE__INST3_SEG2 0323#define DCN_BASE__INST3_SEG3 0324#define DCN_BASE__INST3_SEG4 0325326#define DCN_BASE__INST4_SEG0 0327#define DCN_BASE__INST4_SEG1 0328#define DCN_BASE__INST4_SEG2 0329#define DCN_BASE__INST4_SEG3 0330#define DCN_BASE__INST4_SEG4 0331332#define MP0_BASE__INST0_SEG0 0x00016000333#define MP0_BASE__INST0_SEG1 0334#define MP0_BASE__INST0_SEG2 0335#define MP0_BASE__INST0_SEG3 0336#define MP0_BASE__INST0_SEG4 0337338#define MP0_BASE__INST1_SEG0 0339#define MP0_BASE__INST1_SEG1 0340#define MP0_BASE__INST1_SEG2 0341#define MP0_BASE__INST1_SEG3 0342#define MP0_BASE__INST1_SEG4 0343344#define MP0_BASE__INST2_SEG0 0345#define MP0_BASE__INST2_SEG1 0346#define MP0_BASE__INST2_SEG2 0347#define MP0_BASE__INST2_SEG3 0348#define MP0_BASE__INST2_SEG4 0349350#define MP0_BASE__INST3_SEG0 0351#define MP0_BASE__INST3_SEG1 0352#define MP0_BASE__INST3_SEG2 0353#define MP0_BASE__INST3_SEG3 0354#define MP0_BASE__INST3_SEG4 0355356#define MP0_BASE__INST4_SEG0 0357#define MP0_BASE__INST4_SEG1 0358#define MP0_BASE__INST4_SEG2 0359#define MP0_BASE__INST4_SEG3 0360#define MP0_BASE__INST4_SEG4 0361362#define MP1_BASE__INST0_SEG0 0x00016200363#define MP1_BASE__INST0_SEG1 0364#define MP1_BASE__INST0_SEG2 0365#define MP1_BASE__INST0_SEG3 0366#define MP1_BASE__INST0_SEG4 0367368#define MP1_BASE__INST1_SEG0 0369#define MP1_BASE__INST1_SEG1 0370#define MP1_BASE__INST1_SEG2 0371#define MP1_BASE__INST1_SEG3 0372#define MP1_BASE__INST1_SEG4 0373374#define MP1_BASE__INST2_SEG0 0375#define MP1_BASE__INST2_SEG1 0376#define MP1_BASE__INST2_SEG2 0377#define MP1_BASE__INST2_SEG3 0378#define MP1_BASE__INST2_SEG4 0379380#define MP1_BASE__INST3_SEG0 0381#define MP1_BASE__INST3_SEG1 0382#define MP1_BASE__INST3_SEG2 0383#define MP1_BASE__INST3_SEG3 0384#define MP1_BASE__INST3_SEG4 0385386#define MP1_BASE__INST4_SEG0 0387#define MP1_BASE__INST4_SEG1 0388#define MP1_BASE__INST4_SEG2 0389#define MP1_BASE__INST4_SEG3 0390#define MP1_BASE__INST4_SEG4 0391392#define MP2_BASE__INST0_SEG0 0x00016400393#define MP2_BASE__INST0_SEG1 0394#define MP2_BASE__INST0_SEG2 0395#define MP2_BASE__INST0_SEG3 0396#define MP2_BASE__INST0_SEG4 0397398#define MP2_BASE__INST1_SEG0 0399#define MP2_BASE__INST1_SEG1 0400#define MP2_BASE__INST1_SEG2 0401#define MP2_BASE__INST1_SEG3 0402#define MP2_BASE__INST1_SEG4 0403404#define MP2_BASE__INST2_SEG0 0405#define MP2_BASE__INST2_SEG1 0406#define MP2_BASE__INST2_SEG2 0407#define MP2_BASE__INST2_SEG3 0408#define MP2_BASE__INST2_SEG4 0409410#define MP2_BASE__INST3_SEG0 0411#define MP2_BASE__INST3_SEG1 0412#define MP2_BASE__INST3_SEG2 0413#define MP2_BASE__INST3_SEG3 0414#define MP2_BASE__INST3_SEG4 0415416#define MP2_BASE__INST4_SEG0 0417#define MP2_BASE__INST4_SEG1 0418#define MP2_BASE__INST4_SEG2 0419#define MP2_BASE__INST4_SEG3 0420#define MP2_BASE__INST4_SEG4 0421422#define DF_BASE__INST0_SEG0 0x00007000423#define DF_BASE__INST0_SEG1 0424#define DF_BASE__INST0_SEG2 0425#define DF_BASE__INST0_SEG3 0426#define DF_BASE__INST0_SEG4 0427428#define DF_BASE__INST1_SEG0 0429#define DF_BASE__INST1_SEG1 0430#define DF_BASE__INST1_SEG2 0431#define DF_BASE__INST1_SEG3 0432#define DF_BASE__INST1_SEG4 0433434#define DF_BASE__INST2_SEG0 0435#define DF_BASE__INST2_SEG1 0436#define DF_BASE__INST2_SEG2 0437#define DF_BASE__INST2_SEG3 0438#define DF_BASE__INST2_SEG4 0439440#define DF_BASE__INST3_SEG0 0441#define DF_BASE__INST3_SEG1 0442#define DF_BASE__INST3_SEG2 0443#define DF_BASE__INST3_SEG3 0444#define DF_BASE__INST3_SEG4 0445446#define DF_BASE__INST4_SEG0 0447#define DF_BASE__INST4_SEG1 0448#define DF_BASE__INST4_SEG2 0449#define DF_BASE__INST4_SEG3 0450#define DF_BASE__INST4_SEG4 0451452#define UVD_BASE__INST0_SEG0 0x00007800453#define UVD_BASE__INST0_SEG1 0x00007E00454#define UVD_BASE__INST0_SEG2 0455#define UVD_BASE__INST0_SEG3 0456#define UVD_BASE__INST0_SEG4 0457458#define UVD_BASE__INST1_SEG0 0459#define UVD_BASE__INST1_SEG1 0460#define UVD_BASE__INST1_SEG2 0461#define UVD_BASE__INST1_SEG3 0462#define UVD_BASE__INST1_SEG4 0463464#define UVD_BASE__INST2_SEG0 0465#define UVD_BASE__INST2_SEG1 0466#define UVD_BASE__INST2_SEG2 0467#define UVD_BASE__INST2_SEG3 0468#define UVD_BASE__INST2_SEG4 0469470#define UVD_BASE__INST3_SEG0 0471#define UVD_BASE__INST3_SEG1 0472#define UVD_BASE__INST3_SEG2 0473#define UVD_BASE__INST3_SEG3 0474#define UVD_BASE__INST3_SEG4 0475476#define UVD_BASE__INST4_SEG0 0477#define UVD_BASE__INST4_SEG1 0478#define UVD_BASE__INST4_SEG2 0479#define UVD_BASE__INST4_SEG3 0480#define UVD_BASE__INST4_SEG4 0481482#define VCN_BASE__INST0_SEG0 0x00007800483#define VCN_BASE__INST0_SEG1 0x00007E00484#define VCN_BASE__INST0_SEG2 0485#define VCN_BASE__INST0_SEG3 0486#define VCN_BASE__INST0_SEG4 0487488#define VCN_BASE__INST1_SEG0 0489#define VCN_BASE__INST1_SEG1 0490#define VCN_BASE__INST1_SEG2 0491#define VCN_BASE__INST1_SEG3 0492#define VCN_BASE__INST1_SEG4 0493494#define VCN_BASE__INST2_SEG0 0495#define VCN_BASE__INST2_SEG1 0496#define VCN_BASE__INST2_SEG2 0497#define VCN_BASE__INST2_SEG3 0498#define VCN_BASE__INST2_SEG4 0499500#define VCN_BASE__INST3_SEG0 0501#define VCN_BASE__INST3_SEG1 0502#define VCN_BASE__INST3_SEG2 0503#define VCN_BASE__INST3_SEG3 0504#define VCN_BASE__INST3_SEG4 0505506#define VCN_BASE__INST4_SEG0 0507#define VCN_BASE__INST4_SEG1 0508#define VCN_BASE__INST4_SEG2 0509#define VCN_BASE__INST4_SEG3 0510#define VCN_BASE__INST4_SEG4 0511512#define DBGU_BASE__INST0_SEG0 0x00000180513#define DBGU_BASE__INST0_SEG1 0x000001A0514#define DBGU_BASE__INST0_SEG2 0515#define DBGU_BASE__INST0_SEG3 0516#define DBGU_BASE__INST0_SEG4 0517518#define DBGU_BASE__INST1_SEG0 0519#define DBGU_BASE__INST1_SEG1 0520#define DBGU_BASE__INST1_SEG2 0521#define DBGU_BASE__INST1_SEG3 0522#define DBGU_BASE__INST1_SEG4 0523524#define DBGU_BASE__INST2_SEG0 0525#define DBGU_BASE__INST2_SEG1 0526#define DBGU_BASE__INST2_SEG2 0527#define DBGU_BASE__INST2_SEG3 0528#define DBGU_BASE__INST2_SEG4 0529530#define DBGU_BASE__INST3_SEG0 0531#define DBGU_BASE__INST3_SEG1 0532#define DBGU_BASE__INST3_SEG2 0533#define DBGU_BASE__INST3_SEG3 0534#define DBGU_BASE__INST3_SEG4 0535536#define DBGU_BASE__INST4_SEG0 0537#define DBGU_BASE__INST4_SEG1 0538#define DBGU_BASE__INST4_SEG2 0539#define DBGU_BASE__INST4_SEG3 0540#define DBGU_BASE__INST4_SEG4 0541542#define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0543#define DBGU_NBIO_BASE__INST0_SEG1 0544#define DBGU_NBIO_BASE__INST0_SEG2 0545#define DBGU_NBIO_BASE__INST0_SEG3 0546#define DBGU_NBIO_BASE__INST0_SEG4 0547548#define DBGU_NBIO_BASE__INST1_SEG0 0549#define DBGU_NBIO_BASE__INST1_SEG1 0550#define DBGU_NBIO_BASE__INST1_SEG2 0551#define DBGU_NBIO_BASE__INST1_SEG3 0552#define DBGU_NBIO_BASE__INST1_SEG4 0553554#define DBGU_NBIO_BASE__INST2_SEG0 0555#define DBGU_NBIO_BASE__INST2_SEG1 0556#define DBGU_NBIO_BASE__INST2_SEG2 0557#define DBGU_NBIO_BASE__INST2_SEG3 0558#define DBGU_NBIO_BASE__INST2_SEG4 0559560#define DBGU_NBIO_BASE__INST3_SEG0 0561#define DBGU_NBIO_BASE__INST3_SEG1 0562#define DBGU_NBIO_BASE__INST3_SEG2 0563#define DBGU_NBIO_BASE__INST3_SEG3 0564#define DBGU_NBIO_BASE__INST3_SEG4 0565566#define DBGU_NBIO_BASE__INST4_SEG0 0567#define DBGU_NBIO_BASE__INST4_SEG1 0568#define DBGU_NBIO_BASE__INST4_SEG2 0569#define DBGU_NBIO_BASE__INST4_SEG3 0570#define DBGU_NBIO_BASE__INST4_SEG4 0571572#define DBGU_IO_BASE__INST0_SEG0 0x000001E0573#define DBGU_IO_BASE__INST0_SEG1 0574#define DBGU_IO_BASE__INST0_SEG2 0575#define DBGU_IO_BASE__INST0_SEG3 0576#define DBGU_IO_BASE__INST0_SEG4 0577578#define DBGU_IO_BASE__INST1_SEG0 0579#define DBGU_IO_BASE__INST1_SEG1 0580#define DBGU_IO_BASE__INST1_SEG2 0581#define DBGU_IO_BASE__INST1_SEG3 0582#define DBGU_IO_BASE__INST1_SEG4 0583584#define DBGU_IO_BASE__INST2_SEG0 0585#define DBGU_IO_BASE__INST2_SEG1 0586#define DBGU_IO_BASE__INST2_SEG2 0587#define DBGU_IO_BASE__INST2_SEG3 0588#define DBGU_IO_BASE__INST2_SEG4 0589590#define DBGU_IO_BASE__INST3_SEG0 0591#define DBGU_IO_BASE__INST3_SEG1 0592#define DBGU_IO_BASE__INST3_SEG2 0593#define DBGU_IO_BASE__INST3_SEG3 0594#define DBGU_IO_BASE__INST3_SEG4 0595596#define DBGU_IO_BASE__INST4_SEG0 0597#define DBGU_IO_BASE__INST4_SEG1 0598#define DBGU_IO_BASE__INST4_SEG2 0599#define DBGU_IO_BASE__INST4_SEG3 0600#define DBGU_IO_BASE__INST4_SEG4 0601602#define DFX_DAP_BASE__INST0_SEG0 0x000005A0603#define DFX_DAP_BASE__INST0_SEG1 0604#define DFX_DAP_BASE__INST0_SEG2 0605#define DFX_DAP_BASE__INST0_SEG3 0606#define DFX_DAP_BASE__INST0_SEG4 0607608#define DFX_DAP_BASE__INST1_SEG0 0609#define DFX_DAP_BASE__INST1_SEG1 0610#define DFX_DAP_BASE__INST1_SEG2 0611#define DFX_DAP_BASE__INST1_SEG3 0612#define DFX_DAP_BASE__INST1_SEG4 0613614#define DFX_DAP_BASE__INST2_SEG0 0615#define DFX_DAP_BASE__INST2_SEG1 0616#define DFX_DAP_BASE__INST2_SEG2 0617#define DFX_DAP_BASE__INST2_SEG3 0618#define DFX_DAP_BASE__INST2_SEG4 0619620#define DFX_DAP_BASE__INST3_SEG0 0621#define DFX_DAP_BASE__INST3_SEG1 0622#define DFX_DAP_BASE__INST3_SEG2 0623#define DFX_DAP_BASE__INST3_SEG3 0624#define DFX_DAP_BASE__INST3_SEG4 0625626#define DFX_DAP_BASE__INST4_SEG0 0627#define DFX_DAP_BASE__INST4_SEG1 0628#define DFX_DAP_BASE__INST4_SEG2 0629#define DFX_DAP_BASE__INST4_SEG3 0630#define DFX_DAP_BASE__INST4_SEG4 0631632#define DFX_BASE__INST0_SEG0 0x00000580633#define DFX_BASE__INST0_SEG1 0634#define DFX_BASE__INST0_SEG2 0635#define DFX_BASE__INST0_SEG3 0636#define DFX_BASE__INST0_SEG4 0637638#define DFX_BASE__INST1_SEG0 0639#define DFX_BASE__INST1_SEG1 0640#define DFX_BASE__INST1_SEG2 0641#define DFX_BASE__INST1_SEG3 0642#define DFX_BASE__INST1_SEG4 0643644#define DFX_BASE__INST2_SEG0 0645#define DFX_BASE__INST2_SEG1 0646#define DFX_BASE__INST2_SEG2 0647#define DFX_BASE__INST2_SEG3 0648#define DFX_BASE__INST2_SEG4 0649650#define DFX_BASE__INST3_SEG0 0651#define DFX_BASE__INST3_SEG1 0652#define DFX_BASE__INST3_SEG2 0653#define DFX_BASE__INST3_SEG3 0654#define DFX_BASE__INST3_SEG4 0655656#define DFX_BASE__INST4_SEG0 0657#define DFX_BASE__INST4_SEG1 0658#define DFX_BASE__INST4_SEG2 0659#define DFX_BASE__INST4_SEG3 0660#define DFX_BASE__INST4_SEG4 0661662#define ISP_BASE__INST0_SEG0 0x00018000663#define ISP_BASE__INST0_SEG1 0664#define ISP_BASE__INST0_SEG2 0665#define ISP_BASE__INST0_SEG3 0666#define ISP_BASE__INST0_SEG4 0667668#define ISP_BASE__INST1_SEG0 0669#define ISP_BASE__INST1_SEG1 0670#define ISP_BASE__INST1_SEG2 0671#define ISP_BASE__INST1_SEG3 0672#define ISP_BASE__INST1_SEG4 0673674#define ISP_BASE__INST2_SEG0 0675#define ISP_BASE__INST2_SEG1 0676#define ISP_BASE__INST2_SEG2 0677#define ISP_BASE__INST2_SEG3 0678#define ISP_BASE__INST2_SEG4 0679680#define ISP_BASE__INST3_SEG0 0681#define ISP_BASE__INST3_SEG1 0682#define ISP_BASE__INST3_SEG2 0683#define ISP_BASE__INST3_SEG3 0684#define ISP_BASE__INST3_SEG4 0685686#define ISP_BASE__INST4_SEG0 0687#define ISP_BASE__INST4_SEG1 0688#define ISP_BASE__INST4_SEG2 0689#define ISP_BASE__INST4_SEG3 0690#define ISP_BASE__INST4_SEG4 0691692#define SYSTEMHUB_BASE__INST0_SEG0 0x00000EA0693#define SYSTEMHUB_BASE__INST0_SEG1 0694#define SYSTEMHUB_BASE__INST0_SEG2 0695#define SYSTEMHUB_BASE__INST0_SEG3 0696#define SYSTEMHUB_BASE__INST0_SEG4 0697698#define SYSTEMHUB_BASE__INST1_SEG0 0699#define SYSTEMHUB_BASE__INST1_SEG1 0700#define SYSTEMHUB_BASE__INST1_SEG2 0701#define SYSTEMHUB_BASE__INST1_SEG3 0702#define SYSTEMHUB_BASE__INST1_SEG4 0703704#define SYSTEMHUB_BASE__INST2_SEG0 0705#define SYSTEMHUB_BASE__INST2_SEG1 0706#define SYSTEMHUB_BASE__INST2_SEG2 0707#define SYSTEMHUB_BASE__INST2_SEG3 0708#define SYSTEMHUB_BASE__INST2_SEG4 0709710#define SYSTEMHUB_BASE__INST3_SEG0 0711#define SYSTEMHUB_BASE__INST3_SEG1 0712#define SYSTEMHUB_BASE__INST3_SEG2 0713#define SYSTEMHUB_BASE__INST3_SEG3 0714#define SYSTEMHUB_BASE__INST3_SEG4 0715716#define SYSTEMHUB_BASE__INST4_SEG0 0717#define SYSTEMHUB_BASE__INST4_SEG1 0718#define SYSTEMHUB_BASE__INST4_SEG2 0719#define SYSTEMHUB_BASE__INST4_SEG3 0720#define SYSTEMHUB_BASE__INST4_SEG4 0721722#define L2IMU_BASE__INST0_SEG0 0x00007DC0723#define L2IMU_BASE__INST0_SEG1 0724#define L2IMU_BASE__INST0_SEG2 0725#define L2IMU_BASE__INST0_SEG3 0726#define L2IMU_BASE__INST0_SEG4 0727728#define L2IMU_BASE__INST1_SEG0 0729#define L2IMU_BASE__INST1_SEG1 0730#define L2IMU_BASE__INST1_SEG2 0731#define L2IMU_BASE__INST1_SEG3 0732#define L2IMU_BASE__INST1_SEG4 0733734#define L2IMU_BASE__INST2_SEG0 0735#define L2IMU_BASE__INST2_SEG1 0736#define L2IMU_BASE__INST2_SEG2 0737#define L2IMU_BASE__INST2_SEG3 0738#define L2IMU_BASE__INST2_SEG4 0739740#define L2IMU_BASE__INST3_SEG0 0741#define L2IMU_BASE__INST3_SEG1 0742#define L2IMU_BASE__INST3_SEG2 0743#define L2IMU_BASE__INST3_SEG3 0744#define L2IMU_BASE__INST3_SEG4 0745746#define L2IMU_BASE__INST4_SEG0 0747#define L2IMU_BASE__INST4_SEG1 0748#define L2IMU_BASE__INST4_SEG2 0749#define L2IMU_BASE__INST4_SEG3 0750#define L2IMU_BASE__INST4_SEG4 0751752#define IOHC_BASE__INST0_SEG0 0x00010000753#define IOHC_BASE__INST0_SEG1 0754#define IOHC_BASE__INST0_SEG2 0755#define IOHC_BASE__INST0_SEG3 0756#define IOHC_BASE__INST0_SEG4 0757758#define IOHC_BASE__INST1_SEG0 0759#define IOHC_BASE__INST1_SEG1 0760#define IOHC_BASE__INST1_SEG2 0761#define IOHC_BASE__INST1_SEG3 0762#define IOHC_BASE__INST1_SEG4 0763764#define IOHC_BASE__INST2_SEG0 0765#define IOHC_BASE__INST2_SEG1 0766#define IOHC_BASE__INST2_SEG2 0767#define IOHC_BASE__INST2_SEG3 0768#define IOHC_BASE__INST2_SEG4 0769770#define IOHC_BASE__INST3_SEG0 0771#define IOHC_BASE__INST3_SEG1 0772#define IOHC_BASE__INST3_SEG2 0773#define IOHC_BASE__INST3_SEG3 0774#define IOHC_BASE__INST3_SEG4 0775776#define IOHC_BASE__INST4_SEG0 0777#define IOHC_BASE__INST4_SEG1 0778#define IOHC_BASE__INST4_SEG2 0779#define IOHC_BASE__INST4_SEG3 0780#define IOHC_BASE__INST4_SEG4 0781782#define ATHUB_BASE__INST0_SEG0 0x00000C20783#define ATHUB_BASE__INST0_SEG1 0784#define ATHUB_BASE__INST0_SEG2 0785#define ATHUB_BASE__INST0_SEG3 0786#define ATHUB_BASE__INST0_SEG4 0787788#define ATHUB_BASE__INST1_SEG0 0789#define ATHUB_BASE__INST1_SEG1 0790#define ATHUB_BASE__INST1_SEG2 0791#define ATHUB_BASE__INST1_SEG3 0792#define ATHUB_BASE__INST1_SEG4 0793794#define ATHUB_BASE__INST2_SEG0 0795#define ATHUB_BASE__INST2_SEG1 0796#define ATHUB_BASE__INST2_SEG2 0797#define ATHUB_BASE__INST2_SEG3 0798#define ATHUB_BASE__INST2_SEG4 0799800#define ATHUB_BASE__INST3_SEG0 0801#define ATHUB_BASE__INST3_SEG1 0802#define ATHUB_BASE__INST3_SEG2 0803#define ATHUB_BASE__INST3_SEG3 0804#define ATHUB_BASE__INST3_SEG4 0805806#define ATHUB_BASE__INST4_SEG0 0807#define ATHUB_BASE__INST4_SEG1 0808#define ATHUB_BASE__INST4_SEG2 0809#define ATHUB_BASE__INST4_SEG3 0810#define ATHUB_BASE__INST4_SEG4 0811812#define VCE_BASE__INST0_SEG0 0x00007E00813#define VCE_BASE__INST0_SEG1 0x00048800814#define VCE_BASE__INST0_SEG2 0815#define VCE_BASE__INST0_SEG3 0816#define VCE_BASE__INST0_SEG4 0817818#define VCE_BASE__INST1_SEG0 0819#define VCE_BASE__INST1_SEG1 0820#define VCE_BASE__INST1_SEG2 0821#define VCE_BASE__INST1_SEG3 0822#define VCE_BASE__INST1_SEG4 0823824#define VCE_BASE__INST2_SEG0 0825#define VCE_BASE__INST2_SEG1 0826#define VCE_BASE__INST2_SEG2 0827#define VCE_BASE__INST2_SEG3 0828#define VCE_BASE__INST2_SEG4 0829830#define VCE_BASE__INST3_SEG0 0831#define VCE_BASE__INST3_SEG1 0832#define VCE_BASE__INST3_SEG2 0833#define VCE_BASE__INST3_SEG3 0834#define VCE_BASE__INST3_SEG4 0835836#define VCE_BASE__INST4_SEG0 0837#define VCE_BASE__INST4_SEG1 0838#define VCE_BASE__INST4_SEG2 0839#define VCE_BASE__INST4_SEG3 0840#define VCE_BASE__INST4_SEG4 0841842#define GC_BASE__INST0_SEG0 0x00002000843#define GC_BASE__INST0_SEG1 0x0000A000844#define GC_BASE__INST0_SEG2 0845#define GC_BASE__INST0_SEG3 0846#define GC_BASE__INST0_SEG4 0847848#define GC_BASE__INST1_SEG0 0849#define GC_BASE__INST1_SEG1 0850#define GC_BASE__INST1_SEG2 0851#define GC_BASE__INST1_SEG3 0852#define GC_BASE__INST1_SEG4 0853854#define GC_BASE__INST2_SEG0 0855#define GC_BASE__INST2_SEG1 0856#define GC_BASE__INST2_SEG2 0857#define GC_BASE__INST2_SEG3 0858#define GC_BASE__INST2_SEG4 0859860#define GC_BASE__INST3_SEG0 0861#define GC_BASE__INST3_SEG1 0862#define GC_BASE__INST3_SEG2 0863#define GC_BASE__INST3_SEG3 0864#define GC_BASE__INST3_SEG4 0865866#define GC_BASE__INST4_SEG0 0867#define GC_BASE__INST4_SEG1 0868#define GC_BASE__INST4_SEG2 0869#define GC_BASE__INST4_SEG3 0870#define GC_BASE__INST4_SEG4 0871872#define MMHUB_BASE__INST0_SEG0 0x0001A000873#define MMHUB_BASE__INST0_SEG1 0874#define MMHUB_BASE__INST0_SEG2 0875#define MMHUB_BASE__INST0_SEG3 0876#define MMHUB_BASE__INST0_SEG4 0877878#define MMHUB_BASE__INST1_SEG0 0879#define MMHUB_BASE__INST1_SEG1 0880#define MMHUB_BASE__INST1_SEG2 0881#define MMHUB_BASE__INST1_SEG3 0882#define MMHUB_BASE__INST1_SEG4 0883884#define MMHUB_BASE__INST2_SEG0 0885#define MMHUB_BASE__INST2_SEG1 0886#define MMHUB_BASE__INST2_SEG2 0887#define MMHUB_BASE__INST2_SEG3 0888#define MMHUB_BASE__INST2_SEG4 0889890#define MMHUB_BASE__INST3_SEG0 0891#define MMHUB_BASE__INST3_SEG1 0892#define MMHUB_BASE__INST3_SEG2 0893#define MMHUB_BASE__INST3_SEG3 0894#define MMHUB_BASE__INST3_SEG4 0895896#define MMHUB_BASE__INST4_SEG0 0897#define MMHUB_BASE__INST4_SEG1 0898#define MMHUB_BASE__INST4_SEG2 0899#define MMHUB_BASE__INST4_SEG3 0900#define MMHUB_BASE__INST4_SEG4 0901902#define RSMU_BASE__INST0_SEG0 0x00012000903#define RSMU_BASE__INST0_SEG1 0904#define RSMU_BASE__INST0_SEG2 0905#define RSMU_BASE__INST0_SEG3 0906#define RSMU_BASE__INST0_SEG4 0907908#define RSMU_BASE__INST1_SEG0 0909#define RSMU_BASE__INST1_SEG1 0910#define RSMU_BASE__INST1_SEG2 0911#define RSMU_BASE__INST1_SEG3 0912#define RSMU_BASE__INST1_SEG4 0913914#define RSMU_BASE__INST2_SEG0 0915#define RSMU_BASE__INST2_SEG1 0916#define RSMU_BASE__INST2_SEG2 0917#define RSMU_BASE__INST2_SEG3 0918#define RSMU_BASE__INST2_SEG4 0919920#define RSMU_BASE__INST3_SEG0 0921#define RSMU_BASE__INST3_SEG1 0922#define RSMU_BASE__INST3_SEG2 0923#define RSMU_BASE__INST3_SEG3 0924#define RSMU_BASE__INST3_SEG4 0925926#define RSMU_BASE__INST4_SEG0 0927#define RSMU_BASE__INST4_SEG1 0928#define RSMU_BASE__INST4_SEG2 0929#define RSMU_BASE__INST4_SEG3 0930#define RSMU_BASE__INST4_SEG4 0931932#define HDP_BASE__INST0_SEG0 0x00000F20933#define HDP_BASE__INST0_SEG1 0934#define HDP_BASE__INST0_SEG2 0935#define HDP_BASE__INST0_SEG3 0936#define HDP_BASE__INST0_SEG4 0937938#define HDP_BASE__INST1_SEG0 0939#define HDP_BASE__INST1_SEG1 0940#define HDP_BASE__INST1_SEG2 0941#define HDP_BASE__INST1_SEG3 0942#define HDP_BASE__INST1_SEG4 0943944#define HDP_BASE__INST2_SEG0 0945#define HDP_BASE__INST2_SEG1 0946#define HDP_BASE__INST2_SEG2 0947#define HDP_BASE__INST2_SEG3 0948#define HDP_BASE__INST2_SEG4 0949950#define HDP_BASE__INST3_SEG0 0951#define HDP_BASE__INST3_SEG1 0952#define HDP_BASE__INST3_SEG2 0953#define HDP_BASE__INST3_SEG3 0954#define HDP_BASE__INST3_SEG4 0955956#define HDP_BASE__INST4_SEG0 0957#define HDP_BASE__INST4_SEG1 0958#define HDP_BASE__INST4_SEG2 0959#define HDP_BASE__INST4_SEG3 0960#define HDP_BASE__INST4_SEG4 0961962#define OSSSYS_BASE__INST0_SEG0 0x000010A0963#define OSSSYS_BASE__INST0_SEG1 0964#define OSSSYS_BASE__INST0_SEG2 0965#define OSSSYS_BASE__INST0_SEG3 0966#define OSSSYS_BASE__INST0_SEG4 0967968#define OSSSYS_BASE__INST1_SEG0 0969#define OSSSYS_BASE__INST1_SEG1 0970#define OSSSYS_BASE__INST1_SEG2 0971#define OSSSYS_BASE__INST1_SEG3 0972#define OSSSYS_BASE__INST1_SEG4 0973974#define OSSSYS_BASE__INST2_SEG0 0975#define OSSSYS_BASE__INST2_SEG1 0976#define OSSSYS_BASE__INST2_SEG2 0977#define OSSSYS_BASE__INST2_SEG3 0978#define OSSSYS_BASE__INST2_SEG4 0979980#define OSSSYS_BASE__INST3_SEG0 0981#define OSSSYS_BASE__INST3_SEG1 0982#define OSSSYS_BASE__INST3_SEG2 0983#define OSSSYS_BASE__INST3_SEG3 0984#define OSSSYS_BASE__INST3_SEG4 0985986#define OSSSYS_BASE__INST4_SEG0 0987#define OSSSYS_BASE__INST4_SEG1 0988#define OSSSYS_BASE__INST4_SEG2 0989#define OSSSYS_BASE__INST4_SEG3 0990#define OSSSYS_BASE__INST4_SEG4 0991992#define SDMA0_BASE__INST0_SEG0 0x00001260993#define SDMA0_BASE__INST0_SEG1 0994#define SDMA0_BASE__INST0_SEG2 0995#define SDMA0_BASE__INST0_SEG3 0996#define SDMA0_BASE__INST0_SEG4 0997998#define SDMA0_BASE__INST1_SEG0 0999#define SDMA0_BASE__INST1_SEG1 01000#define SDMA0_BASE__INST1_SEG2 01001#define SDMA0_BASE__INST1_SEG3 01002#define SDMA0_BASE__INST1_SEG4 010031004#define SDMA0_BASE__INST2_SEG0 01005#define SDMA0_BASE__INST2_SEG1 01006#define SDMA0_BASE__INST2_SEG2 01007#define SDMA0_BASE__INST2_SEG3 01008#define SDMA0_BASE__INST2_SEG4 010091010#define SDMA0_BASE__INST3_SEG0 01011#define SDMA0_BASE__INST3_SEG1 01012#define SDMA0_BASE__INST3_SEG2 01013#define SDMA0_BASE__INST3_SEG3 01014#define SDMA0_BASE__INST3_SEG4 010151016#define SDMA0_BASE__INST4_SEG0 01017#define SDMA0_BASE__INST4_SEG1 01018#define SDMA0_BASE__INST4_SEG2 01019#define SDMA0_BASE__INST4_SEG3 01020#define SDMA0_BASE__INST4_SEG4 010211022#define SDMA1_BASE__INST0_SEG0 0x000014601023#define SDMA1_BASE__INST0_SEG1 01024#define SDMA1_BASE__INST0_SEG2 01025#define SDMA1_BASE__INST0_SEG3 01026#define SDMA1_BASE__INST0_SEG4 010271028#define SDMA1_BASE__INST1_SEG0 01029#define SDMA1_BASE__INST1_SEG1 01030#define SDMA1_BASE__INST1_SEG2 01031#define SDMA1_BASE__INST1_SEG3 01032#define SDMA1_BASE__INST1_SEG4 010331034#define SDMA1_BASE__INST2_SEG0 01035#define SDMA1_BASE__INST2_SEG1 01036#define SDMA1_BASE__INST2_SEG2 01037#define SDMA1_BASE__INST2_SEG3 01038#define SDMA1_BASE__INST2_SEG4 010391040#define SDMA1_BASE__INST3_SEG0 01041#define SDMA1_BASE__INST3_SEG1 01042#define SDMA1_BASE__INST3_SEG2 01043#define SDMA1_BASE__INST3_SEG3 01044#define SDMA1_BASE__INST3_SEG4 010451046#define SDMA1_BASE__INST4_SEG0 01047#define SDMA1_BASE__INST4_SEG1 01048#define SDMA1_BASE__INST4_SEG2 01049#define SDMA1_BASE__INST4_SEG3 01050#define SDMA1_BASE__INST4_SEG4 010511052#define XDMA_BASE__INST0_SEG0 0x000034001053#define XDMA_BASE__INST0_SEG1 01054#define XDMA_BASE__INST0_SEG2 01055#define XDMA_BASE__INST0_SEG3 01056#define XDMA_BASE__INST0_SEG4 010571058#define XDMA_BASE__INST1_SEG0 01059#define XDMA_BASE__INST1_SEG1 01060#define XDMA_BASE__INST1_SEG2 01061#define XDMA_BASE__INST1_SEG3 01062#define XDMA_BASE__INST1_SEG4 010631064#define XDMA_BASE__INST2_SEG0 01065#define XDMA_BASE__INST2_SEG1 01066#define XDMA_BASE__INST2_SEG2 01067#define XDMA_BASE__INST2_SEG3 01068#define XDMA_BASE__INST2_SEG4 010691070#define XDMA_BASE__INST3_SEG0 01071#define XDMA_BASE__INST3_SEG1 01072#define XDMA_BASE__INST3_SEG2 01073#define XDMA_BASE__INST3_SEG3 01074#define XDMA_BASE__INST3_SEG4 010751076#define XDMA_BASE__INST4_SEG0 01077#define XDMA_BASE__INST4_SEG1 01078#define XDMA_BASE__INST4_SEG2 01079#define XDMA_BASE__INST4_SEG3 01080#define XDMA_BASE__INST4_SEG4 010811082#define UMC_BASE__INST0_SEG0 0x000140001083#define UMC_BASE__INST0_SEG1 01084#define UMC_BASE__INST0_SEG2 01085#define UMC_BASE__INST0_SEG3 01086#define UMC_BASE__INST0_SEG4 010871088#define UMC_BASE__INST1_SEG0 01089#define UMC_BASE__INST1_SEG1 01090#define UMC_BASE__INST1_SEG2 01091#define UMC_BASE__INST1_SEG3 01092#define UMC_BASE__INST1_SEG4 010931094#define UMC_BASE__INST2_SEG0 01095#define UMC_BASE__INST2_SEG1 01096#define UMC_BASE__INST2_SEG2 01097#define UMC_BASE__INST2_SEG3 01098#define UMC_BASE__INST2_SEG4 010991100#define UMC_BASE__INST3_SEG0 01101#define UMC_BASE__INST3_SEG1 01102#define UMC_BASE__INST3_SEG2 01103#define UMC_BASE__INST3_SEG3 01104#define UMC_BASE__INST3_SEG4 011051106#define UMC_BASE__INST4_SEG0 01107#define UMC_BASE__INST4_SEG1 01108#define UMC_BASE__INST4_SEG2 01109#define UMC_BASE__INST4_SEG3 01110#define UMC_BASE__INST4_SEG4 011111112#define THM_BASE__INST0_SEG0 0x000166001113#define THM_BASE__INST0_SEG1 01114#define THM_BASE__INST0_SEG2 01115#define THM_BASE__INST0_SEG3 01116#define THM_BASE__INST0_SEG4 011171118#define THM_BASE__INST1_SEG0 01119#define THM_BASE__INST1_SEG1 01120#define THM_BASE__INST1_SEG2 01121#define THM_BASE__INST1_SEG3 01122#define THM_BASE__INST1_SEG4 011231124#define THM_BASE__INST2_SEG0 01125#define THM_BASE__INST2_SEG1 01126#define THM_BASE__INST2_SEG2 01127#define THM_BASE__INST2_SEG3 01128#define THM_BASE__INST2_SEG4 011291130#define THM_BASE__INST3_SEG0 01131#define THM_BASE__INST3_SEG1 01132#define THM_BASE__INST3_SEG2 01133#define THM_BASE__INST3_SEG3 01134#define THM_BASE__INST3_SEG4 011351136#define THM_BASE__INST4_SEG0 01137#define THM_BASE__INST4_SEG1 01138#define THM_BASE__INST4_SEG2 01139#define THM_BASE__INST4_SEG3 01140#define THM_BASE__INST4_SEG4 011411142#define SMUIO_BASE__INST0_SEG0 0x000168001143#define SMUIO_BASE__INST0_SEG1 01144#define SMUIO_BASE__INST0_SEG2 01145#define SMUIO_BASE__INST0_SEG3 01146#define SMUIO_BASE__INST0_SEG4 011471148#define SMUIO_BASE__INST1_SEG0 01149#define SMUIO_BASE__INST1_SEG1 01150#define SMUIO_BASE__INST1_SEG2 01151#define SMUIO_BASE__INST1_SEG3 01152#define SMUIO_BASE__INST1_SEG4 011531154#define SMUIO_BASE__INST2_SEG0 01155#define SMUIO_BASE__INST2_SEG1 01156#define SMUIO_BASE__INST2_SEG2 01157#define SMUIO_BASE__INST2_SEG3 01158#define SMUIO_BASE__INST2_SEG4 011591160#define SMUIO_BASE__INST3_SEG0 01161#define SMUIO_BASE__INST3_SEG1 01162#define SMUIO_BASE__INST3_SEG2 01163#define SMUIO_BASE__INST3_SEG3 01164#define SMUIO_BASE__INST3_SEG4 011651166#define SMUIO_BASE__INST4_SEG0 01167#define SMUIO_BASE__INST4_SEG1 01168#define SMUIO_BASE__INST4_SEG2 01169#define SMUIO_BASE__INST4_SEG3 01170#define SMUIO_BASE__INST4_SEG4 011711172#define PWR_BASE__INST0_SEG0 0x00016A001173#define PWR_BASE__INST0_SEG1 01174#define PWR_BASE__INST0_SEG2 01175#define PWR_BASE__INST0_SEG3 01176#define PWR_BASE__INST0_SEG4 011771178#define PWR_BASE__INST1_SEG0 01179#define PWR_BASE__INST1_SEG1 01180#define PWR_BASE__INST1_SEG2 01181#define PWR_BASE__INST1_SEG3 01182#define PWR_BASE__INST1_SEG4 011831184#define PWR_BASE__INST2_SEG0 01185#define PWR_BASE__INST2_SEG1 01186#define PWR_BASE__INST2_SEG2 01187#define PWR_BASE__INST2_SEG3 01188#define PWR_BASE__INST2_SEG4 011891190#define PWR_BASE__INST3_SEG0 01191#define PWR_BASE__INST3_SEG1 01192#define PWR_BASE__INST3_SEG2 01193#define PWR_BASE__INST3_SEG3 01194#define PWR_BASE__INST3_SEG4 011951196#define PWR_BASE__INST4_SEG0 01197#define PWR_BASE__INST4_SEG1 01198#define PWR_BASE__INST4_SEG2 01199#define PWR_BASE__INST4_SEG3 01200#define PWR_BASE__INST4_SEG4 012011202#define CLK_BASE__INST0_SEG0 0x00016C001203#define CLK_BASE__INST0_SEG1 01204#define CLK_BASE__INST0_SEG2 01205#define CLK_BASE__INST0_SEG3 01206#define CLK_BASE__INST0_SEG4 012071208#define CLK_BASE__INST1_SEG0 0x00016E001209#define CLK_BASE__INST1_SEG1 01210#define CLK_BASE__INST1_SEG2 01211#define CLK_BASE__INST1_SEG3 01212#define CLK_BASE__INST1_SEG4 012131214#define CLK_BASE__INST2_SEG0 0x000170001215#define CLK_BASE__INST2_SEG1 01216#define CLK_BASE__INST2_SEG2 01217#define CLK_BASE__INST2_SEG3 01218#define CLK_BASE__INST2_SEG4 012191220#define CLK_BASE__INST3_SEG0 0x000172001221#define CLK_BASE__INST3_SEG1 01222#define CLK_BASE__INST3_SEG2 01223#define CLK_BASE__INST3_SEG3 01224#define CLK_BASE__INST3_SEG4 012251226#define CLK_BASE__INST4_SEG0 0x00017E001227#define CLK_BASE__INST4_SEG1 01228#define CLK_BASE__INST4_SEG2 01229#define CLK_BASE__INST4_SEG3 01230#define CLK_BASE__INST4_SEG4 012311232#define FUSE_BASE__INST0_SEG0 0x000174001233#define FUSE_BASE__INST0_SEG1 01234#define FUSE_BASE__INST0_SEG2 01235#define FUSE_BASE__INST0_SEG3 01236#define FUSE_BASE__INST0_SEG4 012371238#define FUSE_BASE__INST1_SEG0 01239#define FUSE_BASE__INST1_SEG1 01240#define FUSE_BASE__INST1_SEG2 01241#define FUSE_BASE__INST1_SEG3 01242#define FUSE_BASE__INST1_SEG4 012431244#define FUSE_BASE__INST2_SEG0 01245#define FUSE_BASE__INST2_SEG1 01246#define FUSE_BASE__INST2_SEG2 01247#define FUSE_BASE__INST2_SEG3 01248#define FUSE_BASE__INST2_SEG4 012491250#define FUSE_BASE__INST3_SEG0 01251#define FUSE_BASE__INST3_SEG1 01252#define FUSE_BASE__INST3_SEG2 01253#define FUSE_BASE__INST3_SEG3 01254#define FUSE_BASE__INST3_SEG4 012551256#define FUSE_BASE__INST4_SEG0 01257#define FUSE_BASE__INST4_SEG1 01258#define FUSE_BASE__INST4_SEG2 01259#define FUSE_BASE__INST4_SEG3 01260#define FUSE_BASE__INST4_SEG4 01261#endif1262126312641265