Path: blob/master/drivers/gpu/drm/amd/include/vega20_ip_offset.h
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/*1* Copyright (C) 2018 Advanced Micro Devices, Inc.2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice shall be included11* in all copies or substantial portions of the Software.12*13* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS14* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,15* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL16* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN17* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN18* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.19*/20#ifndef _vega20_ip_offset_HEADER21#define _vega20_ip_offset_HEADER2223#define MAX_INSTANCE 624#define MAX_SEGMENT 6252627struct IP_BASE_INSTANCE {28unsigned int segment[MAX_SEGMENT];29};3031struct IP_BASE {32struct IP_BASE_INSTANCE instance[MAX_INSTANCE];33} __maybe_unused;343536static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0, 0, 0, 0, 0 } },37{ { 0, 0, 0, 0, 0, 0 } },38{ { 0, 0, 0, 0, 0, 0 } },39{ { 0, 0, 0, 0, 0, 0 } },40{ { 0, 0, 0, 0, 0, 0 } },41{ { 0, 0, 0, 0, 0, 0 } } } };42static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017200, 0x0001B000, 0x0001B200 } },43{ { 0, 0, 0, 0, 0, 0 } },44{ { 0, 0, 0, 0, 0, 0 } },45{ { 0, 0, 0, 0, 0, 0 } },46{ { 0, 0, 0, 0, 0, 0 } },47{ { 0, 0, 0, 0, 0, 0 } } } };48static const struct IP_BASE DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0, 0 } },49{ { 0, 0, 0, 0, 0, 0 } },50{ { 0, 0, 0, 0, 0, 0 } },51{ { 0, 0, 0, 0, 0, 0 } },52{ { 0, 0, 0, 0, 0, 0 } },53{ { 0, 0, 0, 0, 0, 0 } } } };54static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0, 0, 0, 0, 0 } },55{ { 0, 0, 0, 0, 0, 0 } },56{ { 0, 0, 0, 0, 0, 0 } },57{ { 0, 0, 0, 0, 0, 0 } },58{ { 0, 0, 0, 0, 0, 0 } },59{ { 0, 0, 0, 0, 0, 0 } } } };60static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0, 0, 0, 0, 0 } },61{ { 0, 0, 0, 0, 0, 0 } },62{ { 0, 0, 0, 0, 0, 0 } },63{ { 0, 0, 0, 0, 0, 0 } },64{ { 0, 0, 0, 0, 0, 0 } },65{ { 0, 0, 0, 0, 0, 0 } } } };66static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0, 0, 0, 0 } },67{ { 0, 0, 0, 0, 0, 0 } },68{ { 0, 0, 0, 0, 0, 0 } },69{ { 0, 0, 0, 0, 0, 0 } },70{ { 0, 0, 0, 0, 0, 0 } },71{ { 0, 0, 0, 0, 0, 0 } } } };72static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0, 0, 0, 0, 0 } },73{ { 0, 0, 0, 0, 0, 0 } },74{ { 0, 0, 0, 0, 0, 0 } },75{ { 0, 0, 0, 0, 0, 0 } },76{ { 0, 0, 0, 0, 0, 0 } },77{ { 0, 0, 0, 0, 0, 0 } } } };78static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0, 0 } },79{ { 0, 0, 0, 0, 0, 0 } },80{ { 0, 0, 0, 0, 0, 0 } },81{ { 0, 0, 0, 0, 0, 0 } },82{ { 0, 0, 0, 0, 0, 0 } },83{ { 0, 0, 0, 0, 0, 0 } } } };84static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0, 0 } },85{ { 0, 0, 0, 0, 0, 0 } },86{ { 0, 0, 0, 0, 0, 0 } },87{ { 0, 0, 0, 0, 0, 0 } },88{ { 0, 0, 0, 0, 0, 0 } },89{ { 0, 0, 0, 0, 0, 0 } } } };90static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0, 0 } },91{ { 0, 0, 0, 0, 0, 0 } },92{ { 0, 0, 0, 0, 0, 0 } },93{ { 0, 0, 0, 0, 0, 0 } },94{ { 0, 0, 0, 0, 0, 0 } },95{ { 0, 0, 0, 0, 0, 0 } } } };96static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } },97{ { 0, 0, 0, 0, 0, 0 } },98{ { 0, 0, 0, 0, 0, 0 } },99{ { 0, 0, 0, 0, 0, 0 } },100{ { 0, 0, 0, 0, 0, 0 } },101{ { 0, 0, 0, 0, 0, 0 } } } };102static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0, 0, 0, 0, 0 } },103{ { 0, 0, 0, 0, 0, 0 } },104{ { 0, 0, 0, 0, 0, 0 } },105{ { 0, 0, 0, 0, 0, 0 } },106{ { 0, 0, 0, 0, 0, 0 } },107{ { 0, 0, 0, 0, 0, 0 } } } };108static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0, 0, 0, 0, 0 } },109{ { 0, 0, 0, 0, 0, 0 } },110{ { 0, 0, 0, 0, 0, 0 } },111{ { 0, 0, 0, 0, 0, 0 } },112{ { 0, 0, 0, 0, 0, 0 } },113{ { 0, 0, 0, 0, 0, 0 } } } };114static const struct IP_BASE SDMA1_BASE = { { { { 0x00001860, 0, 0, 0, 0, 0 } },115{ { 0, 0, 0, 0, 0, 0 } },116{ { 0, 0, 0, 0, 0, 0 } },117{ { 0, 0, 0, 0, 0, 0 } },118{ { 0, 0, 0, 0, 0, 0 } },119{ { 0, 0, 0, 0, 0, 0 } } } };120static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } },121{ { 0, 0, 0, 0, 0, 0 } },122{ { 0, 0, 0, 0, 0, 0 } },123{ { 0, 0, 0, 0, 0, 0 } },124{ { 0, 0, 0, 0, 0, 0 } },125{ { 0, 0, 0, 0, 0, 0 } } } };126static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0, 0, 0, 0, 0 } },127{ { 0, 0, 0, 0, 0, 0 } },128{ { 0, 0, 0, 0, 0, 0 } },129{ { 0, 0, 0, 0, 0, 0 } },130{ { 0, 0, 0, 0, 0, 0 } },131{ { 0, 0, 0, 0, 0, 0 } } } };132static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0, 0, 0, 0, 0 } },133{ { 0, 0, 0, 0, 0, 0 } },134{ { 0, 0, 0, 0, 0, 0 } },135{ { 0, 0, 0, 0, 0, 0 } },136{ { 0, 0, 0, 0, 0, 0 } },137{ { 0, 0, 0, 0, 0, 0 } } } };138static const struct IP_BASE UVD_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0, 0 } },139{ { 0, 0x00009000, 0, 0, 0, 0 } },140{ { 0, 0, 0, 0, 0, 0 } },141{ { 0, 0, 0, 0, 0, 0 } },142{ { 0, 0, 0, 0, 0, 0 } },143{ { 0, 0, 0, 0, 0, 0 } } } };144/* Adjust VCE_BASE to make vce_4_1 use vce_4_0 offset header files*/145static const struct IP_BASE VCE_BASE = { { { { 0x00007E00/* 0x00008800 */, 0, 0, 0, 0, 0 } },146{ { 0, 0, 0, 0, 0, 0 } },147{ { 0, 0, 0, 0, 0, 0 } },148{ { 0, 0, 0, 0, 0, 0 } },149{ { 0, 0, 0, 0, 0, 0 } },150{ { 0, 0, 0, 0, 0, 0 } } } };151static const struct IP_BASE XDMA_BASE = { { { { 0x00003400, 0, 0, 0, 0, 0 } },152{ { 0, 0, 0, 0, 0, 0 } },153{ { 0, 0, 0, 0, 0, 0 } },154{ { 0, 0, 0, 0, 0, 0 } },155{ { 0, 0, 0, 0, 0, 0 } },156{ { 0, 0, 0, 0, 0, 0 } } } };157static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0, 0 } },158{ { 0, 0, 0, 0, 0, 0 } },159{ { 0, 0, 0, 0, 0, 0 } },160{ { 0, 0, 0, 0, 0, 0 } },161{ { 0, 0, 0, 0, 0, 0 } },162{ { 0, 0, 0, 0, 0, 0 } } } };163164165#define ATHUB_BASE__INST0_SEG0 0x00000C20166#define ATHUB_BASE__INST0_SEG1 0167#define ATHUB_BASE__INST0_SEG2 0168#define ATHUB_BASE__INST0_SEG3 0169#define ATHUB_BASE__INST0_SEG4 0170#define ATHUB_BASE__INST0_SEG5 0171172#define ATHUB_BASE__INST1_SEG0 0173#define ATHUB_BASE__INST1_SEG1 0174#define ATHUB_BASE__INST1_SEG2 0175#define ATHUB_BASE__INST1_SEG3 0176#define ATHUB_BASE__INST1_SEG4 0177#define ATHUB_BASE__INST1_SEG5 0178179#define ATHUB_BASE__INST2_SEG0 0180#define ATHUB_BASE__INST2_SEG1 0181#define ATHUB_BASE__INST2_SEG2 0182#define ATHUB_BASE__INST2_SEG3 0183#define ATHUB_BASE__INST2_SEG4 0184#define ATHUB_BASE__INST2_SEG5 0185186#define ATHUB_BASE__INST3_SEG0 0187#define ATHUB_BASE__INST3_SEG1 0188#define ATHUB_BASE__INST3_SEG2 0189#define ATHUB_BASE__INST3_SEG3 0190#define ATHUB_BASE__INST3_SEG4 0191#define ATHUB_BASE__INST3_SEG5 0192193#define ATHUB_BASE__INST4_SEG0 0194#define ATHUB_BASE__INST4_SEG1 0195#define ATHUB_BASE__INST4_SEG2 0196#define ATHUB_BASE__INST4_SEG3 0197#define ATHUB_BASE__INST4_SEG4 0198#define ATHUB_BASE__INST4_SEG5 0199200#define ATHUB_BASE__INST5_SEG0 0201#define ATHUB_BASE__INST5_SEG1 0202#define ATHUB_BASE__INST5_SEG2 0203#define ATHUB_BASE__INST5_SEG3 0204#define ATHUB_BASE__INST5_SEG4 0205#define ATHUB_BASE__INST5_SEG5 0206207#define CLK_BASE__INST0_SEG0 0x00016C00208#define CLK_BASE__INST0_SEG1 0x00016E00209#define CLK_BASE__INST0_SEG2 0x00017000210#define CLK_BASE__INST0_SEG3 0x00017200211#define CLK_BASE__INST0_SEG4 0x0001B000212#define CLK_BASE__INST0_SEG5 0x0001B200213214#define CLK_BASE__INST1_SEG0 0215#define CLK_BASE__INST1_SEG1 0216#define CLK_BASE__INST1_SEG2 0217#define CLK_BASE__INST1_SEG3 0218#define CLK_BASE__INST1_SEG4 0219#define CLK_BASE__INST1_SEG5 0220221#define CLK_BASE__INST2_SEG0 0222#define CLK_BASE__INST2_SEG1 0223#define CLK_BASE__INST2_SEG2 0224#define CLK_BASE__INST2_SEG3 0225#define CLK_BASE__INST2_SEG4 0226#define CLK_BASE__INST2_SEG5 0227228#define CLK_BASE__INST3_SEG0 0229#define CLK_BASE__INST3_SEG1 0230#define CLK_BASE__INST3_SEG2 0231#define CLK_BASE__INST3_SEG3 0232#define CLK_BASE__INST3_SEG4 0233#define CLK_BASE__INST3_SEG5 0234235#define CLK_BASE__INST4_SEG0 0236#define CLK_BASE__INST4_SEG1 0237#define CLK_BASE__INST4_SEG2 0238#define CLK_BASE__INST4_SEG3 0239#define CLK_BASE__INST4_SEG4 0240#define CLK_BASE__INST4_SEG5 0241242#define CLK_BASE__INST5_SEG0 0243#define CLK_BASE__INST5_SEG1 0244#define CLK_BASE__INST5_SEG2 0245#define CLK_BASE__INST5_SEG3 0246#define CLK_BASE__INST5_SEG4 0247#define CLK_BASE__INST5_SEG5 0248249#define DCE_BASE__INST0_SEG0 0x00000012250#define DCE_BASE__INST0_SEG1 0x000000C0251#define DCE_BASE__INST0_SEG2 0x000034C0252#define DCE_BASE__INST0_SEG3 0253#define DCE_BASE__INST0_SEG4 0254#define DCE_BASE__INST0_SEG5 0255256#define DCE_BASE__INST1_SEG0 0257#define DCE_BASE__INST1_SEG1 0258#define DCE_BASE__INST1_SEG2 0259#define DCE_BASE__INST1_SEG3 0260#define DCE_BASE__INST1_SEG4 0261#define DCE_BASE__INST1_SEG5 0262263#define DCE_BASE__INST2_SEG0 0264#define DCE_BASE__INST2_SEG1 0265#define DCE_BASE__INST2_SEG2 0266#define DCE_BASE__INST2_SEG3 0267#define DCE_BASE__INST2_SEG4 0268#define DCE_BASE__INST2_SEG5 0269270#define DCE_BASE__INST3_SEG0 0271#define DCE_BASE__INST3_SEG1 0272#define DCE_BASE__INST3_SEG2 0273#define DCE_BASE__INST3_SEG3 0274#define DCE_BASE__INST3_SEG4 0275#define DCE_BASE__INST3_SEG5 0276277#define DCE_BASE__INST4_SEG0 0278#define DCE_BASE__INST4_SEG1 0279#define DCE_BASE__INST4_SEG2 0280#define DCE_BASE__INST4_SEG3 0281#define DCE_BASE__INST4_SEG4 0282#define DCE_BASE__INST4_SEG5 0283284#define DCE_BASE__INST5_SEG0 0285#define DCE_BASE__INST5_SEG1 0286#define DCE_BASE__INST5_SEG2 0287#define DCE_BASE__INST5_SEG3 0288#define DCE_BASE__INST5_SEG4 0289#define DCE_BASE__INST5_SEG5 0290291#define DF_BASE__INST0_SEG0 0x00007000292#define DF_BASE__INST0_SEG1 0293#define DF_BASE__INST0_SEG2 0294#define DF_BASE__INST0_SEG3 0295#define DF_BASE__INST0_SEG4 0296#define DF_BASE__INST0_SEG5 0297298#define DF_BASE__INST1_SEG0 0299#define DF_BASE__INST1_SEG1 0300#define DF_BASE__INST1_SEG2 0301#define DF_BASE__INST1_SEG3 0302#define DF_BASE__INST1_SEG4 0303#define DF_BASE__INST1_SEG5 0304305#define DF_BASE__INST2_SEG0 0306#define DF_BASE__INST2_SEG1 0307#define DF_BASE__INST2_SEG2 0308#define DF_BASE__INST2_SEG3 0309#define DF_BASE__INST2_SEG4 0310#define DF_BASE__INST2_SEG5 0311312#define DF_BASE__INST3_SEG0 0313#define DF_BASE__INST3_SEG1 0314#define DF_BASE__INST3_SEG2 0315#define DF_BASE__INST3_SEG3 0316#define DF_BASE__INST3_SEG4 0317#define DF_BASE__INST3_SEG5 0318319#define DF_BASE__INST4_SEG0 0320#define DF_BASE__INST4_SEG1 0321#define DF_BASE__INST4_SEG2 0322#define DF_BASE__INST4_SEG3 0323#define DF_BASE__INST4_SEG4 0324#define DF_BASE__INST4_SEG5 0325326#define DF_BASE__INST5_SEG0 0327#define DF_BASE__INST5_SEG1 0328#define DF_BASE__INST5_SEG2 0329#define DF_BASE__INST5_SEG3 0330#define DF_BASE__INST5_SEG4 0331#define DF_BASE__INST5_SEG5 0332333#define FUSE_BASE__INST0_SEG0 0x00017400334#define FUSE_BASE__INST0_SEG1 0335#define FUSE_BASE__INST0_SEG2 0336#define FUSE_BASE__INST0_SEG3 0337#define FUSE_BASE__INST0_SEG4 0338#define FUSE_BASE__INST0_SEG5 0339340#define FUSE_BASE__INST1_SEG0 0341#define FUSE_BASE__INST1_SEG1 0342#define FUSE_BASE__INST1_SEG2 0343#define FUSE_BASE__INST1_SEG3 0344#define FUSE_BASE__INST1_SEG4 0345#define FUSE_BASE__INST1_SEG5 0346347#define FUSE_BASE__INST2_SEG0 0348#define FUSE_BASE__INST2_SEG1 0349#define FUSE_BASE__INST2_SEG2 0350#define FUSE_BASE__INST2_SEG3 0351#define FUSE_BASE__INST2_SEG4 0352#define FUSE_BASE__INST2_SEG5 0353354#define FUSE_BASE__INST3_SEG0 0355#define FUSE_BASE__INST3_SEG1 0356#define FUSE_BASE__INST3_SEG2 0357#define FUSE_BASE__INST3_SEG3 0358#define FUSE_BASE__INST3_SEG4 0359#define FUSE_BASE__INST3_SEG5 0360361#define FUSE_BASE__INST4_SEG0 0362#define FUSE_BASE__INST4_SEG1 0363#define FUSE_BASE__INST4_SEG2 0364#define FUSE_BASE__INST4_SEG3 0365#define FUSE_BASE__INST4_SEG4 0366#define FUSE_BASE__INST4_SEG5 0367368#define FUSE_BASE__INST5_SEG0 0369#define FUSE_BASE__INST5_SEG1 0370#define FUSE_BASE__INST5_SEG2 0371#define FUSE_BASE__INST5_SEG3 0372#define FUSE_BASE__INST5_SEG4 0373#define FUSE_BASE__INST5_SEG5 0374375#define GC_BASE__INST0_SEG0 0x00002000376#define GC_BASE__INST0_SEG1 0x0000A000377#define GC_BASE__INST0_SEG2 0378#define GC_BASE__INST0_SEG3 0379#define GC_BASE__INST0_SEG4 0380#define GC_BASE__INST0_SEG5 0381382#define GC_BASE__INST1_SEG0 0383#define GC_BASE__INST1_SEG1 0384#define GC_BASE__INST1_SEG2 0385#define GC_BASE__INST1_SEG3 0386#define GC_BASE__INST1_SEG4 0387#define GC_BASE__INST1_SEG5 0388389#define GC_BASE__INST2_SEG0 0390#define GC_BASE__INST2_SEG1 0391#define GC_BASE__INST2_SEG2 0392#define GC_BASE__INST2_SEG3 0393#define GC_BASE__INST2_SEG4 0394#define GC_BASE__INST2_SEG5 0395396#define GC_BASE__INST3_SEG0 0397#define GC_BASE__INST3_SEG1 0398#define GC_BASE__INST3_SEG2 0399#define GC_BASE__INST3_SEG3 0400#define GC_BASE__INST3_SEG4 0401#define GC_BASE__INST3_SEG5 0402403#define GC_BASE__INST4_SEG0 0404#define GC_BASE__INST4_SEG1 0405#define GC_BASE__INST4_SEG2 0406#define GC_BASE__INST4_SEG3 0407#define GC_BASE__INST4_SEG4 0408#define GC_BASE__INST4_SEG5 0409410#define GC_BASE__INST5_SEG0 0411#define GC_BASE__INST5_SEG1 0412#define GC_BASE__INST5_SEG2 0413#define GC_BASE__INST5_SEG3 0414#define GC_BASE__INST5_SEG4 0415#define GC_BASE__INST5_SEG5 0416417#define HDP_BASE__INST0_SEG0 0x00000F20418#define HDP_BASE__INST0_SEG1 0419#define HDP_BASE__INST0_SEG2 0420#define HDP_BASE__INST0_SEG3 0421#define HDP_BASE__INST0_SEG4 0422#define HDP_BASE__INST0_SEG5 0423424#define HDP_BASE__INST1_SEG0 0425#define HDP_BASE__INST1_SEG1 0426#define HDP_BASE__INST1_SEG2 0427#define HDP_BASE__INST1_SEG3 0428#define HDP_BASE__INST1_SEG4 0429#define HDP_BASE__INST1_SEG5 0430431#define HDP_BASE__INST2_SEG0 0432#define HDP_BASE__INST2_SEG1 0433#define HDP_BASE__INST2_SEG2 0434#define HDP_BASE__INST2_SEG3 0435#define HDP_BASE__INST2_SEG4 0436#define HDP_BASE__INST2_SEG5 0437438#define HDP_BASE__INST3_SEG0 0439#define HDP_BASE__INST3_SEG1 0440#define HDP_BASE__INST3_SEG2 0441#define HDP_BASE__INST3_SEG3 0442#define HDP_BASE__INST3_SEG4 0443#define HDP_BASE__INST3_SEG5 0444445#define HDP_BASE__INST4_SEG0 0446#define HDP_BASE__INST4_SEG1 0447#define HDP_BASE__INST4_SEG2 0448#define HDP_BASE__INST4_SEG3 0449#define HDP_BASE__INST4_SEG4 0450#define HDP_BASE__INST4_SEG5 0451452#define HDP_BASE__INST5_SEG0 0453#define HDP_BASE__INST5_SEG1 0454#define HDP_BASE__INST5_SEG2 0455#define HDP_BASE__INST5_SEG3 0456#define HDP_BASE__INST5_SEG4 0457#define HDP_BASE__INST5_SEG5 0458459#define MMHUB_BASE__INST0_SEG0 0x0001A000460#define MMHUB_BASE__INST0_SEG1 0461#define MMHUB_BASE__INST0_SEG2 0462#define MMHUB_BASE__INST0_SEG3 0463#define MMHUB_BASE__INST0_SEG4 0464#define MMHUB_BASE__INST0_SEG5 0465466#define MMHUB_BASE__INST1_SEG0 0467#define MMHUB_BASE__INST1_SEG1 0468#define MMHUB_BASE__INST1_SEG2 0469#define MMHUB_BASE__INST1_SEG3 0470#define MMHUB_BASE__INST1_SEG4 0471#define MMHUB_BASE__INST1_SEG5 0472473#define MMHUB_BASE__INST2_SEG0 0474#define MMHUB_BASE__INST2_SEG1 0475#define MMHUB_BASE__INST2_SEG2 0476#define MMHUB_BASE__INST2_SEG3 0477#define MMHUB_BASE__INST2_SEG4 0478#define MMHUB_BASE__INST2_SEG5 0479480#define MMHUB_BASE__INST3_SEG0 0481#define MMHUB_BASE__INST3_SEG1 0482#define MMHUB_BASE__INST3_SEG2 0483#define MMHUB_BASE__INST3_SEG3 0484#define MMHUB_BASE__INST3_SEG4 0485#define MMHUB_BASE__INST3_SEG5 0486487#define MMHUB_BASE__INST4_SEG0 0488#define MMHUB_BASE__INST4_SEG1 0489#define MMHUB_BASE__INST4_SEG2 0490#define MMHUB_BASE__INST4_SEG3 0491#define MMHUB_BASE__INST4_SEG4 0492#define MMHUB_BASE__INST4_SEG5 0493494#define MMHUB_BASE__INST5_SEG0 0495#define MMHUB_BASE__INST5_SEG1 0496#define MMHUB_BASE__INST5_SEG2 0497#define MMHUB_BASE__INST5_SEG3 0498#define MMHUB_BASE__INST5_SEG4 0499#define MMHUB_BASE__INST5_SEG5 0500501#define MP0_BASE__INST0_SEG0 0x00016000502#define MP0_BASE__INST0_SEG1 0503#define MP0_BASE__INST0_SEG2 0504#define MP0_BASE__INST0_SEG3 0505#define MP0_BASE__INST0_SEG4 0506#define MP0_BASE__INST0_SEG5 0507508#define MP0_BASE__INST1_SEG0 0509#define MP0_BASE__INST1_SEG1 0510#define MP0_BASE__INST1_SEG2 0511#define MP0_BASE__INST1_SEG3 0512#define MP0_BASE__INST1_SEG4 0513#define MP0_BASE__INST1_SEG5 0514515#define MP0_BASE__INST2_SEG0 0516#define MP0_BASE__INST2_SEG1 0517#define MP0_BASE__INST2_SEG2 0518#define MP0_BASE__INST2_SEG3 0519#define MP0_BASE__INST2_SEG4 0520#define MP0_BASE__INST2_SEG5 0521522#define MP0_BASE__INST3_SEG0 0523#define MP0_BASE__INST3_SEG1 0524#define MP0_BASE__INST3_SEG2 0525#define MP0_BASE__INST3_SEG3 0526#define MP0_BASE__INST3_SEG4 0527#define MP0_BASE__INST3_SEG5 0528529#define MP0_BASE__INST4_SEG0 0530#define MP0_BASE__INST4_SEG1 0531#define MP0_BASE__INST4_SEG2 0532#define MP0_BASE__INST4_SEG3 0533#define MP0_BASE__INST4_SEG4 0534#define MP0_BASE__INST4_SEG5 0535536#define MP0_BASE__INST5_SEG0 0537#define MP0_BASE__INST5_SEG1 0538#define MP0_BASE__INST5_SEG2 0539#define MP0_BASE__INST5_SEG3 0540#define MP0_BASE__INST5_SEG4 0541#define MP0_BASE__INST5_SEG5 0542543#define MP1_BASE__INST0_SEG0 0x00016000544#define MP1_BASE__INST0_SEG1 0545#define MP1_BASE__INST0_SEG2 0546#define MP1_BASE__INST0_SEG3 0547#define MP1_BASE__INST0_SEG4 0548#define MP1_BASE__INST0_SEG5 0549550#define MP1_BASE__INST1_SEG0 0551#define MP1_BASE__INST1_SEG1 0552#define MP1_BASE__INST1_SEG2 0553#define MP1_BASE__INST1_SEG3 0554#define MP1_BASE__INST1_SEG4 0555#define MP1_BASE__INST1_SEG5 0556557#define MP1_BASE__INST2_SEG0 0558#define MP1_BASE__INST2_SEG1 0559#define MP1_BASE__INST2_SEG2 0560#define MP1_BASE__INST2_SEG3 0561#define MP1_BASE__INST2_SEG4 0562#define MP1_BASE__INST2_SEG5 0563564#define MP1_BASE__INST3_SEG0 0565#define MP1_BASE__INST3_SEG1 0566#define MP1_BASE__INST3_SEG2 0567#define MP1_BASE__INST3_SEG3 0568#define MP1_BASE__INST3_SEG4 0569#define MP1_BASE__INST3_SEG5 0570571#define MP1_BASE__INST4_SEG0 0572#define MP1_BASE__INST4_SEG1 0573#define MP1_BASE__INST4_SEG2 0574#define MP1_BASE__INST4_SEG3 0575#define MP1_BASE__INST4_SEG4 0576#define MP1_BASE__INST4_SEG5 0577578#define MP1_BASE__INST5_SEG0 0579#define MP1_BASE__INST5_SEG1 0580#define MP1_BASE__INST5_SEG2 0581#define MP1_BASE__INST5_SEG3 0582#define MP1_BASE__INST5_SEG4 0583#define MP1_BASE__INST5_SEG5 0584585#define NBIO_BASE__INST0_SEG0 0x00000000586#define NBIO_BASE__INST0_SEG1 0x00000014587#define NBIO_BASE__INST0_SEG2 0x00000D20588#define NBIO_BASE__INST0_SEG3 0x00010400589#define NBIO_BASE__INST0_SEG4 0590#define NBIO_BASE__INST0_SEG5 0591592#define NBIO_BASE__INST1_SEG0 0593#define NBIO_BASE__INST1_SEG1 0594#define NBIO_BASE__INST1_SEG2 0595#define NBIO_BASE__INST1_SEG3 0596#define NBIO_BASE__INST1_SEG4 0597#define NBIO_BASE__INST1_SEG5 0598599#define NBIO_BASE__INST2_SEG0 0600#define NBIO_BASE__INST2_SEG1 0601#define NBIO_BASE__INST2_SEG2 0602#define NBIO_BASE__INST2_SEG3 0603#define NBIO_BASE__INST2_SEG4 0604#define NBIO_BASE__INST2_SEG5 0605606#define NBIO_BASE__INST3_SEG0 0607#define NBIO_BASE__INST3_SEG1 0608#define NBIO_BASE__INST3_SEG2 0609#define NBIO_BASE__INST3_SEG3 0610#define NBIO_BASE__INST3_SEG4 0611#define NBIO_BASE__INST3_SEG5 0612613#define NBIO_BASE__INST4_SEG0 0614#define NBIO_BASE__INST4_SEG1 0615#define NBIO_BASE__INST4_SEG2 0616#define NBIO_BASE__INST4_SEG3 0617#define NBIO_BASE__INST4_SEG4 0618#define NBIO_BASE__INST4_SEG5 0619620#define NBIO_BASE__INST5_SEG0 0621#define NBIO_BASE__INST5_SEG1 0622#define NBIO_BASE__INST5_SEG2 0623#define NBIO_BASE__INST5_SEG3 0624#define NBIO_BASE__INST5_SEG4 0625#define NBIO_BASE__INST5_SEG5 0626627#define OSSSYS_BASE__INST0_SEG0 0x000010A0628#define OSSSYS_BASE__INST0_SEG1 0629#define OSSSYS_BASE__INST0_SEG2 0630#define OSSSYS_BASE__INST0_SEG3 0631#define OSSSYS_BASE__INST0_SEG4 0632#define OSSSYS_BASE__INST0_SEG5 0633634#define OSSSYS_BASE__INST1_SEG0 0635#define OSSSYS_BASE__INST1_SEG1 0636#define OSSSYS_BASE__INST1_SEG2 0637#define OSSSYS_BASE__INST1_SEG3 0638#define OSSSYS_BASE__INST1_SEG4 0639#define OSSSYS_BASE__INST1_SEG5 0640641#define OSSSYS_BASE__INST2_SEG0 0642#define OSSSYS_BASE__INST2_SEG1 0643#define OSSSYS_BASE__INST2_SEG2 0644#define OSSSYS_BASE__INST2_SEG3 0645#define OSSSYS_BASE__INST2_SEG4 0646#define OSSSYS_BASE__INST2_SEG5 0647648#define OSSSYS_BASE__INST3_SEG0 0649#define OSSSYS_BASE__INST3_SEG1 0650#define OSSSYS_BASE__INST3_SEG2 0651#define OSSSYS_BASE__INST3_SEG3 0652#define OSSSYS_BASE__INST3_SEG4 0653#define OSSSYS_BASE__INST3_SEG5 0654655#define OSSSYS_BASE__INST4_SEG0 0656#define OSSSYS_BASE__INST4_SEG1 0657#define OSSSYS_BASE__INST4_SEG2 0658#define OSSSYS_BASE__INST4_SEG3 0659#define OSSSYS_BASE__INST4_SEG4 0660#define OSSSYS_BASE__INST4_SEG5 0661662#define OSSSYS_BASE__INST5_SEG0 0663#define OSSSYS_BASE__INST5_SEG1 0664#define OSSSYS_BASE__INST5_SEG2 0665#define OSSSYS_BASE__INST5_SEG3 0666#define OSSSYS_BASE__INST5_SEG4 0667#define OSSSYS_BASE__INST5_SEG5 0668669#define SDMA0_BASE__INST0_SEG0 0x00001260670#define SDMA0_BASE__INST0_SEG1 0671#define SDMA0_BASE__INST0_SEG2 0672#define SDMA0_BASE__INST0_SEG3 0673#define SDMA0_BASE__INST0_SEG4 0674#define SDMA0_BASE__INST0_SEG5 0675676#define SDMA0_BASE__INST1_SEG0 0677#define SDMA0_BASE__INST1_SEG1 0678#define SDMA0_BASE__INST1_SEG2 0679#define SDMA0_BASE__INST1_SEG3 0680#define SDMA0_BASE__INST1_SEG4 0681#define SDMA0_BASE__INST1_SEG5 0682683#define SDMA0_BASE__INST2_SEG0 0684#define SDMA0_BASE__INST2_SEG1 0685#define SDMA0_BASE__INST2_SEG2 0686#define SDMA0_BASE__INST2_SEG3 0687#define SDMA0_BASE__INST2_SEG4 0688#define SDMA0_BASE__INST2_SEG5 0689690#define SDMA0_BASE__INST3_SEG0 0691#define SDMA0_BASE__INST3_SEG1 0692#define SDMA0_BASE__INST3_SEG2 0693#define SDMA0_BASE__INST3_SEG3 0694#define SDMA0_BASE__INST3_SEG4 0695#define SDMA0_BASE__INST3_SEG5 0696697#define SDMA0_BASE__INST4_SEG0 0698#define SDMA0_BASE__INST4_SEG1 0699#define SDMA0_BASE__INST4_SEG2 0700#define SDMA0_BASE__INST4_SEG3 0701#define SDMA0_BASE__INST4_SEG4 0702#define SDMA0_BASE__INST4_SEG5 0703704#define SDMA0_BASE__INST5_SEG0 0705#define SDMA0_BASE__INST5_SEG1 0706#define SDMA0_BASE__INST5_SEG2 0707#define SDMA0_BASE__INST5_SEG3 0708#define SDMA0_BASE__INST5_SEG4 0709#define SDMA0_BASE__INST5_SEG5 0710711#define SDMA1_BASE__INST0_SEG0 0x00001860712#define SDMA1_BASE__INST0_SEG1 0713#define SDMA1_BASE__INST0_SEG2 0714#define SDMA1_BASE__INST0_SEG3 0715#define SDMA1_BASE__INST0_SEG4 0716#define SDMA1_BASE__INST0_SEG5 0717718#define SDMA1_BASE__INST1_SEG0 0719#define SDMA1_BASE__INST1_SEG1 0720#define SDMA1_BASE__INST1_SEG2 0721#define SDMA1_BASE__INST1_SEG3 0722#define SDMA1_BASE__INST1_SEG4 0723#define SDMA1_BASE__INST1_SEG5 0724725#define SDMA1_BASE__INST2_SEG0 0726#define SDMA1_BASE__INST2_SEG1 0727#define SDMA1_BASE__INST2_SEG2 0728#define SDMA1_BASE__INST2_SEG3 0729#define SDMA1_BASE__INST2_SEG4 0730#define SDMA1_BASE__INST2_SEG5 0731732#define SDMA1_BASE__INST3_SEG0 0733#define SDMA1_BASE__INST3_SEG1 0734#define SDMA1_BASE__INST3_SEG2 0735#define SDMA1_BASE__INST3_SEG3 0736#define SDMA1_BASE__INST3_SEG4 0737#define SDMA1_BASE__INST3_SEG5 0738739#define SDMA1_BASE__INST4_SEG0 0740#define SDMA1_BASE__INST4_SEG1 0741#define SDMA1_BASE__INST4_SEG2 0742#define SDMA1_BASE__INST4_SEG3 0743#define SDMA1_BASE__INST4_SEG4 0744#define SDMA1_BASE__INST4_SEG5 0745746#define SDMA1_BASE__INST5_SEG0 0747#define SDMA1_BASE__INST5_SEG1 0748#define SDMA1_BASE__INST5_SEG2 0749#define SDMA1_BASE__INST5_SEG3 0750#define SDMA1_BASE__INST5_SEG4 0751#define SDMA1_BASE__INST5_SEG5 0752753#define SMUIO_BASE__INST0_SEG0 0x00016800754#define SMUIO_BASE__INST0_SEG1 0x00016A00755#define SMUIO_BASE__INST0_SEG2 0756#define SMUIO_BASE__INST0_SEG3 0757#define SMUIO_BASE__INST0_SEG4 0758#define SMUIO_BASE__INST0_SEG5 0759760#define SMUIO_BASE__INST1_SEG0 0761#define SMUIO_BASE__INST1_SEG1 0762#define SMUIO_BASE__INST1_SEG2 0763#define SMUIO_BASE__INST1_SEG3 0764#define SMUIO_BASE__INST1_SEG4 0765#define SMUIO_BASE__INST1_SEG5 0766767#define SMUIO_BASE__INST2_SEG0 0768#define SMUIO_BASE__INST2_SEG1 0769#define SMUIO_BASE__INST2_SEG2 0770#define SMUIO_BASE__INST2_SEG3 0771#define SMUIO_BASE__INST2_SEG4 0772#define SMUIO_BASE__INST2_SEG5 0773774#define SMUIO_BASE__INST3_SEG0 0775#define SMUIO_BASE__INST3_SEG1 0776#define SMUIO_BASE__INST3_SEG2 0777#define SMUIO_BASE__INST3_SEG3 0778#define SMUIO_BASE__INST3_SEG4 0779#define SMUIO_BASE__INST3_SEG5 0780781#define SMUIO_BASE__INST4_SEG0 0782#define SMUIO_BASE__INST4_SEG1 0783#define SMUIO_BASE__INST4_SEG2 0784#define SMUIO_BASE__INST4_SEG3 0785#define SMUIO_BASE__INST4_SEG4 0786#define SMUIO_BASE__INST4_SEG5 0787788#define SMUIO_BASE__INST5_SEG0 0789#define SMUIO_BASE__INST5_SEG1 0790#define SMUIO_BASE__INST5_SEG2 0791#define SMUIO_BASE__INST5_SEG3 0792#define SMUIO_BASE__INST5_SEG4 0793#define SMUIO_BASE__INST5_SEG5 0794795#define THM_BASE__INST0_SEG0 0x00016600796#define THM_BASE__INST0_SEG1 0797#define THM_BASE__INST0_SEG2 0798#define THM_BASE__INST0_SEG3 0799#define THM_BASE__INST0_SEG4 0800#define THM_BASE__INST0_SEG5 0801802#define THM_BASE__INST1_SEG0 0803#define THM_BASE__INST1_SEG1 0804#define THM_BASE__INST1_SEG2 0805#define THM_BASE__INST1_SEG3 0806#define THM_BASE__INST1_SEG4 0807#define THM_BASE__INST1_SEG5 0808809#define THM_BASE__INST2_SEG0 0810#define THM_BASE__INST2_SEG1 0811#define THM_BASE__INST2_SEG2 0812#define THM_BASE__INST2_SEG3 0813#define THM_BASE__INST2_SEG4 0814#define THM_BASE__INST2_SEG5 0815816#define THM_BASE__INST3_SEG0 0817#define THM_BASE__INST3_SEG1 0818#define THM_BASE__INST3_SEG2 0819#define THM_BASE__INST3_SEG3 0820#define THM_BASE__INST3_SEG4 0821#define THM_BASE__INST3_SEG5 0822823#define THM_BASE__INST4_SEG0 0824#define THM_BASE__INST4_SEG1 0825#define THM_BASE__INST4_SEG2 0826#define THM_BASE__INST4_SEG3 0827#define THM_BASE__INST4_SEG4 0828#define THM_BASE__INST4_SEG5 0829830#define THM_BASE__INST5_SEG0 0831#define THM_BASE__INST5_SEG1 0832#define THM_BASE__INST5_SEG2 0833#define THM_BASE__INST5_SEG3 0834#define THM_BASE__INST5_SEG4 0835#define THM_BASE__INST5_SEG5 0836837#define UMC_BASE__INST0_SEG0 0x00014000838#define UMC_BASE__INST0_SEG1 0839#define UMC_BASE__INST0_SEG2 0840#define UMC_BASE__INST0_SEG3 0841#define UMC_BASE__INST0_SEG4 0842#define UMC_BASE__INST0_SEG5 0843844#define UMC_BASE__INST1_SEG0 0845#define UMC_BASE__INST1_SEG1 0846#define UMC_BASE__INST1_SEG2 0847#define UMC_BASE__INST1_SEG3 0848#define UMC_BASE__INST1_SEG4 0849#define UMC_BASE__INST1_SEG5 0850851#define UMC_BASE__INST2_SEG0 0852#define UMC_BASE__INST2_SEG1 0853#define UMC_BASE__INST2_SEG2 0854#define UMC_BASE__INST2_SEG3 0855#define UMC_BASE__INST2_SEG4 0856#define UMC_BASE__INST2_SEG5 0857858#define UMC_BASE__INST3_SEG0 0859#define UMC_BASE__INST3_SEG1 0860#define UMC_BASE__INST3_SEG2 0861#define UMC_BASE__INST3_SEG3 0862#define UMC_BASE__INST3_SEG4 0863#define UMC_BASE__INST3_SEG5 0864865#define UMC_BASE__INST4_SEG0 0866#define UMC_BASE__INST4_SEG1 0867#define UMC_BASE__INST4_SEG2 0868#define UMC_BASE__INST4_SEG3 0869#define UMC_BASE__INST4_SEG4 0870#define UMC_BASE__INST4_SEG5 0871872#define UMC_BASE__INST5_SEG0 0873#define UMC_BASE__INST5_SEG1 0874#define UMC_BASE__INST5_SEG2 0875#define UMC_BASE__INST5_SEG3 0876#define UMC_BASE__INST5_SEG4 0877#define UMC_BASE__INST5_SEG5 0878879#define UVD_BASE__INST0_SEG0 0x00007800880#define UVD_BASE__INST0_SEG1 0x00007E00881#define UVD_BASE__INST0_SEG2 0882#define UVD_BASE__INST0_SEG3 0883#define UVD_BASE__INST0_SEG4 0884#define UVD_BASE__INST0_SEG5 0885886#define UVD_BASE__INST1_SEG0 0887#define UVD_BASE__INST1_SEG1 0x00009000888#define UVD_BASE__INST1_SEG2 0889#define UVD_BASE__INST1_SEG3 0890#define UVD_BASE__INST1_SEG4 0891#define UVD_BASE__INST1_SEG5 0892893#define UVD_BASE__INST2_SEG0 0894#define UVD_BASE__INST2_SEG1 0895#define UVD_BASE__INST2_SEG2 0896#define UVD_BASE__INST2_SEG3 0897#define UVD_BASE__INST2_SEG4 0898#define UVD_BASE__INST2_SEG5 0899900#define UVD_BASE__INST3_SEG0 0901#define UVD_BASE__INST3_SEG1 0902#define UVD_BASE__INST3_SEG2 0903#define UVD_BASE__INST3_SEG3 0904#define UVD_BASE__INST3_SEG4 0905#define UVD_BASE__INST3_SEG5 0906907#define UVD_BASE__INST4_SEG0 0908#define UVD_BASE__INST4_SEG1 0909#define UVD_BASE__INST4_SEG2 0910#define UVD_BASE__INST4_SEG3 0911#define UVD_BASE__INST4_SEG4 0912#define UVD_BASE__INST4_SEG5 0913914#define UVD_BASE__INST5_SEG0 0915#define UVD_BASE__INST5_SEG1 0916#define UVD_BASE__INST5_SEG2 0917#define UVD_BASE__INST5_SEG3 0918#define UVD_BASE__INST5_SEG4 0919#define UVD_BASE__INST5_SEG5 0920921#define VCE_BASE__INST0_SEG0 0x00008800922#define VCE_BASE__INST0_SEG1 0923#define VCE_BASE__INST0_SEG2 0924#define VCE_BASE__INST0_SEG3 0925#define VCE_BASE__INST0_SEG4 0926#define VCE_BASE__INST0_SEG5 0927928#define VCE_BASE__INST1_SEG0 0929#define VCE_BASE__INST1_SEG1 0930#define VCE_BASE__INST1_SEG2 0931#define VCE_BASE__INST1_SEG3 0932#define VCE_BASE__INST1_SEG4 0933#define VCE_BASE__INST1_SEG5 0934935#define VCE_BASE__INST2_SEG0 0936#define VCE_BASE__INST2_SEG1 0937#define VCE_BASE__INST2_SEG2 0938#define VCE_BASE__INST2_SEG3 0939#define VCE_BASE__INST2_SEG4 0940#define VCE_BASE__INST2_SEG5 0941942#define VCE_BASE__INST3_SEG0 0943#define VCE_BASE__INST3_SEG1 0944#define VCE_BASE__INST3_SEG2 0945#define VCE_BASE__INST3_SEG3 0946#define VCE_BASE__INST3_SEG4 0947#define VCE_BASE__INST3_SEG5 0948949#define VCE_BASE__INST4_SEG0 0950#define VCE_BASE__INST4_SEG1 0951#define VCE_BASE__INST4_SEG2 0952#define VCE_BASE__INST4_SEG3 0953#define VCE_BASE__INST4_SEG4 0954#define VCE_BASE__INST4_SEG5 0955956#define VCE_BASE__INST5_SEG0 0957#define VCE_BASE__INST5_SEG1 0958#define VCE_BASE__INST5_SEG2 0959#define VCE_BASE__INST5_SEG3 0960#define VCE_BASE__INST5_SEG4 0961#define VCE_BASE__INST5_SEG5 0962963#define XDMA_BASE__INST0_SEG0 0x00003400964#define XDMA_BASE__INST0_SEG1 0965#define XDMA_BASE__INST0_SEG2 0966#define XDMA_BASE__INST0_SEG3 0967#define XDMA_BASE__INST0_SEG4 0968#define XDMA_BASE__INST0_SEG5 0969970#define XDMA_BASE__INST1_SEG0 0971#define XDMA_BASE__INST1_SEG1 0972#define XDMA_BASE__INST1_SEG2 0973#define XDMA_BASE__INST1_SEG3 0974#define XDMA_BASE__INST1_SEG4 0975#define XDMA_BASE__INST1_SEG5 0976977#define XDMA_BASE__INST2_SEG0 0978#define XDMA_BASE__INST2_SEG1 0979#define XDMA_BASE__INST2_SEG2 0980#define XDMA_BASE__INST2_SEG3 0981#define XDMA_BASE__INST2_SEG4 0982#define XDMA_BASE__INST2_SEG5 0983984#define XDMA_BASE__INST3_SEG0 0985#define XDMA_BASE__INST3_SEG1 0986#define XDMA_BASE__INST3_SEG2 0987#define XDMA_BASE__INST3_SEG3 0988#define XDMA_BASE__INST3_SEG4 0989#define XDMA_BASE__INST3_SEG5 0990991#define XDMA_BASE__INST4_SEG0 0992#define XDMA_BASE__INST4_SEG1 0993#define XDMA_BASE__INST4_SEG2 0994#define XDMA_BASE__INST4_SEG3 0995#define XDMA_BASE__INST4_SEG4 0996#define XDMA_BASE__INST4_SEG5 0997998#define XDMA_BASE__INST5_SEG0 0999#define XDMA_BASE__INST5_SEG1 01000#define XDMA_BASE__INST5_SEG2 01001#define XDMA_BASE__INST5_SEG3 01002#define XDMA_BASE__INST5_SEG4 01003#define XDMA_BASE__INST5_SEG5 010041005#define RSMU_BASE__INST0_SEG0 0x000120001006#define RSMU_BASE__INST0_SEG1 01007#define RSMU_BASE__INST0_SEG2 01008#define RSMU_BASE__INST0_SEG3 01009#define RSMU_BASE__INST0_SEG4 01010#define RSMU_BASE__INST0_SEG5 010111012#define RSMU_BASE__INST1_SEG0 01013#define RSMU_BASE__INST1_SEG1 01014#define RSMU_BASE__INST1_SEG2 01015#define RSMU_BASE__INST1_SEG3 01016#define RSMU_BASE__INST1_SEG4 01017#define RSMU_BASE__INST1_SEG5 010181019#define RSMU_BASE__INST2_SEG0 01020#define RSMU_BASE__INST2_SEG1 01021#define RSMU_BASE__INST2_SEG2 01022#define RSMU_BASE__INST2_SEG3 01023#define RSMU_BASE__INST2_SEG4 01024#define RSMU_BASE__INST2_SEG5 010251026#define RSMU_BASE__INST3_SEG0 01027#define RSMU_BASE__INST3_SEG1 01028#define RSMU_BASE__INST3_SEG2 01029#define RSMU_BASE__INST3_SEG3 01030#define RSMU_BASE__INST3_SEG4 01031#define RSMU_BASE__INST3_SEG5 010321033#define RSMU_BASE__INST4_SEG0 01034#define RSMU_BASE__INST4_SEG1 01035#define RSMU_BASE__INST4_SEG2 01036#define RSMU_BASE__INST4_SEG3 01037#define RSMU_BASE__INST4_SEG4 01038#define RSMU_BASE__INST4_SEG5 010391040#define RSMU_BASE__INST5_SEG0 01041#define RSMU_BASE__INST5_SEG1 01042#define RSMU_BASE__INST5_SEG2 01043#define RSMU_BASE__INST5_SEG3 01044#define RSMU_BASE__INST5_SEG4 01045#define RSMU_BASE__INST5_SEG5 010461047#endif1048104910501051