Path: blob/master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pppcielanes.c
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/*1* Copyright 2015 Advanced Micro Devices, Inc.2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice shall be included in11* all copies or substantial portions of the Software.12*13* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR14* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,15* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL16* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR17* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,18* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR19* OTHER DEALINGS IN THE SOFTWARE.20*21*/2223#include <linux/types.h>24#include "atom-types.h"25#include "atombios.h"26#include "pppcielanes.h"2728/** \file29* Functions related to PCIe lane changes.30*/3132/* For converting from number of lanes to lane bits. */33static const unsigned char pp_r600_encode_lanes[] = {340, /* 0 Not Supported */351, /* 1 Lane */362, /* 2 Lanes */370, /* 3 Not Supported */383, /* 4 Lanes */390, /* 5 Not Supported */400, /* 6 Not Supported */410, /* 7 Not Supported */424, /* 8 Lanes */430, /* 9 Not Supported */440, /* 10 Not Supported */450, /* 11 Not Supported */465, /* 12 Lanes (Not actually supported) */470, /* 13 Not Supported */480, /* 14 Not Supported */490, /* 15 Not Supported */506 /* 16 Lanes */51};5253static const unsigned char pp_r600_decoded_lanes[8] = { 16, 1, 2, 4, 8, 12, 16, };5455uint8_t encode_pcie_lane_width(uint32_t num_lanes)56{57return pp_r600_encode_lanes[num_lanes];58}5960uint8_t decode_pcie_lane_width(uint32_t num_lanes)61{62return pp_r600_decoded_lanes[num_lanes];63}646566