Path: blob/master/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
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/* SPDX-License-Identifier: GPL-2.0 */1/*2* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.3* Author: James.Qian.Wang <[email protected]>4*5*/6#ifndef _KOMEDA_PIPELINE_H_7#define _KOMEDA_PIPELINE_H_89#include <linux/types.h>10#include <drm/drm_atomic.h>11#include <drm/drm_atomic_helper.h>12#include "malidp_utils.h"13#include "komeda_color_mgmt.h"1415#define KOMEDA_MAX_PIPELINES 216#define KOMEDA_PIPELINE_MAX_LAYERS 417#define KOMEDA_PIPELINE_MAX_SCALERS 218#define KOMEDA_COMPONENT_N_INPUTS 51920/* pipeline component IDs */21enum {22KOMEDA_COMPONENT_LAYER0 = 0,23KOMEDA_COMPONENT_LAYER1 = 1,24KOMEDA_COMPONENT_LAYER2 = 2,25KOMEDA_COMPONENT_LAYER3 = 3,26KOMEDA_COMPONENT_WB_LAYER = 7, /* write back layer */27KOMEDA_COMPONENT_SCALER0 = 8,28KOMEDA_COMPONENT_SCALER1 = 9,29KOMEDA_COMPONENT_SPLITTER = 12,30KOMEDA_COMPONENT_MERGER = 14,31KOMEDA_COMPONENT_COMPIZ0 = 16, /* compositor */32KOMEDA_COMPONENT_COMPIZ1 = 17,33KOMEDA_COMPONENT_IPS0 = 20, /* post image processor */34KOMEDA_COMPONENT_IPS1 = 21,35KOMEDA_COMPONENT_TIMING_CTRLR = 22, /* timing controller */36};3738#define KOMEDA_PIPELINE_LAYERS (BIT(KOMEDA_COMPONENT_LAYER0) |\39BIT(KOMEDA_COMPONENT_LAYER1) |\40BIT(KOMEDA_COMPONENT_LAYER2) |\41BIT(KOMEDA_COMPONENT_LAYER3))4243#define KOMEDA_PIPELINE_SCALERS (BIT(KOMEDA_COMPONENT_SCALER0) |\44BIT(KOMEDA_COMPONENT_SCALER1))4546#define KOMEDA_PIPELINE_COMPIZS (BIT(KOMEDA_COMPONENT_COMPIZ0) |\47BIT(KOMEDA_COMPONENT_COMPIZ1))4849#define KOMEDA_PIPELINE_IMPROCS (BIT(KOMEDA_COMPONENT_IPS0) |\50BIT(KOMEDA_COMPONENT_IPS1))51struct komeda_component;52struct komeda_component_state;5354/** komeda_component_funcs - component control functions */55struct komeda_component_funcs {56/** @validate: optional,57* component may has special requirements or limitations, this function58* supply HW the ability to do the further HW specific check.59*/60int (*validate)(struct komeda_component *c,61struct komeda_component_state *state);62/** @update: update is a active update */63void (*update)(struct komeda_component *c,64struct komeda_component_state *state);65/** @disable: disable component */66void (*disable)(struct komeda_component *c);67/** @dump_register: Optional, dump registers to seq_file */68void (*dump_register)(struct komeda_component *c, struct seq_file *seq);69};7071/**72* struct komeda_component73*74* struct komeda_component describe the data flow capabilities for how to link a75* component into the display pipeline.76* all specified components are subclass of this structure.77*/78struct komeda_component {79/** @obj: treat component as private obj */80struct drm_private_obj obj;81/** @pipeline: the komeda pipeline this component belongs to */82struct komeda_pipeline *pipeline;83/** @name: component name */84char name[32];85/**86* @reg:87* component register base,88* which is initialized by chip and used by chip only89*/90u32 __iomem *reg;91/** @id: component id */92u32 id;93/**94* @hw_id: component hw id,95* which is initialized by chip and used by chip only96*/97u32 hw_id;9899/**100* @max_active_inputs:101* @max_active_outputs:102*103* maximum number of inputs/outputs that can be active at the same time104* Note:105* the number isn't the bit number of @supported_inputs or106* @supported_outputs, but may be less than it, since component may not107* support enabling all @supported_inputs/outputs at the same time.108*/109u8 max_active_inputs;110/** @max_active_outputs: maximum number of outputs */111u8 max_active_outputs;112/**113* @supported_inputs:114* @supported_outputs:115*116* bitmask of BIT(component->id) for the supported inputs/outputs,117* describes the possibilities of how a component is linked into a118* pipeline.119*/120u32 supported_inputs;121/** @supported_outputs: bitmask of supported output componenet ids */122u32 supported_outputs;123124/**125* @funcs: chip functions to access HW126*/127const struct komeda_component_funcs *funcs;128};129130/**131* struct komeda_component_output132*133* a component has multiple outputs, if want to know where the data134* comes from, only know the component is not enough, we still need to know135* its output port136*/137struct komeda_component_output {138/** @component: indicate which component the data comes from */139struct komeda_component *component;140/**141* @output_port:142* the output port of the &komeda_component_output.component143*/144u8 output_port;145};146147/**148* struct komeda_component_state149*150* component_state is the data flow configuration of the component, and it's151* the superclass of all specific component_state like @komeda_layer_state,152* @komeda_scaler_state153*/154struct komeda_component_state {155/** @obj: tracking component_state by drm_atomic_state */156struct drm_private_state obj;157/** @component: backpointer to the component */158struct komeda_component *component;159/**160* @binding_user:161* currently bound user, the user can be @crtc, @plane or @wb_conn,162* which is valid decided by @component and @inputs163*164* - Layer: its user always is plane.165* - compiz/improc/timing_ctrlr: the user is crtc.166* - wb_layer: wb_conn;167* - scaler: plane when input is layer, wb_conn if input is compiz.168*/169union {170/** @crtc: backpointer for user crtc */171struct drm_crtc *crtc;172/** @plane: backpointer for user plane */173struct drm_plane *plane;174/** @wb_conn: backpointer for user wb_connector */175struct drm_connector *wb_conn;176void *binding_user;177};178179/**180* @active_inputs:181*182* active_inputs is bitmask of @inputs index183*184* - active_inputs = changed_active_inputs | unchanged_active_inputs185* - affected_inputs = old->active_inputs | new->active_inputs;186* - disabling_inputs = affected_inputs ^ active_inputs;187* - changed_inputs = disabling_inputs | changed_active_inputs;188*189* NOTE:190* changed_inputs doesn't include all active_input but only191* @changed_active_inputs, and this bitmask can be used in chip192* level for dirty update.193*/194u16 active_inputs;195/** @changed_active_inputs: bitmask of the changed @active_inputs */196u16 changed_active_inputs;197/** @affected_inputs: bitmask for affected @inputs */198u16 affected_inputs;199/**200* @inputs:201*202* the specific inputs[i] only valid on BIT(i) has been set in203* @active_inputs, if not the inputs[i] is undefined.204*/205struct komeda_component_output inputs[KOMEDA_COMPONENT_N_INPUTS];206};207208static inline u16 component_disabling_inputs(struct komeda_component_state *st)209{210return st->affected_inputs ^ st->active_inputs;211}212213static inline u16 component_changed_inputs(struct komeda_component_state *st)214{215return component_disabling_inputs(st) | st->changed_active_inputs;216}217218#define for_each_changed_input(st, i) \219for ((i) = 0; (i) < (st)->component->max_active_inputs; (i)++) \220if (has_bit((i), component_changed_inputs(st)))221222#define to_comp(__c) (((__c) == NULL) ? NULL : &((__c)->base))223#define to_cpos(__c) ((struct komeda_component **)&(__c))224225struct komeda_layer {226struct komeda_component base;227/* accepted h/v input range before rotation */228struct malidp_range hsize_in, vsize_in;229u32 layer_type; /* RICH, SIMPLE or WB */230u32 line_sz;231u32 yuv_line_sz; /* maximum line size for YUV422 and YUV420 */232u32 supported_rots;233/* komeda supports layer split which splits a whole image to two parts234* left and right and handle them by two individual layer processors235* Note: left/right are always according to the final display rect,236* not the source buffer.237*/238struct komeda_layer *right;239};240241struct komeda_layer_state {242struct komeda_component_state base;243/* layer specific configuration state */244u16 hsize, vsize;245u32 rot;246u16 afbc_crop_l;247u16 afbc_crop_r;248u16 afbc_crop_t;249u16 afbc_crop_b;250dma_addr_t addr[3];251};252253struct komeda_scaler {254struct komeda_component base;255struct malidp_range hsize, vsize;256u32 max_upscaling;257u32 max_downscaling;258u8 scaling_split_overlap; /* split overlap for scaling */259u8 enh_split_overlap; /* split overlap for image enhancement */260};261262struct komeda_scaler_state {263struct komeda_component_state base;264u16 hsize_in, vsize_in;265u16 hsize_out, vsize_out;266u16 total_hsize_in, total_vsize_in;267u16 total_hsize_out; /* total_xxxx are size before split */268u16 left_crop, right_crop;269u8 en_scaling : 1,270en_alpha : 1, /* enable alpha processing */271en_img_enhancement : 1,272en_split : 1,273right_part : 1; /* right part of split image */274};275276struct komeda_compiz {277struct komeda_component base;278struct malidp_range hsize, vsize;279};280281struct komeda_compiz_input_cfg {282u16 hsize, vsize;283u16 hoffset, voffset;284u8 pixel_blend_mode, layer_alpha;285};286287struct komeda_compiz_state {288struct komeda_component_state base;289/* composition size */290u16 hsize, vsize;291struct komeda_compiz_input_cfg cins[KOMEDA_COMPONENT_N_INPUTS];292};293294struct komeda_merger {295struct komeda_component base;296struct malidp_range hsize_merged;297struct malidp_range vsize_merged;298};299300struct komeda_merger_state {301struct komeda_component_state base;302u16 hsize_merged;303u16 vsize_merged;304};305306struct komeda_splitter {307struct komeda_component base;308struct malidp_range hsize, vsize;309};310311struct komeda_splitter_state {312struct komeda_component_state base;313u16 hsize, vsize;314u16 overlap;315};316317struct komeda_improc {318struct komeda_component base;319u32 supported_color_formats; /* DRM_RGB/YUV444/YUV420*/320u32 supported_color_depths; /* BIT(8) | BIT(10)*/321u8 supports_degamma : 1;322u8 supports_csc : 1;323u8 supports_gamma : 1;324};325326struct komeda_improc_state {327struct komeda_component_state base;328u8 color_format, color_depth;329u16 hsize, vsize;330u32 fgamma_coeffs[KOMEDA_N_GAMMA_COEFFS];331u32 ctm_coeffs[KOMEDA_N_CTM_COEFFS];332};333334/* display timing controller */335struct komeda_timing_ctrlr {336struct komeda_component base;337u8 supports_dual_link : 1;338};339340struct komeda_timing_ctrlr_state {341struct komeda_component_state base;342};343344/* Why define A separated structure but not use plane_state directly ?345* 1. Komeda supports layer_split which means a plane_state can be split and346* handled by two layers, one layer only handle half of plane image.347* 2. Fix up the user properties according to HW's capabilities, like user348* set rotation to R180, but HW only supports REFLECT_X+Y. the rot here is349* after drm_rotation_simplify()350*/351struct komeda_data_flow_cfg {352struct komeda_component_output input;353u16 in_x, in_y, in_w, in_h;354u32 out_x, out_y, out_w, out_h;355u16 total_in_h, total_in_w;356u16 total_out_w;357u16 left_crop, right_crop, overlap;358u32 rot;359int blending_zorder;360u8 pixel_blend_mode, layer_alpha;361u8 en_scaling : 1,362en_img_enhancement : 1,363en_split : 1,364is_yuv : 1,365right_part : 1; /* right part of display image if split enabled */366};367368struct komeda_pipeline_funcs {369/* check if the aclk (main engine clock) can satisfy the clock370* requirements of the downscaling that specified by dflow371*/372int (*downscaling_clk_check)(struct komeda_pipeline *pipe,373struct drm_display_mode *mode,374unsigned long aclk_rate,375struct komeda_data_flow_cfg *dflow);376/* dump_register: Optional, dump registers to seq_file */377void (*dump_register)(struct komeda_pipeline *pipe,378struct seq_file *sf);379};380381/**382* struct komeda_pipeline383*384* Represent a complete display pipeline and hold all functional components.385*/386struct komeda_pipeline {387/** @obj: link pipeline as private obj of drm_atomic_state */388struct drm_private_obj obj;389/** @mdev: the parent komeda_dev */390struct komeda_dev *mdev;391/** @pxlclk: pixel clock */392struct clk *pxlclk;393/** @id: pipeline id */394int id;395/** @avail_comps: available components mask of pipeline */396u32 avail_comps;397/**398* @standalone_disabled_comps:399*400* When disable the pipeline, some components can not be disabled401* together with others, but need a sparated and standalone disable.402* The standalone_disabled_comps are the components which need to be403* disabled standalone, and this concept also introduce concept of404* two phase.405* phase 1: for disabling the common components.406* phase 2: for disabling the standalong_disabled_comps.407*/408u32 standalone_disabled_comps;409/** @n_layers: the number of layer on @layers */410int n_layers;411/** @layers: the pipeline layers */412struct komeda_layer *layers[KOMEDA_PIPELINE_MAX_LAYERS];413/** @n_scalers: the number of scaler on @scalers */414int n_scalers;415/** @scalers: the pipeline scalers */416struct komeda_scaler *scalers[KOMEDA_PIPELINE_MAX_SCALERS];417/** @compiz: compositor */418struct komeda_compiz *compiz;419/** @splitter: for split the compiz output to two half data flows */420struct komeda_splitter *splitter;421/** @merger: merger */422struct komeda_merger *merger;423/** @wb_layer: writeback layer */424struct komeda_layer *wb_layer;425/** @improc: post image processor */426struct komeda_improc *improc;427/** @ctrlr: timing controller */428struct komeda_timing_ctrlr *ctrlr;429/** @funcs: chip private pipeline functions */430const struct komeda_pipeline_funcs *funcs;431432/** @of_node: pipeline dt node */433struct device_node *of_node;434/** @of_output_port: pipeline output port */435struct device_node *of_output_port;436/** @of_output_links: output connector device nodes */437struct device_node *of_output_links[2];438/** @dual_link: true if of_output_links[0] and [1] are both valid */439bool dual_link;440};441442/**443* struct komeda_pipeline_state444*445* NOTE:446* Unlike the pipeline, pipeline_state doesn’t gather any component_state447* into it. It because all component will be managed by drm_atomic_state.448*/449struct komeda_pipeline_state {450/** @obj: tracking pipeline_state by drm_atomic_state */451struct drm_private_state obj;452/** @pipe: backpointer to the pipeline */453struct komeda_pipeline *pipe;454/** @crtc: currently bound crtc */455struct drm_crtc *crtc;456/**457* @active_comps:458*459* bitmask - BIT(component->id) of active components460*/461u32 active_comps;462};463464#define to_layer(c) container_of(c, struct komeda_layer, base)465#define to_compiz(c) container_of(c, struct komeda_compiz, base)466#define to_scaler(c) container_of(c, struct komeda_scaler, base)467#define to_splitter(c) container_of(c, struct komeda_splitter, base)468#define to_merger(c) container_of(c, struct komeda_merger, base)469#define to_improc(c) container_of(c, struct komeda_improc, base)470#define to_ctrlr(c) container_of(c, struct komeda_timing_ctrlr, base)471472#define to_layer_st(c) container_of(c, struct komeda_layer_state, base)473#define to_compiz_st(c) container_of(c, struct komeda_compiz_state, base)474#define to_scaler_st(c) container_of(c, struct komeda_scaler_state, base)475#define to_splitter_st(c) container_of(c, struct komeda_splitter_state, base)476#define to_merger_st(c) container_of(c, struct komeda_merger_state, base)477#define to_improc_st(c) container_of(c, struct komeda_improc_state, base)478#define to_ctrlr_st(c) container_of(c, struct komeda_timing_ctrlr_state, base)479480#define priv_to_comp_st(o) container_of(o, struct komeda_component_state, obj)481#define priv_to_pipe_st(o) container_of(o, struct komeda_pipeline_state, obj)482483/* pipeline APIs */484struct komeda_pipeline *485komeda_pipeline_add(struct komeda_dev *mdev, size_t size,486const struct komeda_pipeline_funcs *funcs);487void komeda_pipeline_destroy(struct komeda_dev *mdev,488struct komeda_pipeline *pipe);489struct komeda_pipeline *490komeda_pipeline_get_slave(struct komeda_pipeline *master);491int komeda_assemble_pipelines(struct komeda_dev *mdev);492struct komeda_component *493komeda_pipeline_get_component(struct komeda_pipeline *pipe, int id);494struct komeda_component *495komeda_pipeline_get_first_component(struct komeda_pipeline *pipe,496u32 comp_mask);497498void komeda_pipeline_dump_register(struct komeda_pipeline *pipe,499struct seq_file *sf);500501/* component APIs */502extern __printf(10, 11)503struct komeda_component *504komeda_component_add(struct komeda_pipeline *pipe,505size_t comp_sz, u32 id, u32 hw_id,506const struct komeda_component_funcs *funcs,507u8 max_active_inputs, u32 supported_inputs,508u8 max_active_outputs, u32 __iomem *reg,509const char *name_fmt, ...);510511void komeda_component_destroy(struct komeda_dev *mdev,512struct komeda_component *c);513514static inline struct komeda_component *515komeda_component_pickup_output(struct komeda_component *c, u32 avail_comps)516{517u32 avail_inputs = c->supported_outputs & (avail_comps);518519return komeda_pipeline_get_first_component(c->pipeline, avail_inputs);520}521522struct komeda_plane_state;523struct komeda_crtc_state;524struct komeda_crtc;525526void pipeline_composition_size(struct komeda_crtc_state *kcrtc_st,527u16 *hsize, u16 *vsize);528529int komeda_build_layer_data_flow(struct komeda_layer *layer,530struct komeda_plane_state *kplane_st,531struct komeda_crtc_state *kcrtc_st,532struct komeda_data_flow_cfg *dflow);533int komeda_build_wb_data_flow(struct komeda_layer *wb_layer,534struct drm_connector_state *conn_st,535struct komeda_crtc_state *kcrtc_st,536struct komeda_data_flow_cfg *dflow);537int komeda_build_display_data_flow(struct komeda_crtc *kcrtc,538struct komeda_crtc_state *kcrtc_st);539540int komeda_build_layer_split_data_flow(struct komeda_layer *left,541struct komeda_plane_state *kplane_st,542struct komeda_crtc_state *kcrtc_st,543struct komeda_data_flow_cfg *dflow);544int komeda_build_wb_split_data_flow(struct komeda_layer *wb_layer,545struct drm_connector_state *conn_st,546struct komeda_crtc_state *kcrtc_st,547struct komeda_data_flow_cfg *dflow);548549int komeda_release_unclaimed_resources(struct komeda_pipeline *pipe,550struct komeda_crtc_state *kcrtc_st);551552struct komeda_pipeline_state *553komeda_pipeline_get_old_state(struct komeda_pipeline *pipe,554struct drm_atomic_state *state);555bool komeda_pipeline_disable(struct komeda_pipeline *pipe,556struct drm_atomic_state *old_state);557void komeda_pipeline_update(struct komeda_pipeline *pipe,558struct drm_atomic_state *old_state);559560void komeda_complete_data_flow_cfg(struct komeda_layer *layer,561struct komeda_data_flow_cfg *dflow,562struct drm_framebuffer *fb);563564#endif /* _KOMEDA_PIPELINE_H_*/565566567