Path: blob/master/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
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/* SPDX-License-Identifier: GPL-2.0-only */1/*2* Copyright(c) 2016, Analogix Semiconductor.3* Copyright(c) 2017, Icenowy Zheng <[email protected]>4*5* Based on anx7808 driver obtained from chromeos with copyright:6* Copyright(c) 2013, Google Inc.7*/8#include <linux/delay.h>9#include <linux/err.h>10#include <linux/gpio/consumer.h>11#include <linux/i2c.h>12#include <linux/interrupt.h>13#include <linux/kernel.h>14#include <linux/module.h>15#include <linux/of_platform.h>16#include <linux/regmap.h>17#include <linux/regulator/consumer.h>18#include <linux/types.h>1920#include <drm/display/drm_dp_helper.h>21#include <drm/drm_atomic_helper.h>22#include <drm/drm_bridge.h>23#include <drm/drm_crtc.h>24#include <drm/drm_edid.h>25#include <drm/drm_of.h>26#include <drm/drm_panel.h>27#include <drm/drm_print.h>28#include <drm/drm_probe_helper.h>2930#include "analogix-i2c-dptx.h"31#include "analogix-i2c-txcommon.h"3233#define POLL_DELAY 50000 /* us */34#define POLL_TIMEOUT 5000000 /* us */3536#define I2C_IDX_DPTX 037#define I2C_IDX_TXCOM 13839static const u8 anx6345_i2c_addresses[] = {40[I2C_IDX_DPTX] = 0x70,41[I2C_IDX_TXCOM] = 0x72,42};43#define I2C_NUM_ADDRESSES ARRAY_SIZE(anx6345_i2c_addresses)4445struct anx6345 {46struct drm_dp_aux aux;47struct drm_bridge bridge;48struct i2c_client *client;49const struct drm_edid *drm_edid;50struct drm_connector connector;51struct drm_panel *panel;52struct regulator *dvdd12;53struct regulator *dvdd25;54struct gpio_desc *gpiod_reset;55struct mutex lock; /* protect EDID access */5657/* I2C Slave addresses of ANX6345 are mapped as DPTX and SYS */58struct i2c_client *i2c_clients[I2C_NUM_ADDRESSES];59struct regmap *map[I2C_NUM_ADDRESSES];6061u16 chipid;62u8 dpcd[DP_RECEIVER_CAP_SIZE];6364bool powered;65};6667static inline struct anx6345 *connector_to_anx6345(struct drm_connector *c)68{69return container_of(c, struct anx6345, connector);70}7172static inline struct anx6345 *bridge_to_anx6345(struct drm_bridge *bridge)73{74return container_of(bridge, struct anx6345, bridge);75}7677static int anx6345_set_bits(struct regmap *map, u8 reg, u8 mask)78{79return regmap_update_bits(map, reg, mask, mask);80}8182static int anx6345_clear_bits(struct regmap *map, u8 reg, u8 mask)83{84return regmap_update_bits(map, reg, mask, 0);85}8687static ssize_t anx6345_aux_transfer(struct drm_dp_aux *aux,88struct drm_dp_aux_msg *msg)89{90struct anx6345 *anx6345 = container_of(aux, struct anx6345, aux);9192return anx_dp_aux_transfer(anx6345->map[I2C_IDX_DPTX], msg);93}9495static int anx6345_dp_link_training(struct anx6345 *anx6345)96{97unsigned int value;98u8 dp_bw, dpcd[2];99int err;100101err = anx6345_clear_bits(anx6345->map[I2C_IDX_TXCOM],102SP_POWERDOWN_CTRL_REG,103SP_TOTAL_PD);104if (err)105return err;106107err = drm_dp_dpcd_readb(&anx6345->aux, DP_MAX_LINK_RATE, &dp_bw);108if (err < 0)109return err;110111switch (dp_bw) {112case DP_LINK_BW_1_62:113case DP_LINK_BW_2_7:114break;115116default:117DRM_DEBUG_KMS("DP bandwidth (%#02x) not supported\n", dp_bw);118return -EINVAL;119}120121err = anx6345_set_bits(anx6345->map[I2C_IDX_TXCOM], SP_VID_CTRL1_REG,122SP_VIDEO_MUTE);123if (err)124return err;125126err = anx6345_clear_bits(anx6345->map[I2C_IDX_TXCOM],127SP_VID_CTRL1_REG, SP_VIDEO_EN);128if (err)129return err;130131/* Get DPCD info */132err = drm_dp_dpcd_read(&anx6345->aux, DP_DPCD_REV,133&anx6345->dpcd, DP_RECEIVER_CAP_SIZE);134if (err < 0) {135DRM_ERROR("Failed to read DPCD: %d\n", err);136return err;137}138139/* Clear channel x SERDES power down */140err = anx6345_clear_bits(anx6345->map[I2C_IDX_DPTX],141SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);142if (err)143return err;144145drm_dp_link_power_up(&anx6345->aux, anx6345->dpcd[DP_DPCD_REV]);146147/* Possibly enable downspread on the sink */148err = regmap_write(anx6345->map[I2C_IDX_DPTX],149SP_DP_DOWNSPREAD_CTRL1_REG, 0);150if (err)151return err;152153if (anx6345->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) {154DRM_DEBUG("Enable downspread on the sink\n");155/* 4000PPM */156err = regmap_write(anx6345->map[I2C_IDX_DPTX],157SP_DP_DOWNSPREAD_CTRL1_REG, 8);158if (err)159return err;160161err = drm_dp_dpcd_writeb(&anx6345->aux, DP_DOWNSPREAD_CTRL,162DP_SPREAD_AMP_0_5);163if (err < 0)164return err;165} else {166err = drm_dp_dpcd_writeb(&anx6345->aux, DP_DOWNSPREAD_CTRL, 0);167if (err < 0)168return err;169}170171/* Set the lane count and the link rate on the sink */172if (drm_dp_enhanced_frame_cap(anx6345->dpcd))173err = anx6345_set_bits(anx6345->map[I2C_IDX_DPTX],174SP_DP_SYSTEM_CTRL_BASE + 4,175SP_ENHANCED_MODE);176else177err = anx6345_clear_bits(anx6345->map[I2C_IDX_DPTX],178SP_DP_SYSTEM_CTRL_BASE + 4,179SP_ENHANCED_MODE);180if (err)181return err;182183dpcd[0] = dp_bw;184err = regmap_write(anx6345->map[I2C_IDX_DPTX],185SP_DP_MAIN_LINK_BW_SET_REG, dpcd[0]);186if (err)187return err;188189dpcd[1] = drm_dp_max_lane_count(anx6345->dpcd);190191err = regmap_write(anx6345->map[I2C_IDX_DPTX],192SP_DP_LANE_COUNT_SET_REG, dpcd[1]);193if (err)194return err;195196if (drm_dp_enhanced_frame_cap(anx6345->dpcd))197dpcd[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;198199err = drm_dp_dpcd_write(&anx6345->aux, DP_LINK_BW_SET, dpcd,200sizeof(dpcd));201202if (err < 0) {203DRM_ERROR("Failed to configure link: %d\n", err);204return err;205}206207/* Start training on the source */208err = regmap_write(anx6345->map[I2C_IDX_DPTX], SP_DP_LT_CTRL_REG,209SP_LT_EN);210if (err)211return err;212213return regmap_read_poll_timeout(anx6345->map[I2C_IDX_DPTX],214SP_DP_LT_CTRL_REG,215value, !(value & SP_DP_LT_INPROGRESS),216POLL_DELAY, POLL_TIMEOUT);217}218219static int anx6345_tx_initialization(struct anx6345 *anx6345)220{221int err, i;222223/* FIXME: colordepth is hardcoded for now */224err = regmap_write(anx6345->map[I2C_IDX_TXCOM], SP_VID_CTRL2_REG,225SP_IN_BPC_6BIT << SP_IN_BPC_SHIFT);226if (err)227return err;228229err = regmap_write(anx6345->map[I2C_IDX_DPTX], SP_DP_PLL_CTRL_REG, 0);230if (err)231return err;232233err = regmap_write(anx6345->map[I2C_IDX_TXCOM],234SP_ANALOG_DEBUG1_REG, 0);235if (err)236return err;237238err = regmap_write(anx6345->map[I2C_IDX_DPTX],239SP_DP_LINK_DEBUG_CTRL_REG,240SP_NEW_PRBS7 | SP_M_VID_DEBUG);241if (err)242return err;243244err = regmap_write(anx6345->map[I2C_IDX_DPTX],245SP_DP_ANALOG_POWER_DOWN_REG, 0);246if (err)247return err;248249/* Force HPD */250err = anx6345_set_bits(anx6345->map[I2C_IDX_DPTX],251SP_DP_SYSTEM_CTRL_BASE + 3,252SP_HPD_FORCE | SP_HPD_CTRL);253if (err)254return err;255256for (i = 0; i < 4; i++) {257/* 4 lanes */258err = regmap_write(anx6345->map[I2C_IDX_DPTX],259SP_DP_LANE0_LT_CTRL_REG + i, 0);260if (err)261return err;262}263264/* Reset AUX */265err = anx6345_set_bits(anx6345->map[I2C_IDX_TXCOM],266SP_RESET_CTRL2_REG, SP_AUX_RST);267if (err)268return err;269270return anx6345_clear_bits(anx6345->map[I2C_IDX_TXCOM],271SP_RESET_CTRL2_REG, SP_AUX_RST);272}273274static void anx6345_poweron(struct anx6345 *anx6345)275{276int err;277278/* Ensure reset is asserted before starting power on sequence */279gpiod_set_value_cansleep(anx6345->gpiod_reset, 1);280usleep_range(1000, 2000);281282err = regulator_enable(anx6345->dvdd12);283if (err) {284DRM_ERROR("Failed to enable dvdd12 regulator: %d\n",285err);286return;287}288289/* T1 - delay between VDD12 and VDD25 should be 0-2ms */290usleep_range(1000, 2000);291292err = regulator_enable(anx6345->dvdd25);293if (err) {294DRM_ERROR("Failed to enable dvdd25 regulator: %d\n",295err);296return;297}298299/* T2 - delay between RESETN and all power rail stable,300* should be 2-5ms301*/302usleep_range(2000, 5000);303304gpiod_set_value_cansleep(anx6345->gpiod_reset, 0);305306/* Power on registers module */307anx6345_set_bits(anx6345->map[I2C_IDX_TXCOM], SP_POWERDOWN_CTRL_REG,308SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);309anx6345_clear_bits(anx6345->map[I2C_IDX_TXCOM], SP_POWERDOWN_CTRL_REG,310SP_REGISTER_PD | SP_TOTAL_PD);311312if (anx6345->panel)313drm_panel_prepare(anx6345->panel);314315anx6345->powered = true;316}317318static void anx6345_poweroff(struct anx6345 *anx6345)319{320int err;321322gpiod_set_value_cansleep(anx6345->gpiod_reset, 1);323usleep_range(1000, 2000);324325if (anx6345->panel)326drm_panel_unprepare(anx6345->panel);327328err = regulator_disable(anx6345->dvdd25);329if (err) {330DRM_ERROR("Failed to disable dvdd25 regulator: %d\n",331err);332return;333}334335usleep_range(5000, 10000);336337err = regulator_disable(anx6345->dvdd12);338if (err) {339DRM_ERROR("Failed to disable dvdd12 regulator: %d\n",340err);341return;342}343344usleep_range(1000, 2000);345346anx6345->powered = false;347}348349static int anx6345_start(struct anx6345 *anx6345)350{351int err;352353if (!anx6345->powered)354anx6345_poweron(anx6345);355356/* Power on needed modules */357err = anx6345_clear_bits(anx6345->map[I2C_IDX_TXCOM],358SP_POWERDOWN_CTRL_REG,359SP_VIDEO_PD | SP_LINK_PD);360361err = anx6345_tx_initialization(anx6345);362if (err) {363DRM_ERROR("Failed eDP transmitter initialization: %d\n", err);364anx6345_poweroff(anx6345);365return err;366}367368err = anx6345_dp_link_training(anx6345);369if (err) {370DRM_ERROR("Failed link training: %d\n", err);371anx6345_poweroff(anx6345);372return err;373}374375/*376* This delay seems to help keep the hardware in a good state. Without377* it, there are times where it fails silently.378*/379usleep_range(10000, 15000);380381return 0;382}383384static int anx6345_config_dp_output(struct anx6345 *anx6345)385{386int err;387388err = anx6345_clear_bits(anx6345->map[I2C_IDX_TXCOM], SP_VID_CTRL1_REG,389SP_VIDEO_MUTE);390if (err)391return err;392393/* Enable DP output */394err = anx6345_set_bits(anx6345->map[I2C_IDX_TXCOM], SP_VID_CTRL1_REG,395SP_VIDEO_EN);396if (err)397return err;398399/* Force stream valid */400return anx6345_set_bits(anx6345->map[I2C_IDX_DPTX],401SP_DP_SYSTEM_CTRL_BASE + 3,402SP_STRM_FORCE | SP_STRM_CTRL);403}404405static int anx6345_get_downstream_info(struct anx6345 *anx6345)406{407u8 value;408int err;409410err = drm_dp_dpcd_readb(&anx6345->aux, DP_SINK_COUNT, &value);411if (err < 0) {412DRM_ERROR("Get sink count failed %d\n", err);413return err;414}415416if (!DP_GET_SINK_COUNT(value)) {417DRM_ERROR("Downstream disconnected\n");418return -EIO;419}420421return 0;422}423424static int anx6345_get_modes(struct drm_connector *connector)425{426struct anx6345 *anx6345 = connector_to_anx6345(connector);427int err, num_modes = 0;428bool power_off = false;429430mutex_lock(&anx6345->lock);431432if (!anx6345->drm_edid) {433if (!anx6345->powered) {434anx6345_poweron(anx6345);435power_off = true;436}437438err = anx6345_get_downstream_info(anx6345);439if (err) {440DRM_ERROR("Failed to get downstream info: %d\n", err);441goto unlock;442}443444anx6345->drm_edid = drm_edid_read_ddc(connector, &anx6345->aux.ddc);445if (!anx6345->drm_edid)446DRM_ERROR("Failed to read EDID from panel\n");447448err = drm_edid_connector_update(connector, anx6345->drm_edid);449if (err) {450DRM_ERROR("Failed to update EDID property: %d\n", err);451goto unlock;452}453}454455num_modes += drm_edid_connector_add_modes(connector);456457/* Driver currently supports only 6bpc */458connector->display_info.bpc = 6;459460unlock:461if (power_off)462anx6345_poweroff(anx6345);463464mutex_unlock(&anx6345->lock);465466if (!num_modes && anx6345->panel)467num_modes += drm_panel_get_modes(anx6345->panel, connector);468469return num_modes;470}471472static const struct drm_connector_helper_funcs anx6345_connector_helper_funcs = {473.get_modes = anx6345_get_modes,474};475476static void477anx6345_connector_destroy(struct drm_connector *connector)478{479drm_connector_cleanup(connector);480}481482static const struct drm_connector_funcs anx6345_connector_funcs = {483.fill_modes = drm_helper_probe_single_connector_modes,484.destroy = anx6345_connector_destroy,485.reset = drm_atomic_helper_connector_reset,486.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,487.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,488};489490static int anx6345_bridge_attach(struct drm_bridge *bridge,491struct drm_encoder *encoder,492enum drm_bridge_attach_flags flags)493{494struct anx6345 *anx6345 = bridge_to_anx6345(bridge);495int err;496497if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {498DRM_ERROR("Fix bridge driver to make connector optional!");499return -EINVAL;500}501502/* Register aux channel */503anx6345->aux.name = "DP-AUX";504anx6345->aux.dev = &anx6345->client->dev;505anx6345->aux.drm_dev = bridge->dev;506anx6345->aux.transfer = anx6345_aux_transfer;507508err = drm_dp_aux_register(&anx6345->aux);509if (err < 0) {510DRM_ERROR("Failed to register aux channel: %d\n", err);511return err;512}513514err = drm_connector_init(bridge->dev, &anx6345->connector,515&anx6345_connector_funcs,516DRM_MODE_CONNECTOR_eDP);517if (err) {518DRM_ERROR("Failed to initialize connector: %d\n", err);519goto aux_unregister;520}521522drm_connector_helper_add(&anx6345->connector,523&anx6345_connector_helper_funcs);524525anx6345->connector.polled = DRM_CONNECTOR_POLL_HPD;526527err = drm_connector_attach_encoder(&anx6345->connector,528encoder);529if (err) {530DRM_ERROR("Failed to link up connector to encoder: %d\n", err);531goto connector_cleanup;532}533534err = drm_connector_register(&anx6345->connector);535if (err) {536DRM_ERROR("Failed to register connector: %d\n", err);537goto connector_cleanup;538}539540return 0;541connector_cleanup:542drm_connector_cleanup(&anx6345->connector);543aux_unregister:544drm_dp_aux_unregister(&anx6345->aux);545return err;546}547548static void anx6345_bridge_detach(struct drm_bridge *bridge)549{550drm_dp_aux_unregister(&bridge_to_anx6345(bridge)->aux);551}552553static enum drm_mode_status554anx6345_bridge_mode_valid(struct drm_bridge *bridge,555const struct drm_display_info *info,556const struct drm_display_mode *mode)557{558if (mode->flags & DRM_MODE_FLAG_INTERLACE)559return MODE_NO_INTERLACE;560561/* Max 1200p at 5.4 Ghz, one lane */562if (mode->clock > 154000)563return MODE_CLOCK_HIGH;564565return MODE_OK;566}567568static void anx6345_bridge_disable(struct drm_bridge *bridge)569{570struct anx6345 *anx6345 = bridge_to_anx6345(bridge);571572/* Power off all modules except configuration registers access */573anx6345_set_bits(anx6345->map[I2C_IDX_TXCOM], SP_POWERDOWN_CTRL_REG,574SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);575if (anx6345->panel)576drm_panel_disable(anx6345->panel);577578if (anx6345->powered)579anx6345_poweroff(anx6345);580}581582static void anx6345_bridge_enable(struct drm_bridge *bridge)583{584struct anx6345 *anx6345 = bridge_to_anx6345(bridge);585int err;586587if (anx6345->panel)588drm_panel_enable(anx6345->panel);589590err = anx6345_start(anx6345);591if (err) {592DRM_ERROR("Failed to initialize: %d\n", err);593return;594}595596err = anx6345_config_dp_output(anx6345);597if (err)598DRM_ERROR("Failed to enable DP output: %d\n", err);599}600601static const struct drm_bridge_funcs anx6345_bridge_funcs = {602.attach = anx6345_bridge_attach,603.detach = anx6345_bridge_detach,604.mode_valid = anx6345_bridge_mode_valid,605.disable = anx6345_bridge_disable,606.enable = anx6345_bridge_enable,607};608609static void unregister_i2c_dummy_clients(struct anx6345 *anx6345)610{611unsigned int i;612613for (i = 1; i < ARRAY_SIZE(anx6345->i2c_clients); i++)614if (anx6345->i2c_clients[i] &&615anx6345->i2c_clients[i]->addr != anx6345->client->addr)616i2c_unregister_device(anx6345->i2c_clients[i]);617}618619static const struct regmap_config anx6345_regmap_config = {620.reg_bits = 8,621.val_bits = 8,622.max_register = 0xff,623.cache_type = REGCACHE_NONE,624};625626static const u16 anx6345_chipid_list[] = {6270x6345,628};629630static bool anx6345_get_chip_id(struct anx6345 *anx6345)631{632unsigned int i, idl, idh, version;633634if (regmap_read(anx6345->map[I2C_IDX_TXCOM], SP_DEVICE_IDL_REG, &idl))635return false;636637if (regmap_read(anx6345->map[I2C_IDX_TXCOM], SP_DEVICE_IDH_REG, &idh))638return false;639640anx6345->chipid = (u8)idl | ((u8)idh << 8);641642if (regmap_read(anx6345->map[I2C_IDX_TXCOM], SP_DEVICE_VERSION_REG,643&version))644return false;645646for (i = 0; i < ARRAY_SIZE(anx6345_chipid_list); i++) {647if (anx6345->chipid == anx6345_chipid_list[i]) {648DRM_INFO("Found ANX%x (ver. %d) eDP Transmitter\n",649anx6345->chipid, version);650return true;651}652}653654DRM_ERROR("ANX%x (ver. %d) not supported by this driver\n",655anx6345->chipid, version);656657return false;658}659660static int anx6345_i2c_probe(struct i2c_client *client)661{662struct anx6345 *anx6345;663struct device *dev;664int i, err;665666anx6345 = devm_drm_bridge_alloc(&client->dev, struct anx6345, bridge,667&anx6345_bridge_funcs);668if (IS_ERR(anx6345))669return PTR_ERR(anx6345);670671mutex_init(&anx6345->lock);672673anx6345->bridge.of_node = client->dev.of_node;674675anx6345->client = client;676i2c_set_clientdata(client, anx6345);677678dev = &anx6345->client->dev;679680err = drm_of_find_panel_or_bridge(client->dev.of_node, 1, 0,681&anx6345->panel, NULL);682if (err == -EPROBE_DEFER)683return err;684685if (err)686DRM_DEBUG("No panel found\n");687688/* 1.2V digital core power regulator */689anx6345->dvdd12 = devm_regulator_get(dev, "dvdd12");690if (IS_ERR(anx6345->dvdd12)) {691if (PTR_ERR(anx6345->dvdd12) != -EPROBE_DEFER)692DRM_ERROR("Failed to get dvdd12 supply (%ld)\n",693PTR_ERR(anx6345->dvdd12));694return PTR_ERR(anx6345->dvdd12);695}696697/* 2.5V digital core power regulator */698anx6345->dvdd25 = devm_regulator_get(dev, "dvdd25");699if (IS_ERR(anx6345->dvdd25)) {700if (PTR_ERR(anx6345->dvdd25) != -EPROBE_DEFER)701DRM_ERROR("Failed to get dvdd25 supply (%ld)\n",702PTR_ERR(anx6345->dvdd25));703return PTR_ERR(anx6345->dvdd25);704}705706/* GPIO for chip reset */707anx6345->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);708if (IS_ERR(anx6345->gpiod_reset)) {709DRM_ERROR("Reset gpio not found\n");710return PTR_ERR(anx6345->gpiod_reset);711}712713/* Map slave addresses of ANX6345 */714for (i = 0; i < I2C_NUM_ADDRESSES; i++) {715if (anx6345_i2c_addresses[i] >> 1 != client->addr)716anx6345->i2c_clients[i] = i2c_new_dummy_device(client->adapter,717anx6345_i2c_addresses[i] >> 1);718else719anx6345->i2c_clients[i] = client;720721if (IS_ERR(anx6345->i2c_clients[i])) {722err = PTR_ERR(anx6345->i2c_clients[i]);723DRM_ERROR("Failed to reserve I2C bus %02x\n",724anx6345_i2c_addresses[i]);725goto err_unregister_i2c;726}727728anx6345->map[i] = devm_regmap_init_i2c(anx6345->i2c_clients[i],729&anx6345_regmap_config);730if (IS_ERR(anx6345->map[i])) {731err = PTR_ERR(anx6345->map[i]);732DRM_ERROR("Failed regmap initialization %02x\n",733anx6345_i2c_addresses[i]);734goto err_unregister_i2c;735}736}737738/* Look for supported chip ID */739anx6345_poweron(anx6345);740if (anx6345_get_chip_id(anx6345)) {741drm_bridge_add(&anx6345->bridge);742743return 0;744} else {745anx6345_poweroff(anx6345);746err = -ENODEV;747}748749err_unregister_i2c:750unregister_i2c_dummy_clients(anx6345);751return err;752}753754static void anx6345_i2c_remove(struct i2c_client *client)755{756struct anx6345 *anx6345 = i2c_get_clientdata(client);757758drm_bridge_remove(&anx6345->bridge);759760unregister_i2c_dummy_clients(anx6345);761762drm_edid_free(anx6345->drm_edid);763764mutex_destroy(&anx6345->lock);765}766767static const struct i2c_device_id anx6345_id[] = {768{ "anx6345" },769{ /* sentinel */ }770};771MODULE_DEVICE_TABLE(i2c, anx6345_id);772773static const struct of_device_id anx6345_match_table[] = {774{ .compatible = "analogix,anx6345", },775{ /* sentinel */ },776};777MODULE_DEVICE_TABLE(of, anx6345_match_table);778779static struct i2c_driver anx6345_driver = {780.driver = {781.name = "anx6345",782.of_match_table = anx6345_match_table,783},784.probe = anx6345_i2c_probe,785.remove = anx6345_i2c_remove,786.id_table = anx6345_id,787};788module_i2c_driver(anx6345_driver);789790MODULE_DESCRIPTION("ANX6345 eDP Transmitter driver");791MODULE_AUTHOR("Icenowy Zheng <[email protected]>");792MODULE_LICENSE("GPL v2");793794795