CoCalc -- analogix-i2c-dptx.h

GitHub Repository: torvalds/linux
Path: blob/master/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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 * Copyright(c) 2016, Analogix Semiconductor.
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 *
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 * Based on anx7808 driver obtained from chromeos with copyright:
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 * Copyright(c) 2013, Google Inc.
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 */
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#ifndef _ANALOGIX_I2C_DPTX_H_
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#define _ANALOGIX_I2C_DPTX_H_
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/***************************************************************/
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/* Register definitions for TX_P0                              */
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/***************************************************************/
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/* HDCP Status Register */
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#define SP_TX_HDCP_STATUS_REG		0x00
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#define SP_AUTH_FAIL			BIT(5)
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#define SP_AUTHEN_PASS			BIT(1)
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/* HDCP Control Register 0 */
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#define SP_HDCP_CTRL0_REG		0x01
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#define SP_RX_REPEATER			BIT(6)
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#define SP_RE_AUTH			BIT(5)
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#define SP_SW_AUTH_OK			BIT(4)
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#define SP_HARD_AUTH_EN			BIT(3)
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#define SP_HDCP_ENC_EN			BIT(2)
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#define SP_BKSV_SRM_PASS		BIT(1)
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#define SP_KSVLIST_VLD			BIT(0)
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/* HDCP Function Enabled */
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#define SP_HDCP_FUNCTION_ENABLED	(BIT(0) | BIT(1) | BIT(2) | BIT(3))
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/* HDCP Receiver BSTATUS Register 0 */
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#define	SP_HDCP_RX_BSTATUS0_REG		0x1b
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/* HDCP Receiver BSTATUS Register 1 */
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#define	SP_HDCP_RX_BSTATUS1_REG		0x1c
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/* HDCP Embedded "Blue Screen" Content Registers */
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#define SP_HDCP_VID0_BLUE_SCREEN_REG	0x2c
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#define SP_HDCP_VID1_BLUE_SCREEN_REG	0x2d
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#define SP_HDCP_VID2_BLUE_SCREEN_REG	0x2e
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/* HDCP Wait R0 Timing Register */
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#define SP_HDCP_WAIT_R0_TIME_REG	0x40
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/* HDCP Link Integrity Check Timer Register */
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#define SP_HDCP_LINK_CHECK_TIMER_REG	0x41
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/* HDCP Repeater Ready Wait Timer Register */
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#define SP_HDCP_RPTR_RDY_WAIT_TIME_REG	0x42
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/* HDCP Auto Timer Register */
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#define SP_HDCP_AUTO_TIMER_REG		0x51
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/* HDCP Key Status Register */
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#define SP_HDCP_KEY_STATUS_REG		0x5e
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/* HDCP Key Command Register */
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#define SP_HDCP_KEY_COMMAND_REG		0x5f
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#define SP_DISABLE_SYNC_HDCP		BIT(2)
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/* OTP Memory Key Protection Registers */
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#define SP_OTP_KEY_PROTECT1_REG		0x60
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#define SP_OTP_KEY_PROTECT2_REG		0x61
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#define SP_OTP_KEY_PROTECT3_REG		0x62
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#define SP_OTP_PSW1			0xa2
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#define SP_OTP_PSW2			0x7e
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#define SP_OTP_PSW3			0xc6
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/* DP System Control Registers */
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#define SP_DP_SYSTEM_CTRL_BASE		(0x80 - 1)
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/* Bits for DP System Control Register 2 */
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#define SP_CHA_STA			BIT(2)
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/* Bits for DP System Control Register 3 */
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#define SP_HPD_STATUS			BIT(6)
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#define SP_HPD_FORCE			BIT(5)
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#define SP_HPD_CTRL			BIT(4)
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#define SP_STRM_VALID			BIT(2)
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#define SP_STRM_FORCE			BIT(1)
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#define SP_STRM_CTRL			BIT(0)
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/* Bits for DP System Control Register 4 */
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#define SP_ENHANCED_MODE		BIT(3)
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/* DP Video Control Register */
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#define SP_DP_VIDEO_CTRL_REG		0x84
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#define SP_COLOR_F_MASK			0x06
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#define SP_COLOR_F_SHIFT		1
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#define SP_BPC_MASK			0xe0
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#define SP_BPC_SHIFT			5
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#  define SP_BPC_6BITS			0x00
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#  define SP_BPC_8BITS			0x01
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#  define SP_BPC_10BITS			0x02
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#  define SP_BPC_12BITS			0x03
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/* DP Audio Control Register */
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#define SP_DP_AUDIO_CTRL_REG		0x87
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#define SP_AUD_EN			BIT(0)
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/* 10us Pulse Generate Timer Registers */
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#define SP_I2C_GEN_10US_TIMER0_REG	0x88
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#define SP_I2C_GEN_10US_TIMER1_REG	0x89
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/* Packet Send Control Register */
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#define SP_PACKET_SEND_CTRL_REG		0x90
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#define SP_AUD_IF_UP			BIT(7)
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#define SP_AVI_IF_UD			BIT(6)
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#define SP_MPEG_IF_UD			BIT(5)
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#define SP_SPD_IF_UD			BIT(4)
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#define SP_AUD_IF_EN			BIT(3)
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#define SP_AVI_IF_EN			BIT(2)
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#define SP_MPEG_IF_EN			BIT(1)
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#define SP_SPD_IF_EN			BIT(0)
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/* DP HDCP Control Register */
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#define SP_DP_HDCP_CTRL_REG		0x92
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#define SP_AUTO_EN			BIT(7)
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#define SP_AUTO_START			BIT(5)
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#define SP_LINK_POLLING			BIT(1)
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/* DP Main Link Bandwidth Setting Register */
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#define SP_DP_MAIN_LINK_BW_SET_REG	0xa0
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#define SP_LINK_BW_SET_MASK		0x1f
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#define SP_INITIAL_SLIM_M_AUD_SEL	BIT(5)
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/* DP Lane Count Setting Register */
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#define SP_DP_LANE_COUNT_SET_REG	0xa1
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/* DP Training Pattern Set Register */
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#define SP_DP_TRAINING_PATTERN_SET_REG	0xa2
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/* DP Lane 0 Link Training Control Register */
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#define SP_DP_LANE0_LT_CTRL_REG		0xa3
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#define SP_TX_SW_SET_MASK		0x1b
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#define SP_MAX_PRE_REACH		BIT(5)
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#define SP_MAX_DRIVE_REACH		BIT(4)
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#define SP_PRE_EMP_LEVEL1		BIT(3)
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#define SP_DRVIE_CURRENT_LEVEL1		BIT(0)
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/* DP Link Training Control Register */
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#define SP_DP_LT_CTRL_REG		0xa8
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#define SP_DP_LT_INPROGRESS		0x80
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#define SP_LT_ERROR_TYPE_MASK		0x70
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#  define SP_LT_NO_ERROR		0x00
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#  define SP_LT_AUX_WRITE_ERROR		0x01
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#  define SP_LT_MAX_DRIVE_REACHED	0x02
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#  define SP_LT_WRONG_LANE_COUNT_SET	0x03
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#  define SP_LT_LOOP_SAME_5_TIME	0x04
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#  define SP_LT_CR_FAIL_IN_EQ		0x05
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#  define SP_LT_EQ_LOOP_5_TIME		0x06
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#define SP_LT_EN			BIT(0)
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/* DP CEP Training Control Registers */
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#define SP_DP_CEP_TRAINING_CTRL0_REG	0xa9
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#define SP_DP_CEP_TRAINING_CTRL1_REG	0xaa
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/* DP Debug Register 1 */
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#define SP_DP_DEBUG1_REG		0xb0
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#define SP_DEBUG_PLL_LOCK		BIT(4)
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#define SP_POLLING_EN			BIT(1)
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/* DP Polling Control Register */
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#define SP_DP_POLLING_CTRL_REG		0xb4
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#define SP_AUTO_POLLING_DISABLE		BIT(0)
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/* DP Link Debug Control Register */
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#define SP_DP_LINK_DEBUG_CTRL_REG	0xb8
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#define SP_M_VID_DEBUG			BIT(5)
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#define SP_NEW_PRBS7			BIT(4)
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#define SP_INSERT_ER			BIT(1)
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#define SP_PRBS31_EN			BIT(0)
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/* AUX Misc control Register */
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#define SP_AUX_MISC_CTRL_REG		0xbf
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/* DP PLL control Register */
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#define SP_DP_PLL_CTRL_REG		0xc7
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#define SP_PLL_RST			BIT(6)
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/* DP Analog Power Down Register */
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#define SP_DP_ANALOG_POWER_DOWN_REG	0xc8
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#define SP_CH0_PD			BIT(0)
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/* DP Misc Control Register */
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#define SP_DP_MISC_CTRL_REG		0xcd
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#define SP_EQ_TRAINING_LOOP		BIT(6)
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/* DP Extra I2C Device Address Register */
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#define SP_DP_EXTRA_I2C_DEV_ADDR_REG	0xce
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#define SP_I2C_STRETCH_DISABLE		BIT(7)
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#define SP_I2C_EXTRA_ADDR		0x50
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/* DP Downspread Control Register 1 */
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#define SP_DP_DOWNSPREAD_CTRL1_REG	0xd0
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/* DP M Value Calculation Control Register */
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#define SP_DP_M_CALCULATION_CTRL_REG	0xd9
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#define SP_M_GEN_CLK_SEL		BIT(0)
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/* AUX Channel Access Status Register */
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#define SP_AUX_CH_STATUS_REG		0xe0
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#define SP_AUX_STATUS			0x0f
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/* AUX Channel DEFER Control Register */
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#define SP_AUX_DEFER_CTRL_REG		0xe2
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#define SP_DEFER_CTRL_EN		BIT(7)
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/* DP Buffer Data Count Register */
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#define SP_BUF_DATA_COUNT_REG		0xe4
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#define SP_BUF_DATA_COUNT_MASK		0x1f
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#define SP_BUF_CLR			BIT(7)
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/* DP AUX Channel Control Register 1 */
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#define SP_DP_AUX_CH_CTRL1_REG		0xe5
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#define SP_AUX_TX_COMM_MASK		0x0f
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#define SP_AUX_LENGTH_MASK		0xf0
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#define SP_AUX_LENGTH_SHIFT		4
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/* DP AUX CH Address Register 0 */
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#define SP_AUX_ADDR_7_0_REG		0xe6
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/* DP AUX CH Address Register 1 */
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#define SP_AUX_ADDR_15_8_REG		0xe7
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/* DP AUX CH Address Register 2 */
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#define SP_AUX_ADDR_19_16_REG		0xe8
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#define SP_AUX_ADDR_19_16_MASK		0x0f
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/* DP AUX Channel Control Register 2 */
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#define SP_DP_AUX_CH_CTRL2_REG		0xe9
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#define SP_AUX_SEL_RXCM			BIT(6)
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#define SP_AUX_CHSEL			BIT(3)
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#define SP_AUX_PN_INV			BIT(2)
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#define SP_ADDR_ONLY			BIT(1)
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#define SP_AUX_EN			BIT(0)
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/* DP Video Stream Control InfoFrame Register */
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#define SP_DP_3D_VSC_CTRL_REG		0xea
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#define SP_INFO_FRAME_VSC_EN		BIT(0)
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/* DP Video Stream Data Byte 1 Register */
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#define SP_DP_VSC_DB1_REG		0xeb
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/* DP AUX Channel Control Register 3 */
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#define SP_DP_AUX_CH_CTRL3_REG		0xec
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#define SP_WAIT_COUNTER_7_0_MASK	0xff
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/* DP AUX Channel Control Register 4 */
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#define SP_DP_AUX_CH_CTRL4_REG		0xed
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/* DP AUX Buffer Data Registers */
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#define SP_DP_BUF_DATA0_REG		0xf0
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ssize_t anx_dp_aux_transfer(struct regmap *map_dptx,
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				struct drm_dp_aux_msg *msg);
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#endif
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