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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.c
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// SPDX-License-Identifier: GPL-2.0

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/*

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 * TI j721e Cadence MHDP8546 DP wrapper

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 *

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 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/

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 * Author: Jyri Sarha <[email protected]>

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 */

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#include <linux/io.h>

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#include <linux/platform_device.h>

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#include "cdns-mhdp8546-j721e.h"

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#define	REVISION			0x00

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#define	DPTX_IPCFG			0x04

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#define	ECC_MEM_CFG			0x08

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#define	DPTX_DSC_CFG			0x0c

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#define	DPTX_SRC_CFG			0x10

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#define	DPTX_VIF_SECURE_MODE_CFG	0x14

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#define	DPTX_VIF_CONN_STATUS		0x18

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#define	PHY_CLK_STATUS			0x1c

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#define DPTX_SRC_AIF_EN			BIT(16)

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#define DPTX_SRC_VIF_3_IN30B		BIT(11)

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#define DPTX_SRC_VIF_2_IN30B		BIT(10)

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#define DPTX_SRC_VIF_1_IN30B		BIT(9)

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#define DPTX_SRC_VIF_0_IN30B		BIT(8)

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#define DPTX_SRC_VIF_3_SEL_DPI5		BIT(7)

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#define DPTX_SRC_VIF_3_SEL_DPI3		0

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#define DPTX_SRC_VIF_2_SEL_DPI4		BIT(6)

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#define DPTX_SRC_VIF_2_SEL_DPI2		0

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#define DPTX_SRC_VIF_1_SEL_DPI3		BIT(5)

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#define DPTX_SRC_VIF_1_SEL_DPI1		0

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#define DPTX_SRC_VIF_0_SEL_DPI2		BIT(4)

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#define DPTX_SRC_VIF_0_SEL_DPI0		0

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#define DPTX_SRC_VIF_3_EN		BIT(3)

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#define DPTX_SRC_VIF_2_EN		BIT(2)

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#define DPTX_SRC_VIF_1_EN		BIT(1)

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#define DPTX_SRC_VIF_0_EN		BIT(0)

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/* TODO turn DPTX_IPCFG fw_mem_clk_en at pm_runtime_suspend. */

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static int cdns_mhdp_j721e_init(struct cdns_mhdp_device *mhdp)

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{

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	struct platform_device *pdev = to_platform_device(mhdp->dev);

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	mhdp->j721e_regs = devm_platform_ioremap_resource(pdev, 1);

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	return PTR_ERR_OR_ZERO(mhdp->j721e_regs);

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}

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static void cdns_mhdp_j721e_enable(struct cdns_mhdp_device *mhdp)

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{

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	/*

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	 * Enable VIF_0 and select DPI2 as its input. DSS0 DPI0 is connected

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	 * to eDP DPI2. This is the only supported SST configuration on

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	 * J721E.

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	 */

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	writel(DPTX_SRC_VIF_0_EN | DPTX_SRC_VIF_0_SEL_DPI2,

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	       mhdp->j721e_regs + DPTX_SRC_CFG);

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}

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static void cdns_mhdp_j721e_disable(struct cdns_mhdp_device *mhdp)

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{

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	/* Put everything to defaults  */

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	writel(0, mhdp->j721e_regs + DPTX_DSC_CFG);

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}

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const struct mhdp_platform_ops mhdp_ti_j721e_ops = {

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	.init = cdns_mhdp_j721e_init,

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	.enable = cdns_mhdp_j721e_enable,

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	.disable = cdns_mhdp_j721e_disable,

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};

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const u32

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mhdp_ti_j721e_bridge_input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |

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				       DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE |

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				       DRM_BUS_FLAG_DE_HIGH;

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