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torvalds
GitHub Repository: torvalds/linux
Path: blob/master/drivers/gpu/drm/bridge/ti-dlpc3433.c
26494 views
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2021 RenewOutReach
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* Copyright (C) 2021 Amarula Solutions(India)
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*
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* Author:
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* Jagan Teki <[email protected]>
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* Christopher Vollo <[email protected]>
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*/
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_of.h>
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#include <drm/drm_print.h>
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#include <drm/drm_mipi_dsi.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/i2c.h>
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#include <linux/media-bus-format.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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enum cmd_registers {
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WR_INPUT_SOURCE = 0x05, /* Write Input Source Select */
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WR_EXT_SOURCE_FMT = 0x07, /* Write External Video Source Format */
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WR_IMAGE_CROP = 0x10, /* Write Image Crop */
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WR_DISPLAY_SIZE = 0x12, /* Write Display Size */
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WR_IMAGE_FREEZE = 0x1A, /* Write Image Freeze */
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WR_INPUT_IMAGE_SIZE = 0x2E, /* Write External Input Image Size */
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WR_RGB_LED_EN = 0x52, /* Write RGB LED Enable */
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WR_RGB_LED_CURRENT = 0x54, /* Write RGB LED Current */
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WR_RGB_LED_MAX_CURRENT = 0x5C, /* Write RGB LED Max Current */
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WR_DSI_HS_CLK = 0xBD, /* Write DSI HS Clock */
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RD_DEVICE_ID = 0xD4, /* Read Controller Device ID */
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WR_DSI_PORT_EN = 0xD7, /* Write DSI Port Enable */
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};
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enum input_source {
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INPUT_EXTERNAL_VIDEO = 0,
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INPUT_TEST_PATTERN,
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INPUT_SPLASH_SCREEN,
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};
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#define DEV_ID_MASK GENMASK(3, 0)
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#define IMAGE_FREESE_EN BIT(0)
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#define DSI_PORT_EN 0
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#define EXT_SOURCE_FMT_DSI 0
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#define RED_LED_EN BIT(0)
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#define GREEN_LED_EN BIT(1)
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#define BLUE_LED_EN BIT(2)
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#define LED_MASK GENMASK(2, 0)
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#define MAX_BYTE_SIZE 8
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struct dlpc {
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struct device *dev;
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struct drm_bridge bridge;
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struct drm_bridge *next_bridge;
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struct device_node *host_node;
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struct mipi_dsi_device *dsi;
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struct drm_display_mode mode;
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struct gpio_desc *enable_gpio;
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struct regulator *vcc_intf;
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struct regulator *vcc_flsh;
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struct regmap *regmap;
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unsigned int dsi_lanes;
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};
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static inline struct dlpc *bridge_to_dlpc(struct drm_bridge *bridge)
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{
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return container_of(bridge, struct dlpc, bridge);
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}
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static bool dlpc_writeable_noinc_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case WR_IMAGE_CROP:
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case WR_DISPLAY_SIZE:
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case WR_INPUT_IMAGE_SIZE:
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case WR_DSI_HS_CLK:
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return true;
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default:
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return false;
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}
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}
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static const struct regmap_range dlpc_volatile_ranges[] = {
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{ .range_min = 0x10, .range_max = 0xBF },
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};
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static const struct regmap_access_table dlpc_volatile_table = {
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.yes_ranges = dlpc_volatile_ranges,
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.n_yes_ranges = ARRAY_SIZE(dlpc_volatile_ranges),
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};
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static const struct regmap_config dlpc_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = WR_DSI_PORT_EN,
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.writeable_noinc_reg = dlpc_writeable_noinc_reg,
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.volatile_table = &dlpc_volatile_table,
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.cache_type = REGCACHE_MAPLE,
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.name = "dlpc3433",
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};
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static void dlpc_atomic_enable(struct drm_bridge *bridge,
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struct drm_atomic_state *state)
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{
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struct dlpc *dlpc = bridge_to_dlpc(bridge);
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struct device *dev = dlpc->dev;
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struct drm_display_mode *mode = &dlpc->mode;
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struct regmap *regmap = dlpc->regmap;
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char buf[MAX_BYTE_SIZE];
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unsigned int devid;
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regmap_read(regmap, RD_DEVICE_ID, &devid);
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devid &= DEV_ID_MASK;
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DRM_DEV_DEBUG(dev, "DLPC3433 device id: 0x%02x\n", devid);
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if (devid != 0x01) {
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DRM_DEV_ERROR(dev, "Unsupported DLPC device id: 0x%02x\n", devid);
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return;
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}
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/* disable image freeze */
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regmap_write(regmap, WR_IMAGE_FREEZE, IMAGE_FREESE_EN);
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/* enable DSI port */
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regmap_write(regmap, WR_DSI_PORT_EN, DSI_PORT_EN);
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memset(buf, 0, MAX_BYTE_SIZE);
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/* set image crop */
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buf[4] = mode->hdisplay & 0xff;
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buf[5] = (mode->hdisplay & 0xff00) >> 8;
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buf[6] = mode->vdisplay & 0xff;
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buf[7] = (mode->vdisplay & 0xff00) >> 8;
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regmap_noinc_write(regmap, WR_IMAGE_CROP, buf, MAX_BYTE_SIZE);
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/* set display size */
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buf[4] = mode->hdisplay & 0xff;
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buf[5] = (mode->hdisplay & 0xff00) >> 8;
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buf[6] = mode->vdisplay & 0xff;
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buf[7] = (mode->vdisplay & 0xff00) >> 8;
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regmap_noinc_write(regmap, WR_DISPLAY_SIZE, buf, MAX_BYTE_SIZE);
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/* set input image size */
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buf[0] = mode->hdisplay & 0xff;
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buf[1] = (mode->hdisplay & 0xff00) >> 8;
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buf[2] = mode->vdisplay & 0xff;
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buf[3] = (mode->vdisplay & 0xff00) >> 8;
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regmap_noinc_write(regmap, WR_INPUT_IMAGE_SIZE, buf, 4);
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/* set external video port */
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regmap_write(regmap, WR_INPUT_SOURCE, INPUT_EXTERNAL_VIDEO);
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/* set external video format select as DSI */
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regmap_write(regmap, WR_EXT_SOURCE_FMT, EXT_SOURCE_FMT_DSI);
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/* disable image freeze */
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regmap_write(regmap, WR_IMAGE_FREEZE, 0x00);
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/* enable RGB led */
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regmap_update_bits(regmap, WR_RGB_LED_EN, LED_MASK,
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RED_LED_EN | GREEN_LED_EN | BLUE_LED_EN);
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msleep(10);
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}
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static void dlpc_atomic_pre_enable(struct drm_bridge *bridge,
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struct drm_atomic_state *state)
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{
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struct dlpc *dlpc = bridge_to_dlpc(bridge);
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int ret;
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gpiod_set_value(dlpc->enable_gpio, 1);
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msleep(500);
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ret = regulator_enable(dlpc->vcc_intf);
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if (ret)
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DRM_DEV_ERROR(dlpc->dev,
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"failed to enable VCC_INTF regulator: %d\n", ret);
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ret = regulator_enable(dlpc->vcc_flsh);
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if (ret)
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DRM_DEV_ERROR(dlpc->dev,
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"failed to enable VCC_FLSH regulator: %d\n", ret);
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msleep(10);
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}
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static void dlpc_atomic_post_disable(struct drm_bridge *bridge,
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struct drm_atomic_state *state)
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{
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struct dlpc *dlpc = bridge_to_dlpc(bridge);
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regulator_disable(dlpc->vcc_flsh);
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regulator_disable(dlpc->vcc_intf);
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msleep(10);
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gpiod_set_value(dlpc->enable_gpio, 0);
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msleep(500);
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}
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#define MAX_INPUT_SEL_FORMATS 1
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static u32 *
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dlpc_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
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struct drm_bridge_state *bridge_state,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state,
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u32 output_fmt,
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unsigned int *num_input_fmts)
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{
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u32 *input_fmts;
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*num_input_fmts = 0;
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input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
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GFP_KERNEL);
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if (!input_fmts)
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return NULL;
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/* This is the DSI-end bus format */
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input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
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*num_input_fmts = 1;
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return input_fmts;
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}
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static void dlpc_mode_set(struct drm_bridge *bridge,
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const struct drm_display_mode *mode,
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const struct drm_display_mode *adjusted_mode)
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{
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struct dlpc *dlpc = bridge_to_dlpc(bridge);
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drm_mode_copy(&dlpc->mode, adjusted_mode);
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}
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static int dlpc_attach(struct drm_bridge *bridge, struct drm_encoder *encoder,
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enum drm_bridge_attach_flags flags)
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{
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struct dlpc *dlpc = bridge_to_dlpc(bridge);
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return drm_bridge_attach(encoder, dlpc->next_bridge, bridge, flags);
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}
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static const struct drm_bridge_funcs dlpc_bridge_funcs = {
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.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
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.atomic_get_input_bus_fmts = dlpc_atomic_get_input_bus_fmts,
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.atomic_reset = drm_atomic_helper_bridge_reset,
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.atomic_pre_enable = dlpc_atomic_pre_enable,
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.atomic_enable = dlpc_atomic_enable,
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.atomic_post_disable = dlpc_atomic_post_disable,
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.mode_set = dlpc_mode_set,
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.attach = dlpc_attach,
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};
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static int dlpc3433_parse_dt(struct dlpc *dlpc)
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{
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struct device *dev = dlpc->dev;
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struct device_node *endpoint;
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int ret;
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dlpc->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
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if (IS_ERR(dlpc->enable_gpio))
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return PTR_ERR(dlpc->enable_gpio);
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dlpc->vcc_intf = devm_regulator_get(dlpc->dev, "vcc_intf");
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if (IS_ERR(dlpc->vcc_intf))
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return dev_err_probe(dev, PTR_ERR(dlpc->vcc_intf),
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"failed to get VCC_INTF supply\n");
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dlpc->vcc_flsh = devm_regulator_get(dlpc->dev, "vcc_flsh");
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if (IS_ERR(dlpc->vcc_flsh))
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return dev_err_probe(dev, PTR_ERR(dlpc->vcc_flsh),
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"failed to get VCC_FLSH supply\n");
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dlpc->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
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if (IS_ERR(dlpc->next_bridge))
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return PTR_ERR(dlpc->next_bridge);
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endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);
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dlpc->dsi_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
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if (dlpc->dsi_lanes < 0 || dlpc->dsi_lanes > 4) {
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ret = -EINVAL;
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goto err_put_endpoint;
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}
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dlpc->host_node = of_graph_get_remote_port_parent(endpoint);
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if (!dlpc->host_node) {
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ret = -ENODEV;
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goto err_put_host;
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}
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of_node_put(endpoint);
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return 0;
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err_put_host:
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of_node_put(dlpc->host_node);
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err_put_endpoint:
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of_node_put(endpoint);
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return ret;
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}
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static int dlpc_host_attach(struct dlpc *dlpc)
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{
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struct device *dev = dlpc->dev;
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struct mipi_dsi_host *host;
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struct mipi_dsi_device_info info = {
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.type = "dlpc3433",
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.channel = 0,
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.node = NULL,
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};
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int ret;
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host = of_find_mipi_dsi_host_by_node(dlpc->host_node);
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if (!host)
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return dev_err_probe(dev, -EPROBE_DEFER, "failed to find dsi host\n");
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dlpc->dsi = mipi_dsi_device_register_full(host, &info);
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if (IS_ERR(dlpc->dsi)) {
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DRM_DEV_ERROR(dev, "failed to create dsi device\n");
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return PTR_ERR(dlpc->dsi);
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}
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dlpc->dsi->mode_flags = MIPI_DSI_MODE_VIDEO_BURST;
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dlpc->dsi->format = MIPI_DSI_FMT_RGB565;
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dlpc->dsi->lanes = dlpc->dsi_lanes;
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ret = devm_mipi_dsi_attach(dev, dlpc->dsi);
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if (ret)
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DRM_DEV_ERROR(dev, "failed to attach dsi host\n");
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return ret;
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}
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static int dlpc3433_probe(struct i2c_client *client)
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{
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struct device *dev = &client->dev;
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struct dlpc *dlpc;
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int ret;
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dlpc = devm_drm_bridge_alloc(dev, struct dlpc, bridge,
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&dlpc_bridge_funcs);
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if (IS_ERR(dlpc))
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return PTR_ERR(dlpc);
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dlpc->dev = dev;
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dlpc->regmap = devm_regmap_init_i2c(client, &dlpc_regmap_config);
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if (IS_ERR(dlpc->regmap))
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return PTR_ERR(dlpc->regmap);
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ret = dlpc3433_parse_dt(dlpc);
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if (ret)
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return ret;
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dev_set_drvdata(dev, dlpc);
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i2c_set_clientdata(client, dlpc);
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dlpc->bridge.of_node = dev->of_node;
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drm_bridge_add(&dlpc->bridge);
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ret = dlpc_host_attach(dlpc);
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if (ret)
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goto err_remove_bridge;
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return 0;
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err_remove_bridge:
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drm_bridge_remove(&dlpc->bridge);
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return ret;
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}
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static void dlpc3433_remove(struct i2c_client *client)
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{
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struct dlpc *dlpc = i2c_get_clientdata(client);
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drm_bridge_remove(&dlpc->bridge);
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of_node_put(dlpc->host_node);
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}
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static const struct i2c_device_id dlpc3433_id[] = {
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{ "ti,dlpc3433" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(i2c, dlpc3433_id);
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static const struct of_device_id dlpc3433_match_table[] = {
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{ .compatible = "ti,dlpc3433" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, dlpc3433_match_table);
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static struct i2c_driver dlpc3433_driver = {
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.probe = dlpc3433_probe,
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.remove = dlpc3433_remove,
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.id_table = dlpc3433_id,
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.driver = {
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.name = "ti-dlpc3433",
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.of_match_table = dlpc3433_match_table,
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},
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};
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module_i2c_driver(dlpc3433_driver);
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MODULE_AUTHOR("Jagan Teki <[email protected]>");
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MODULE_AUTHOR("Christopher Vollo <[email protected]>");
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MODULE_DESCRIPTION("TI DLPC3433 MIPI DSI Display Controller Bridge");
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MODULE_LICENSE("GPL");
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