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torvalds
GitHub Repository: torvalds/linux
Path: blob/master/drivers/gpu/drm/display/drm_hdmi_helper.c
26494 views
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// SPDX-License-Identifier: MIT
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#include <linux/export.h>
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#include <linux/module.h>
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#include <drm/display/drm_hdmi_helper.h>
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#include <drm/drm_connector.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_modes.h>
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#include <drm/drm_print.h>
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#include <drm/drm_property.h>
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static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
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{
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return sink_eotf & BIT(output_eotf);
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}
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/**
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* drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
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* HDR metadata from userspace
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* @frame: HDMI DRM infoframe
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* @conn_state: Connector state containing HDR metadata
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*
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* Return: 0 on success or a negative error code on failure.
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*/
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int drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
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const struct drm_connector_state *conn_state)
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{
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struct drm_connector *connector;
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struct hdr_output_metadata *hdr_metadata;
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int err;
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if (!frame || !conn_state)
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return -EINVAL;
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connector = conn_state->connector;
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if (!conn_state->hdr_output_metadata)
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return -EINVAL;
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hdr_metadata = conn_state->hdr_output_metadata->data;
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if (!hdr_metadata || !connector)
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return -EINVAL;
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/* Sink EOTF is Bit map while infoframe is absolute values */
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if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
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connector->display_info.hdr_sink_metadata.hdmi_type1.eotf))
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DRM_DEBUG_KMS("Unknown EOTF %d\n", hdr_metadata->hdmi_metadata_type1.eotf);
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err = hdmi_drm_infoframe_init(frame);
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if (err < 0)
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return err;
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frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
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frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
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BUILD_BUG_ON(sizeof(frame->display_primaries) !=
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sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
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BUILD_BUG_ON(sizeof(frame->white_point) !=
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sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
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memcpy(&frame->display_primaries,
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&hdr_metadata->hdmi_metadata_type1.display_primaries,
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sizeof(frame->display_primaries));
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memcpy(&frame->white_point,
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&hdr_metadata->hdmi_metadata_type1.white_point,
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sizeof(frame->white_point));
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frame->max_display_mastering_luminance =
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hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
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frame->min_display_mastering_luminance =
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hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
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frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
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frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
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return 0;
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}
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EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
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/* HDMI Colorspace Spec Definitions */
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#define FULL_COLORIMETRY_MASK 0x1FF
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#define NORMAL_COLORIMETRY_MASK 0x3
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#define EXTENDED_COLORIMETRY_MASK 0x7
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#define EXTENDED_ACE_COLORIMETRY_MASK 0xF
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#define C(x) ((x) << 0)
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#define EC(x) ((x) << 2)
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#define ACE(x) ((x) << 5)
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#define HDMI_COLORIMETRY_NO_DATA 0x0
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#define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
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#define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
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#define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
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#define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
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#define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
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#define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
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#define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
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#define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
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#define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
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#define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
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#define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
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#define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
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static const u32 hdmi_colorimetry_val[] = {
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[DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
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[DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
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[DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
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[DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
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[DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
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[DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
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[DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
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[DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
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[DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
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[DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
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[DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
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};
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#undef C
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#undef EC
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#undef ACE
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/**
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* drm_hdmi_avi_infoframe_colorimetry() - fill the HDMI AVI infoframe
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* colorimetry information
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* @frame: HDMI AVI infoframe
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* @conn_state: connector state
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*/
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void drm_hdmi_avi_infoframe_colorimetry(struct hdmi_avi_infoframe *frame,
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const struct drm_connector_state *conn_state)
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{
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u32 colorimetry_val;
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u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
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if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
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colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
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else
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colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
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frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
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/*
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* ToDo: Extend it for ACE formats as well. Modify the infoframe
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* structure and extend it in drivers/video/hdmi
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*/
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frame->extended_colorimetry = (colorimetry_val >> 2) &
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EXTENDED_COLORIMETRY_MASK;
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}
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EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorimetry);
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/**
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* drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
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* bar information
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* @frame: HDMI AVI infoframe
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* @conn_state: connector state
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*/
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void drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
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const struct drm_connector_state *conn_state)
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{
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frame->right_bar = conn_state->tv.margins.right;
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frame->left_bar = conn_state->tv.margins.left;
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frame->top_bar = conn_state->tv.margins.top;
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frame->bottom_bar = conn_state->tv.margins.bottom;
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}
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EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
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/**
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* drm_hdmi_avi_infoframe_content_type() - fill the HDMI AVI infoframe
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* content type information, based
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* on correspondent DRM property.
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* @frame: HDMI AVI infoframe
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* @conn_state: DRM display connector state
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*
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*/
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void drm_hdmi_avi_infoframe_content_type(struct hdmi_avi_infoframe *frame,
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const struct drm_connector_state *conn_state)
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{
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switch (conn_state->content_type) {
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case DRM_MODE_CONTENT_TYPE_GRAPHICS:
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frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
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break;
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case DRM_MODE_CONTENT_TYPE_CINEMA:
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frame->content_type = HDMI_CONTENT_TYPE_CINEMA;
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break;
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case DRM_MODE_CONTENT_TYPE_GAME:
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frame->content_type = HDMI_CONTENT_TYPE_GAME;
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break;
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case DRM_MODE_CONTENT_TYPE_PHOTO:
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frame->content_type = HDMI_CONTENT_TYPE_PHOTO;
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break;
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default:
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/* Graphics is the default(0) */
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frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
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}
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frame->itc = conn_state->content_type != DRM_MODE_CONTENT_TYPE_NO_DATA;
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}
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EXPORT_SYMBOL(drm_hdmi_avi_infoframe_content_type);
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/**
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* drm_hdmi_compute_mode_clock() - Computes the TMDS Character Rate
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* @mode: Display mode to compute the clock for
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* @bpc: Bits per character
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* @fmt: Output Pixel Format used
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*
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* Returns the TMDS Character Rate for a given mode, bpc count and output format.
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*
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* RETURNS:
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* The TMDS Character Rate, in Hertz, or 0 on error.
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*/
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unsigned long long
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drm_hdmi_compute_mode_clock(const struct drm_display_mode *mode,
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unsigned int bpc, enum hdmi_colorspace fmt)
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{
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unsigned long long clock = mode->clock * 1000ULL;
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unsigned int vic = drm_match_cea_mode(mode);
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/*
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* CTA-861-G Spec, section 5.4 - Color Coding and Quantization
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* mandates that VIC 1 always uses 8 bpc.
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*/
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if (vic == 1 && bpc != 8)
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return 0;
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if (fmt == HDMI_COLORSPACE_YUV422) {
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/*
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* HDMI 1.0 Spec, section 6.5 - Pixel Encoding states that
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* YUV422 sends 24 bits over three channels, with Cb and Cr
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* components being sent on odd and even pixels, respectively.
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*
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* If fewer than 12 bpc are sent, data are left justified.
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*/
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if (bpc > 12)
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return 0;
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/*
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* HDMI 1.0 Spec, section 6.5 - Pixel Encoding
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* specifies that YUV422 sends two 12-bits components over
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* three TMDS channels per pixel clock, which is equivalent to
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* three 8-bits components over three channels used by RGB as
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* far as the clock rate goes.
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*/
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bpc = 8;
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}
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/*
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* HDMI 2.0 Spec, Section 7.1 - YCbCr 4:2:0 Pixel Encoding
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* specifies that YUV420 encoding is carried at a TMDS Character Rate
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* equal to half the pixel clock rate.
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*/
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if (fmt == HDMI_COLORSPACE_YUV420)
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clock = clock / 2;
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if (mode->flags & DRM_MODE_FLAG_DBLCLK)
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clock = clock * 2;
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return DIV_ROUND_CLOSEST_ULL(clock * bpc, 8);
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}
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EXPORT_SYMBOL(drm_hdmi_compute_mode_clock);
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struct drm_hdmi_acr_n_cts_entry {
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unsigned int n;
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unsigned int cts;
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};
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struct drm_hdmi_acr_data {
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unsigned long tmds_clock_khz;
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struct drm_hdmi_acr_n_cts_entry n_cts_32k,
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n_cts_44k1,
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n_cts_48k;
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};
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static const struct drm_hdmi_acr_data hdmi_acr_n_cts[] = {
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{
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/* "Other" entry */
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.n_cts_32k = { .n = 4096, },
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.n_cts_44k1 = { .n = 6272, },
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.n_cts_48k = { .n = 6144, },
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}, {
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.tmds_clock_khz = 25175,
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.n_cts_32k = { .n = 4576, .cts = 28125, },
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.n_cts_44k1 = { .n = 7007, .cts = 31250, },
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.n_cts_48k = { .n = 6864, .cts = 28125, },
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}, {
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.tmds_clock_khz = 25200,
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.n_cts_32k = { .n = 4096, .cts = 25200, },
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.n_cts_44k1 = { .n = 6272, .cts = 28000, },
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.n_cts_48k = { .n = 6144, .cts = 25200, },
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}, {
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.tmds_clock_khz = 27000,
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.n_cts_32k = { .n = 4096, .cts = 27000, },
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.n_cts_44k1 = { .n = 6272, .cts = 30000, },
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.n_cts_48k = { .n = 6144, .cts = 27000, },
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}, {
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.tmds_clock_khz = 27027,
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.n_cts_32k = { .n = 4096, .cts = 27027, },
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.n_cts_44k1 = { .n = 6272, .cts = 30030, },
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.n_cts_48k = { .n = 6144, .cts = 27027, },
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}, {
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.tmds_clock_khz = 54000,
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.n_cts_32k = { .n = 4096, .cts = 54000, },
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.n_cts_44k1 = { .n = 6272, .cts = 60000, },
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.n_cts_48k = { .n = 6144, .cts = 54000, },
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}, {
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.tmds_clock_khz = 54054,
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.n_cts_32k = { .n = 4096, .cts = 54054, },
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.n_cts_44k1 = { .n = 6272, .cts = 60060, },
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.n_cts_48k = { .n = 6144, .cts = 54054, },
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}, {
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.tmds_clock_khz = 74176,
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.n_cts_32k = { .n = 11648, .cts = 210937, }, /* and 210938 */
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.n_cts_44k1 = { .n = 17836, .cts = 234375, },
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.n_cts_48k = { .n = 11648, .cts = 140625, },
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}, {
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.tmds_clock_khz = 74250,
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.n_cts_32k = { .n = 4096, .cts = 74250, },
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.n_cts_44k1 = { .n = 6272, .cts = 82500, },
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.n_cts_48k = { .n = 6144, .cts = 74250, },
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}, {
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.tmds_clock_khz = 148352,
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.n_cts_32k = { .n = 11648, .cts = 421875, },
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.n_cts_44k1 = { .n = 8918, .cts = 234375, },
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.n_cts_48k = { .n = 5824, .cts = 140625, },
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}, {
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.tmds_clock_khz = 148500,
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.n_cts_32k = { .n = 4096, .cts = 148500, },
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.n_cts_44k1 = { .n = 6272, .cts = 165000, },
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.n_cts_48k = { .n = 6144, .cts = 148500, },
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}, {
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.tmds_clock_khz = 296703,
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.n_cts_32k = { .n = 5824, .cts = 421875, },
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.n_cts_44k1 = { .n = 4459, .cts = 234375, },
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.n_cts_48k = { .n = 5824, .cts = 281250, },
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}, {
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.tmds_clock_khz = 297000,
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.n_cts_32k = { .n = 3072, .cts = 222750, },
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.n_cts_44k1 = { .n = 4704, .cts = 247500, },
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.n_cts_48k = { .n = 5120, .cts = 247500, },
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}, {
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.tmds_clock_khz = 593407,
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.n_cts_32k = { .n = 5824, .cts = 843750, },
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.n_cts_44k1 = { .n = 8918, .cts = 937500, },
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.n_cts_48k = { .n = 5824, .cts = 562500, },
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}, {
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.tmds_clock_khz = 594000,
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.n_cts_32k = { .n = 3072, .cts = 445500, },
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.n_cts_44k1 = { .n = 9408, .cts = 990000, },
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.n_cts_48k = { .n = 6144, .cts = 594000, },
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},
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};
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static int drm_hdmi_acr_find_tmds_entry(unsigned long tmds_clock_khz)
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{
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int i;
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/* skip the "other" entry */
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for (i = 1; i < ARRAY_SIZE(hdmi_acr_n_cts); i++) {
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if (hdmi_acr_n_cts[i].tmds_clock_khz == tmds_clock_khz)
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return i;
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}
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return 0;
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}
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/**
366
* drm_hdmi_acr_get_n_cts() - get N and CTS values for Audio Clock Regeneration
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*
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* @tmds_char_rate: TMDS clock (char rate) as used by the HDMI connector
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* @sample_rate: audio sample rate
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* @out_n: a pointer to write the N value
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* @out_cts: a pointer to write the CTS value
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*
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* Get the N and CTS values (either by calculating them or by returning data
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* from the tables. This follows the HDMI 1.4b Section 7.2 "Audio Sample Clock
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* Capture and Regeneration".
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*
377
* Note, @sample_rate corresponds to the Fs value, see sections 7.2.4 - 7.2.6
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* on how to select Fs for non-L-PCM formats.
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*/
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void
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drm_hdmi_acr_get_n_cts(unsigned long long tmds_char_rate,
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unsigned int sample_rate,
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unsigned int *out_n,
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unsigned int *out_cts)
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{
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/* be a bit more tolerant, especially for the 1.001 entries */
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unsigned long tmds_clock_khz = DIV_ROUND_CLOSEST_ULL(tmds_char_rate, 1000);
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const struct drm_hdmi_acr_n_cts_entry *entry;
389
unsigned int n, cts, mult;
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int tmds_idx;
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tmds_idx = drm_hdmi_acr_find_tmds_entry(tmds_clock_khz);
393
394
/*
395
* Don't change the order, 192 kHz is divisible by 48k and 32k, but it
396
* should use 48k entry.
397
*/
398
if (sample_rate % 48000 == 0) {
399
entry = &hdmi_acr_n_cts[tmds_idx].n_cts_48k;
400
mult = sample_rate / 48000;
401
} else if (sample_rate % 44100 == 0) {
402
entry = &hdmi_acr_n_cts[tmds_idx].n_cts_44k1;
403
mult = sample_rate / 44100;
404
} else if (sample_rate % 32000 == 0) {
405
entry = &hdmi_acr_n_cts[tmds_idx].n_cts_32k;
406
mult = sample_rate / 32000;
407
} else {
408
entry = NULL;
409
}
410
411
if (entry) {
412
n = entry->n * mult;
413
cts = entry->cts;
414
} else {
415
/* Recommended optimal value, HDMI 1.4b, Section 7.2.1 */
416
n = 128 * sample_rate / 1000;
417
cts = 0;
418
}
419
420
if (!cts)
421
cts = DIV_ROUND_CLOSEST_ULL(tmds_char_rate * n,
422
128 * sample_rate);
423
424
*out_n = n;
425
*out_cts = cts;
426
}
427
EXPORT_SYMBOL(drm_hdmi_acr_get_n_cts);
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