CoCalc -- drm

GitHub Repository: torvalds/linux
Path: blob/master/drivers/gpu/drm/drm_edid.c
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/*
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 * Copyright (c) 2006 Luc Verhaegen (quirks list)
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 * Copyright (c) 2007-2008 Intel Corporation
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 *   Jesse Barnes <[email protected]>
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 * Copyright 2010 Red Hat, Inc.
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 *
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 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
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 * FB layer.
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 *   Copyright (C) 2006 Dennis Munsie <[email protected]>
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a
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 * copy of this software and associated documentation files (the "Software"),
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 * to deal in the Software without restriction, including without limitation
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 * the rights to use, copy, modify, merge, publish, distribute, sub license,
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 * and/or sell copies of the Software, and to permit persons to whom the
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 * Software is furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice (including the
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 * next paragraph) shall be included in all copies or substantial portions
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 * of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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 * DEALINGS IN THE SOFTWARE.
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 */
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#include <linux/bitfield.h>
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#include <linux/byteorder/generic.h>
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#include <linux/cec.h>
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#include <linux/export.h>
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#include <linux/hdmi.h>
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#include <linux/i2c.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/seq_buf.h>
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#include <linux/slab.h>
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#include <linux/vga_switcheroo.h>
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#include <drm/drm_drv.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_eld.h>
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#include <drm/drm_encoder.h>
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#include <drm/drm_print.h>
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#include "drm_crtc_internal.h"
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#include "drm_displayid_internal.h"
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#include "drm_internal.h"
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static int oui(u8 first, u8 second, u8 third)
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{
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	return (first << 16) | (second << 8) | third;
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}
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#define EDID_EST_TIMINGS 16
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#define EDID_STD_TIMINGS 8
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#define EDID_DETAILED_TIMINGS 4
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/*
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 * EDID blocks out in the wild have a variety of bugs, try to collect
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 * them here (note that userspace may work around broken monitors first,
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 * but fixes should make their way here so that the kernel "just works"
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 * on as many displays as possible).
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 */
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enum drm_edid_internal_quirk {
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	/* First detailed mode wrong, use largest 60Hz mode */
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	EDID_QUIRK_PREFER_LARGE_60 = DRM_EDID_QUIRK_NUM,
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	/* Reported 135MHz pixel clock is too high, needs adjustment */
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	EDID_QUIRK_135_CLOCK_TOO_HIGH,
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	/* Prefer the largest mode at 75 Hz */
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	EDID_QUIRK_PREFER_LARGE_75,
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	/* Detail timing is in cm not mm */
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	EDID_QUIRK_DETAILED_IN_CM,
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	/* Detailed timing descriptors have bogus size values, so just take the
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	 * maximum size and use that.
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	 */
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	EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE,
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	/* use +hsync +vsync for detailed mode */
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	EDID_QUIRK_DETAILED_SYNC_PP,
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	/* Force reduced-blanking timings for detailed modes */
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	EDID_QUIRK_FORCE_REDUCED_BLANKING,
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	/* Force 8bpc */
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	EDID_QUIRK_FORCE_8BPC,
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	/* Force 12bpc */
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	EDID_QUIRK_FORCE_12BPC,
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	/* Force 6bpc */
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	EDID_QUIRK_FORCE_6BPC,
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	/* Force 10bpc */
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	EDID_QUIRK_FORCE_10BPC,
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	/* Non desktop display (i.e. HMD) */
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	EDID_QUIRK_NON_DESKTOP,
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	/* Cap the DSC target bitrate to 15bpp */
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	EDID_QUIRK_CAP_DSC_15BPP,
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};
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#define MICROSOFT_IEEE_OUI	0xca125c
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struct detailed_mode_closure {
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	struct drm_connector *connector;
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	const struct drm_edid *drm_edid;
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	bool preferred;
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	int modes;
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};
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struct drm_edid_match_closure {
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	const struct drm_edid_ident *ident;
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	bool matched;
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};
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#define LEVEL_DMT	0
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#define LEVEL_GTF	1
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#define LEVEL_GTF2	2
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#define LEVEL_CVT	3
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#define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
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{ \
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	.ident = { \
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		.panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, \
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						     vend_chr_2, product_id), \
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	}, \
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	.quirks = _quirks \
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}
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static const struct edid_quirk {
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	const struct drm_edid_ident ident;
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	u32 quirks;
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} edid_quirk_list[] = {
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	/* Acer AL1706 */
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	EDID_QUIRK('A', 'C', 'R', 44358, BIT(EDID_QUIRK_PREFER_LARGE_60)),
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	/* Acer F51 */
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	EDID_QUIRK('A', 'P', 'I', 0x7602, BIT(EDID_QUIRK_PREFER_LARGE_60)),
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	/* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
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	EDID_QUIRK('A', 'E', 'O', 0, BIT(EDID_QUIRK_FORCE_6BPC)),
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	/* BenQ GW2765 */
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	EDID_QUIRK('B', 'N', 'Q', 0x78d6, BIT(EDID_QUIRK_FORCE_8BPC)),
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	/* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
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	EDID_QUIRK('B', 'O', 'E', 0x78b, BIT(EDID_QUIRK_FORCE_6BPC)),
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	/* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
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	EDID_QUIRK('C', 'P', 'T', 0x17df, BIT(EDID_QUIRK_FORCE_6BPC)),
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	/* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
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	EDID_QUIRK('S', 'D', 'C', 0x3652, BIT(EDID_QUIRK_FORCE_6BPC)),
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	/* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
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	EDID_QUIRK('B', 'O', 'E', 0x0771, BIT(EDID_QUIRK_FORCE_6BPC)),
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	/* Belinea 10 15 55 */
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	EDID_QUIRK('M', 'A', 'X', 1516, BIT(EDID_QUIRK_PREFER_LARGE_60)),
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	EDID_QUIRK('M', 'A', 'X', 0x77e, BIT(EDID_QUIRK_PREFER_LARGE_60)),
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	/* Envision Peripherals, Inc. EN-7100e */
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	EDID_QUIRK('E', 'P', 'I', 59264, BIT(EDID_QUIRK_135_CLOCK_TOO_HIGH)),
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	/* Envision EN2028 */
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	EDID_QUIRK('E', 'P', 'I', 8232, BIT(EDID_QUIRK_PREFER_LARGE_60)),
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	/* Funai Electronics PM36B */
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	EDID_QUIRK('F', 'C', 'M', 13600, BIT(EDID_QUIRK_PREFER_LARGE_75) |
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					 BIT(EDID_QUIRK_DETAILED_IN_CM)),
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	/* LG 27GP950 */
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	EDID_QUIRK('G', 'S', 'M', 0x5bbf, BIT(EDID_QUIRK_CAP_DSC_15BPP)),
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	/* LG 27GN950 */
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	EDID_QUIRK('G', 'S', 'M', 0x5b9a, BIT(EDID_QUIRK_CAP_DSC_15BPP)),
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	/* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
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	EDID_QUIRK('L', 'G', 'D', 764, BIT(EDID_QUIRK_FORCE_10BPC)),
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	/* LG Philips LCD LP154W01-A5 */
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	EDID_QUIRK('L', 'P', 'L', 0, BIT(EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE)),
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	EDID_QUIRK('L', 'P', 'L', 0x2a00, BIT(EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE)),
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	/* Samsung SyncMaster 205BW.  Note: irony */
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	EDID_QUIRK('S', 'A', 'M', 541, BIT(EDID_QUIRK_DETAILED_SYNC_PP)),
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	/* Samsung SyncMaster 22[5-6]BW */
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	EDID_QUIRK('S', 'A', 'M', 596, BIT(EDID_QUIRK_PREFER_LARGE_60)),
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	EDID_QUIRK('S', 'A', 'M', 638, BIT(EDID_QUIRK_PREFER_LARGE_60)),
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	/* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
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	EDID_QUIRK('S', 'N', 'Y', 0x2541, BIT(EDID_QUIRK_FORCE_12BPC)),
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	/* ViewSonic VA2026w */
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	EDID_QUIRK('V', 'S', 'C', 5020, BIT(EDID_QUIRK_FORCE_REDUCED_BLANKING)),
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	/* Medion MD 30217 PG */
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	EDID_QUIRK('M', 'E', 'D', 0x7b8, BIT(EDID_QUIRK_PREFER_LARGE_75)),
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	/* Lenovo G50 */
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	EDID_QUIRK('S', 'D', 'C', 18514, BIT(EDID_QUIRK_FORCE_6BPC)),
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	/* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
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	EDID_QUIRK('S', 'E', 'C', 0xd033, BIT(EDID_QUIRK_FORCE_8BPC)),
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	/* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
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	EDID_QUIRK('E', 'T', 'R', 13896, BIT(EDID_QUIRK_FORCE_8BPC)),
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	/* Valve Index Headset */
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	EDID_QUIRK('V', 'L', 'V', 0x91a8, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('V', 'L', 'V', 0x91b0, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('V', 'L', 'V', 0x91b1, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('V', 'L', 'V', 0x91b2, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('V', 'L', 'V', 0x91b3, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('V', 'L', 'V', 0x91b4, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('V', 'L', 'V', 0x91b5, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('V', 'L', 'V', 0x91b6, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('V', 'L', 'V', 0x91b7, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('V', 'L', 'V', 0x91b8, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('V', 'L', 'V', 0x91b9, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('V', 'L', 'V', 0x91ba, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('V', 'L', 'V', 0x91bb, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('V', 'L', 'V', 0x91bc, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('V', 'L', 'V', 0x91bd, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('V', 'L', 'V', 0x91be, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('V', 'L', 'V', 0x91bf, BIT(EDID_QUIRK_NON_DESKTOP)),
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	/* HTC Vive and Vive Pro VR Headsets */
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	EDID_QUIRK('H', 'V', 'R', 0xaa01, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('H', 'V', 'R', 0xaa02, BIT(EDID_QUIRK_NON_DESKTOP)),
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	/* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
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	EDID_QUIRK('O', 'V', 'R', 0x0001, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('O', 'V', 'R', 0x0003, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('O', 'V', 'R', 0x0004, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('O', 'V', 'R', 0x0012, BIT(EDID_QUIRK_NON_DESKTOP)),
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	/* Windows Mixed Reality Headsets */
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	EDID_QUIRK('A', 'C', 'R', 0x7fce, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('L', 'E', 'N', 0x0408, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('F', 'U', 'J', 0x1970, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('D', 'E', 'L', 0x7fce, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('S', 'E', 'C', 0x144a, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('A', 'U', 'S', 0xc102, BIT(EDID_QUIRK_NON_DESKTOP)),
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	/* Sony PlayStation VR Headset */
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	EDID_QUIRK('S', 'N', 'Y', 0x0704, BIT(EDID_QUIRK_NON_DESKTOP)),
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	/* Sensics VR Headsets */
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	EDID_QUIRK('S', 'E', 'N', 0x1019, BIT(EDID_QUIRK_NON_DESKTOP)),
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	/* OSVR HDK and HDK2 VR Headsets */
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	EDID_QUIRK('S', 'V', 'R', 0x1019, BIT(EDID_QUIRK_NON_DESKTOP)),
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	EDID_QUIRK('A', 'U', 'O', 0x1111, BIT(EDID_QUIRK_NON_DESKTOP)),
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	/*
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	 * @drm_edid_internal_quirk entries end here, following with the
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	 * @drm_edid_quirk entries.
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	 */
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	/* HP ZR24w DP AUX DPCD access requires probing to prevent corruption. */
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	EDID_QUIRK('H', 'W', 'P', 0x2869, BIT(DRM_EDID_QUIRK_DP_DPCD_PROBE)),
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};
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/*
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 * Autogenerated from the DMT spec.
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 * This table is copied from xfree86/modes/xf86EdidModes.c.
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 */
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static const struct drm_display_mode drm_dmt_modes[] = {
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	/* 0x01 - 640x350@85Hz */
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	{ DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
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		   736, 832, 0, 350, 382, 385, 445, 0,
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		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
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	/* 0x02 - 640x400@85Hz */
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	{ DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
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		   736, 832, 0, 400, 401, 404, 445, 0,
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		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
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	/* 0x03 - 720x400@85Hz */
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	{ DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
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		   828, 936, 0, 400, 401, 404, 446, 0,
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		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
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	/* 0x04 - 640x480@60Hz */
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	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
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		   752, 800, 0, 480, 490, 492, 525, 0,
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		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
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	/* 0x05 - 640x480@72Hz */
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	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
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		   704, 832, 0, 480, 489, 492, 520, 0,
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		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
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	/* 0x06 - 640x480@75Hz */
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	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
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		   720, 840, 0, 480, 481, 484, 500, 0,
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		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
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	/* 0x07 - 640x480@85Hz */
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	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
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		   752, 832, 0, 480, 481, 484, 509, 0,
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		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
295
	/* 0x08 - 800x600@56Hz */
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	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
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		   896, 1024, 0, 600, 601, 603, 625, 0,
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		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
299
	/* 0x09 - 800x600@60Hz */
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	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
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		   968, 1056, 0, 600, 601, 605, 628, 0,
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		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
303
	/* 0x0a - 800x600@72Hz */
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	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
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		   976, 1040, 0, 600, 637, 643, 666, 0,
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		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
307
	/* 0x0b - 800x600@75Hz */
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	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
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		   896, 1056, 0, 600, 601, 604, 625, 0,
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		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
311
	/* 0x0c - 800x600@85Hz */
312
	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
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		   896, 1048, 0, 600, 601, 604, 631, 0,
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		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
315
	/* 0x0d - 800x600@120Hz RB */
316
	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
317
		   880, 960, 0, 600, 603, 607, 636, 0,
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		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
319
	/* 0x0e - 848x480@60Hz */
320
	{ DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
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		   976, 1088, 0, 480, 486, 494, 517, 0,
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		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
323
	/* 0x0f - 1024x768@43Hz, interlace */
324
	{ DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
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		   1208, 1264, 0, 768, 768, 776, 817, 0,
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		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
327
		   DRM_MODE_FLAG_INTERLACE) },
328
	/* 0x10 - 1024x768@60Hz */
329
	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
330
		   1184, 1344, 0, 768, 771, 777, 806, 0,
331
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
332
	/* 0x11 - 1024x768@70Hz */
333
	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
334
		   1184, 1328, 0, 768, 771, 777, 806, 0,
335
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
336
	/* 0x12 - 1024x768@75Hz */
337
	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
338
		   1136, 1312, 0, 768, 769, 772, 800, 0,
339
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
340
	/* 0x13 - 1024x768@85Hz */
341
	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
342
		   1168, 1376, 0, 768, 769, 772, 808, 0,
343
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
344
	/* 0x14 - 1024x768@120Hz RB */
345
	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
346
		   1104, 1184, 0, 768, 771, 775, 813, 0,
347
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
348
	/* 0x15 - 1152x864@75Hz */
349
	{ DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
350
		   1344, 1600, 0, 864, 865, 868, 900, 0,
351
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
352
	/* 0x55 - 1280x720@60Hz */
353
	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
354
		   1430, 1650, 0, 720, 725, 730, 750, 0,
355
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
356
	/* 0x16 - 1280x768@60Hz RB */
357
	{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
358
		   1360, 1440, 0, 768, 771, 778, 790, 0,
359
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
360
	/* 0x17 - 1280x768@60Hz */
361
	{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
362
		   1472, 1664, 0, 768, 771, 778, 798, 0,
363
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
364
	/* 0x18 - 1280x768@75Hz */
365
	{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
366
		   1488, 1696, 0, 768, 771, 778, 805, 0,
367
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
368
	/* 0x19 - 1280x768@85Hz */
369
	{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
370
		   1496, 1712, 0, 768, 771, 778, 809, 0,
371
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
372
	/* 0x1a - 1280x768@120Hz RB */
373
	{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
374
		   1360, 1440, 0, 768, 771, 778, 813, 0,
375
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
376
	/* 0x1b - 1280x800@60Hz RB */
377
	{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
378
		   1360, 1440, 0, 800, 803, 809, 823, 0,
379
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
380
	/* 0x1c - 1280x800@60Hz */
381
	{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
382
		   1480, 1680, 0, 800, 803, 809, 831, 0,
383
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
384
	/* 0x1d - 1280x800@75Hz */
385
	{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
386
		   1488, 1696, 0, 800, 803, 809, 838, 0,
387
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
388
	/* 0x1e - 1280x800@85Hz */
389
	{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
390
		   1496, 1712, 0, 800, 803, 809, 843, 0,
391
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
392
	/* 0x1f - 1280x800@120Hz RB */
393
	{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
394
		   1360, 1440, 0, 800, 803, 809, 847, 0,
395
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
396
	/* 0x20 - 1280x960@60Hz */
397
	{ DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
398
		   1488, 1800, 0, 960, 961, 964, 1000, 0,
399
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
400
	/* 0x21 - 1280x960@85Hz */
401
	{ DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
402
		   1504, 1728, 0, 960, 961, 964, 1011, 0,
403
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
404
	/* 0x22 - 1280x960@120Hz RB */
405
	{ DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
406
		   1360, 1440, 0, 960, 963, 967, 1017, 0,
407
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
408
	/* 0x23 - 1280x1024@60Hz */
409
	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
410
		   1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
411
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
412
	/* 0x24 - 1280x1024@75Hz */
413
	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
414
		   1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
415
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
416
	/* 0x25 - 1280x1024@85Hz */
417
	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
418
		   1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
419
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
420
	/* 0x26 - 1280x1024@120Hz RB */
421
	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
422
		   1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
423
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
424
	/* 0x27 - 1360x768@60Hz */
425
	{ DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
426
		   1536, 1792, 0, 768, 771, 777, 795, 0,
427
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
428
	/* 0x28 - 1360x768@120Hz RB */
429
	{ DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
430
		   1440, 1520, 0, 768, 771, 776, 813, 0,
431
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
432
	/* 0x51 - 1366x768@60Hz */
433
	{ DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
434
		   1579, 1792, 0, 768, 771, 774, 798, 0,
435
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
436
	/* 0x56 - 1366x768@60Hz */
437
	{ DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
438
		   1436, 1500, 0, 768, 769, 772, 800, 0,
439
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
440
	/* 0x29 - 1400x1050@60Hz RB */
441
	{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
442
		   1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
443
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
444
	/* 0x2a - 1400x1050@60Hz */
445
	{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
446
		   1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
447
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
448
	/* 0x2b - 1400x1050@75Hz */
449
	{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
450
		   1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
451
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
452
	/* 0x2c - 1400x1050@85Hz */
453
	{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
454
		   1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
455
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
456
	/* 0x2d - 1400x1050@120Hz RB */
457
	{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
458
		   1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
459
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
460
	/* 0x2e - 1440x900@60Hz RB */
461
	{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
462
		   1520, 1600, 0, 900, 903, 909, 926, 0,
463
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
464
	/* 0x2f - 1440x900@60Hz */
465
	{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
466
		   1672, 1904, 0, 900, 903, 909, 934, 0,
467
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
468
	/* 0x30 - 1440x900@75Hz */
469
	{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
470
		   1688, 1936, 0, 900, 903, 909, 942, 0,
471
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
472
	/* 0x31 - 1440x900@85Hz */
473
	{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
474
		   1696, 1952, 0, 900, 903, 909, 948, 0,
475
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
476
	/* 0x32 - 1440x900@120Hz RB */
477
	{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
478
		   1520, 1600, 0, 900, 903, 909, 953, 0,
479
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
480
	/* 0x53 - 1600x900@60Hz */
481
	{ DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
482
		   1704, 1800, 0, 900, 901, 904, 1000, 0,
483
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
484
	/* 0x33 - 1600x1200@60Hz */
485
	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
486
		   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
487
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
488
	/* 0x34 - 1600x1200@65Hz */
489
	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
490
		   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
491
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
492
	/* 0x35 - 1600x1200@70Hz */
493
	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
494
		   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
495
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
496
	/* 0x36 - 1600x1200@75Hz */
497
	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
498
		   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
499
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
500
	/* 0x37 - 1600x1200@85Hz */
501
	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
502
		   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
503
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
504
	/* 0x38 - 1600x1200@120Hz RB */
505
	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
506
		   1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
507
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
508
	/* 0x39 - 1680x1050@60Hz RB */
509
	{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
510
		   1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
511
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
512
	/* 0x3a - 1680x1050@60Hz */
513
	{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
514
		   1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
515
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
516
	/* 0x3b - 1680x1050@75Hz */
517
	{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
518
		   1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
519
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
520
	/* 0x3c - 1680x1050@85Hz */
521
	{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
522
		   1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
523
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
524
	/* 0x3d - 1680x1050@120Hz RB */
525
	{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
526
		   1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
527
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
528
	/* 0x3e - 1792x1344@60Hz */
529
	{ DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
530
		   2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
531
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
532
	/* 0x3f - 1792x1344@75Hz */
533
	{ DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
534
		   2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
535
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
536
	/* 0x40 - 1792x1344@120Hz RB */
537
	{ DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
538
		   1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
539
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
540
	/* 0x41 - 1856x1392@60Hz */
541
	{ DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
542
		   2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
543
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
544
	/* 0x42 - 1856x1392@75Hz */
545
	{ DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
546
		   2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
547
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
548
	/* 0x43 - 1856x1392@120Hz RB */
549
	{ DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
550
		   1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
551
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
552
	/* 0x52 - 1920x1080@60Hz */
553
	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
554
		   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
555
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
556
	/* 0x44 - 1920x1200@60Hz RB */
557
	{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
558
		   2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
559
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
560
	/* 0x45 - 1920x1200@60Hz */
561
	{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
562
		   2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
563
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
564
	/* 0x46 - 1920x1200@75Hz */
565
	{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
566
		   2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
567
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
568
	/* 0x47 - 1920x1200@85Hz */
569
	{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
570
		   2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
571
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
572
	/* 0x48 - 1920x1200@120Hz RB */
573
	{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
574
		   2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
575
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
576
	/* 0x49 - 1920x1440@60Hz */
577
	{ DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
578
		   2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
579
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
580
	/* 0x4a - 1920x1440@75Hz */
581
	{ DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
582
		   2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
583
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
584
	/* 0x4b - 1920x1440@120Hz RB */
585
	{ DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
586
		   2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
587
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
588
	/* 0x54 - 2048x1152@60Hz */
589
	{ DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
590
		   2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
591
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
592
	/* 0x4c - 2560x1600@60Hz RB */
593
	{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
594
		   2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
595
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
596
	/* 0x4d - 2560x1600@60Hz */
597
	{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
598
		   3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
599
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
600
	/* 0x4e - 2560x1600@75Hz */
601
	{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
602
		   3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
603
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
604
	/* 0x4f - 2560x1600@85Hz */
605
	{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
606
		   3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
607
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
608
	/* 0x50 - 2560x1600@120Hz RB */
609
	{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
610
		   2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
611
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
612
	/* 0x57 - 4096x2160@60Hz RB */
613
	{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
614
		   4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
615
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
616
	/* 0x58 - [email protected] RB */
617
	{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
618
		   4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
619
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
620
};
621

622
/*
623
 * These more or less come from the DMT spec.  The 720x400 modes are
624
 * inferred from historical 80x25 practice.  The 640x480@67 and 832x624@75
625
 * modes are old-school Mac modes.  The EDID spec says the 1152x864@75 mode
626
 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
627
 * mode.
628
 *
629
 * The DMT modes have been fact-checked; the rest are mild guesses.
630
 */
631
static const struct drm_display_mode edid_est_modes[] = {
632
	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
633
		   968, 1056, 0, 600, 601, 605, 628, 0,
634
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
635
	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
636
		   896, 1024, 0, 600, 601, 603,  625, 0,
637
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
638
	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
639
		   720, 840, 0, 480, 481, 484, 500, 0,
640
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
641
	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
642
		   704,  832, 0, 480, 489, 492, 520, 0,
643
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
644
	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
645
		   768,  864, 0, 480, 483, 486, 525, 0,
646
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
647
	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
648
		   752, 800, 0, 480, 490, 492, 525, 0,
649
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
650
	{ DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
651
		   846, 900, 0, 400, 421, 423,  449, 0,
652
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
653
	{ DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
654
		   846,  900, 0, 400, 412, 414, 449, 0,
655
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
656
	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
657
		   1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
658
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
659
	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
660
		   1136, 1312, 0,  768, 769, 772, 800, 0,
661
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
662
	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
663
		   1184, 1328, 0,  768, 771, 777, 806, 0,
664
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
665
	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
666
		   1184, 1344, 0,  768, 771, 777, 806, 0,
667
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
668
	{ DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
669
		   1208, 1264, 0, 768, 768, 776, 817, 0,
670
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
671
	{ DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
672
		   928, 1152, 0, 624, 625, 628, 667, 0,
673
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
674
	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
675
		   896, 1056, 0, 600, 601, 604,  625, 0,
676
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
677
	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
678
		   976, 1040, 0, 600, 637, 643, 666, 0,
679
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
680
	{ DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
681
		   1344, 1600, 0,  864, 865, 868, 900, 0,
682
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
683
};
684

685
struct minimode {
686
	short w;
687
	short h;
688
	short r;
689
	short rb;
690
};
691

692
static const struct minimode est3_modes[] = {
693
	/* byte 6 */
694
	{ 640, 350, 85, 0 },
695
	{ 640, 400, 85, 0 },
696
	{ 720, 400, 85, 0 },
697
	{ 640, 480, 85, 0 },
698
	{ 848, 480, 60, 0 },
699
	{ 800, 600, 85, 0 },
700
	{ 1024, 768, 85, 0 },
701
	{ 1152, 864, 75, 0 },
702
	/* byte 7 */
703
	{ 1280, 768, 60, 1 },
704
	{ 1280, 768, 60, 0 },
705
	{ 1280, 768, 75, 0 },
706
	{ 1280, 768, 85, 0 },
707
	{ 1280, 960, 60, 0 },
708
	{ 1280, 960, 85, 0 },
709
	{ 1280, 1024, 60, 0 },
710
	{ 1280, 1024, 85, 0 },
711
	/* byte 8 */
712
	{ 1360, 768, 60, 0 },
713
	{ 1440, 900, 60, 1 },
714
	{ 1440, 900, 60, 0 },
715
	{ 1440, 900, 75, 0 },
716
	{ 1440, 900, 85, 0 },
717
	{ 1400, 1050, 60, 1 },
718
	{ 1400, 1050, 60, 0 },
719
	{ 1400, 1050, 75, 0 },
720
	/* byte 9 */
721
	{ 1400, 1050, 85, 0 },
722
	{ 1680, 1050, 60, 1 },
723
	{ 1680, 1050, 60, 0 },
724
	{ 1680, 1050, 75, 0 },
725
	{ 1680, 1050, 85, 0 },
726
	{ 1600, 1200, 60, 0 },
727
	{ 1600, 1200, 65, 0 },
728
	{ 1600, 1200, 70, 0 },
729
	/* byte 10 */
730
	{ 1600, 1200, 75, 0 },
731
	{ 1600, 1200, 85, 0 },
732
	{ 1792, 1344, 60, 0 },
733
	{ 1792, 1344, 75, 0 },
734
	{ 1856, 1392, 60, 0 },
735
	{ 1856, 1392, 75, 0 },
736
	{ 1920, 1200, 60, 1 },
737
	{ 1920, 1200, 60, 0 },
738
	/* byte 11 */
739
	{ 1920, 1200, 75, 0 },
740
	{ 1920, 1200, 85, 0 },
741
	{ 1920, 1440, 60, 0 },
742
	{ 1920, 1440, 75, 0 },
743
};
744

745
static const struct minimode extra_modes[] = {
746
	{ 1024, 576,  60, 0 },
747
	{ 1366, 768,  60, 0 },
748
	{ 1600, 900,  60, 0 },
749
	{ 1680, 945,  60, 0 },
750
	{ 1920, 1080, 60, 0 },
751
	{ 2048, 1152, 60, 0 },
752
	{ 2048, 1536, 60, 0 },
753
};
754

755
/*
756
 * From CEA/CTA-861 spec.
757
 *
758
 * Do not access directly, instead always use cea_mode_for_vic().
759
 */
760
static const struct drm_display_mode edid_cea_modes_1[] = {
761
	/* 1 - 640x480@60Hz 4:3 */
762
	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
763
		   752, 800, 0, 480, 490, 492, 525, 0,
764
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
765
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
766
	/* 2 - 720x480@60Hz 4:3 */
767
	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
768
		   798, 858, 0, 480, 489, 495, 525, 0,
769
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
770
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
771
	/* 3 - 720x480@60Hz 16:9 */
772
	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
773
		   798, 858, 0, 480, 489, 495, 525, 0,
774
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
775
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
776
	/* 4 - 1280x720@60Hz 16:9 */
777
	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
778
		   1430, 1650, 0, 720, 725, 730, 750, 0,
779
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
780
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
781
	/* 5 - 1920x1080i@60Hz 16:9 */
782
	{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
783
		   2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
784
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
785
		   DRM_MODE_FLAG_INTERLACE),
786
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
787
	/* 6 - 720(1440)x480i@60Hz 4:3 */
788
	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
789
		   801, 858, 0, 480, 488, 494, 525, 0,
790
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
791
		   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
792
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
793
	/* 7 - 720(1440)x480i@60Hz 16:9 */
794
	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
795
		   801, 858, 0, 480, 488, 494, 525, 0,
796
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
797
		   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
798
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
799
	/* 8 - 720(1440)x240@60Hz 4:3 */
800
	{ DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
801
		   801, 858, 0, 240, 244, 247, 262, 0,
802
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
803
		   DRM_MODE_FLAG_DBLCLK),
804
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
805
	/* 9 - 720(1440)x240@60Hz 16:9 */
806
	{ DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
807
		   801, 858, 0, 240, 244, 247, 262, 0,
808
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
809
		   DRM_MODE_FLAG_DBLCLK),
810
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
811
	/* 10 - 2880x480i@60Hz 4:3 */
812
	{ DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
813
		   3204, 3432, 0, 480, 488, 494, 525, 0,
814
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
815
		   DRM_MODE_FLAG_INTERLACE),
816
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
817
	/* 11 - 2880x480i@60Hz 16:9 */
818
	{ DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
819
		   3204, 3432, 0, 480, 488, 494, 525, 0,
820
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
821
		   DRM_MODE_FLAG_INTERLACE),
822
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
823
	/* 12 - 2880x240@60Hz 4:3 */
824
	{ DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
825
		   3204, 3432, 0, 240, 244, 247, 262, 0,
826
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
827
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
828
	/* 13 - 2880x240@60Hz 16:9 */
829
	{ DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
830
		   3204, 3432, 0, 240, 244, 247, 262, 0,
831
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
832
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
833
	/* 14 - 1440x480@60Hz 4:3 */
834
	{ DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
835
		   1596, 1716, 0, 480, 489, 495, 525, 0,
836
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
837
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
838
	/* 15 - 1440x480@60Hz 16:9 */
839
	{ DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
840
		   1596, 1716, 0, 480, 489, 495, 525, 0,
841
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
842
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
843
	/* 16 - 1920x1080@60Hz 16:9 */
844
	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
845
		   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
846
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
847
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
848
	/* 17 - 720x576@50Hz 4:3 */
849
	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
850
		   796, 864, 0, 576, 581, 586, 625, 0,
851
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
852
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
853
	/* 18 - 720x576@50Hz 16:9 */
854
	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
855
		   796, 864, 0, 576, 581, 586, 625, 0,
856
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
857
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
858
	/* 19 - 1280x720@50Hz 16:9 */
859
	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
860
		   1760, 1980, 0, 720, 725, 730, 750, 0,
861
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
862
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
863
	/* 20 - 1920x1080i@50Hz 16:9 */
864
	{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
865
		   2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
866
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
867
		   DRM_MODE_FLAG_INTERLACE),
868
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
869
	/* 21 - 720(1440)x576i@50Hz 4:3 */
870
	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
871
		   795, 864, 0, 576, 580, 586, 625, 0,
872
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
873
		   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
874
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
875
	/* 22 - 720(1440)x576i@50Hz 16:9 */
876
	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
877
		   795, 864, 0, 576, 580, 586, 625, 0,
878
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
879
		   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
880
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
881
	/* 23 - 720(1440)x288@50Hz 4:3 */
882
	{ DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
883
		   795, 864, 0, 288, 290, 293, 312, 0,
884
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
885
		   DRM_MODE_FLAG_DBLCLK),
886
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
887
	/* 24 - 720(1440)x288@50Hz 16:9 */
888
	{ DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
889
		   795, 864, 0, 288, 290, 293, 312, 0,
890
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
891
		   DRM_MODE_FLAG_DBLCLK),
892
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
893
	/* 25 - 2880x576i@50Hz 4:3 */
894
	{ DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
895
		   3180, 3456, 0, 576, 580, 586, 625, 0,
896
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
897
		   DRM_MODE_FLAG_INTERLACE),
898
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
899
	/* 26 - 2880x576i@50Hz 16:9 */
900
	{ DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
901
		   3180, 3456, 0, 576, 580, 586, 625, 0,
902
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
903
		   DRM_MODE_FLAG_INTERLACE),
904
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
905
	/* 27 - 2880x288@50Hz 4:3 */
906
	{ DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
907
		   3180, 3456, 0, 288, 290, 293, 312, 0,
908
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
909
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
910
	/* 28 - 2880x288@50Hz 16:9 */
911
	{ DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
912
		   3180, 3456, 0, 288, 290, 293, 312, 0,
913
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
914
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
915
	/* 29 - 1440x576@50Hz 4:3 */
916
	{ DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
917
		   1592, 1728, 0, 576, 581, 586, 625, 0,
918
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
919
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
920
	/* 30 - 1440x576@50Hz 16:9 */
921
	{ DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
922
		   1592, 1728, 0, 576, 581, 586, 625, 0,
923
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
924
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
925
	/* 31 - 1920x1080@50Hz 16:9 */
926
	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
927
		   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
928
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
929
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
930
	/* 32 - 1920x1080@24Hz 16:9 */
931
	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
932
		   2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
933
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
934
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
935
	/* 33 - 1920x1080@25Hz 16:9 */
936
	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
937
		   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
938
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
939
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
940
	/* 34 - 1920x1080@30Hz 16:9 */
941
	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
942
		   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
943
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
944
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
945
	/* 35 - 2880x480@60Hz 4:3 */
946
	{ DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
947
		   3192, 3432, 0, 480, 489, 495, 525, 0,
948
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
949
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
950
	/* 36 - 2880x480@60Hz 16:9 */
951
	{ DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
952
		   3192, 3432, 0, 480, 489, 495, 525, 0,
953
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
954
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
955
	/* 37 - 2880x576@50Hz 4:3 */
956
	{ DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
957
		   3184, 3456, 0, 576, 581, 586, 625, 0,
958
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
959
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
960
	/* 38 - 2880x576@50Hz 16:9 */
961
	{ DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
962
		   3184, 3456, 0, 576, 581, 586, 625, 0,
963
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
964
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
965
	/* 39 - 1920x1080i@50Hz 16:9 */
966
	{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
967
		   2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
968
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
969
		   DRM_MODE_FLAG_INTERLACE),
970
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
971
	/* 40 - 1920x1080i@100Hz 16:9 */
972
	{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
973
		   2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
974
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
975
		   DRM_MODE_FLAG_INTERLACE),
976
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
977
	/* 41 - 1280x720@100Hz 16:9 */
978
	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
979
		   1760, 1980, 0, 720, 725, 730, 750, 0,
980
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
981
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
982
	/* 42 - 720x576@100Hz 4:3 */
983
	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
984
		   796, 864, 0, 576, 581, 586, 625, 0,
985
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
986
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
987
	/* 43 - 720x576@100Hz 16:9 */
988
	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
989
		   796, 864, 0, 576, 581, 586, 625, 0,
990
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
991
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
992
	/* 44 - 720(1440)x576i@100Hz 4:3 */
993
	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
994
		   795, 864, 0, 576, 580, 586, 625, 0,
995
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
996
		   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
997
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
998
	/* 45 - 720(1440)x576i@100Hz 16:9 */
999
	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
1000
		   795, 864, 0, 576, 580, 586, 625, 0,
1001
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1002
		   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1003
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1004
	/* 46 - 1920x1080i@120Hz 16:9 */
1005
	{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1006
		   2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
1007
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
1008
		   DRM_MODE_FLAG_INTERLACE),
1009
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1010
	/* 47 - 1280x720@120Hz 16:9 */
1011
	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1012
		   1430, 1650, 0, 720, 725, 730, 750, 0,
1013
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1014
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1015
	/* 48 - 720x480@120Hz 4:3 */
1016
	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
1017
		   798, 858, 0, 480, 489, 495, 525, 0,
1018
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1019
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1020
	/* 49 - 720x480@120Hz 16:9 */
1021
	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
1022
		   798, 858, 0, 480, 489, 495, 525, 0,
1023
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1024
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1025
	/* 50 - 720(1440)x480i@120Hz 4:3 */
1026
	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1027
		   801, 858, 0, 480, 488, 494, 525, 0,
1028
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1029
		   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1030
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1031
	/* 51 - 720(1440)x480i@120Hz 16:9 */
1032
	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1033
		   801, 858, 0, 480, 488, 494, 525, 0,
1034
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1035
		   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1036
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1037
	/* 52 - 720x576@200Hz 4:3 */
1038
	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1039
		   796, 864, 0, 576, 581, 586, 625, 0,
1040
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1041
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1042
	/* 53 - 720x576@200Hz 16:9 */
1043
	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1044
		   796, 864, 0, 576, 581, 586, 625, 0,
1045
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1046
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1047
	/* 54 - 720(1440)x576i@200Hz 4:3 */
1048
	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1049
		   795, 864, 0, 576, 580, 586, 625, 0,
1050
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1051
		   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1052
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1053
	/* 55 - 720(1440)x576i@200Hz 16:9 */
1054
	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1055
		   795, 864, 0, 576, 580, 586, 625, 0,
1056
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1057
		   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1058
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1059
	/* 56 - 720x480@240Hz 4:3 */
1060
	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1061
		   798, 858, 0, 480, 489, 495, 525, 0,
1062
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1063
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1064
	/* 57 - 720x480@240Hz 16:9 */
1065
	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1066
		   798, 858, 0, 480, 489, 495, 525, 0,
1067
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1068
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1069
	/* 58 - 720(1440)x480i@240Hz 4:3 */
1070
	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1071
		   801, 858, 0, 480, 488, 494, 525, 0,
1072
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1073
		   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1074
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1075
	/* 59 - 720(1440)x480i@240Hz 16:9 */
1076
	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1077
		   801, 858, 0, 480, 488, 494, 525, 0,
1078
		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1079
		   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1080
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1081
	/* 60 - 1280x720@24Hz 16:9 */
1082
	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1083
		   3080, 3300, 0, 720, 725, 730, 750, 0,
1084
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1085
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1086
	/* 61 - 1280x720@25Hz 16:9 */
1087
	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1088
		   3740, 3960, 0, 720, 725, 730, 750, 0,
1089
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1090
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1091
	/* 62 - 1280x720@30Hz 16:9 */
1092
	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1093
		   3080, 3300, 0, 720, 725, 730, 750, 0,
1094
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1095
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1096
	/* 63 - 1920x1080@120Hz 16:9 */
1097
	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1098
		   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1099
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1100
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1101
	/* 64 - 1920x1080@100Hz 16:9 */
1102
	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1103
		   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1104
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1105
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1106
	/* 65 - 1280x720@24Hz 64:27 */
1107
	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1108
		   3080, 3300, 0, 720, 725, 730, 750, 0,
1109
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1110
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1111
	/* 66 - 1280x720@25Hz 64:27 */
1112
	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1113
		   3740, 3960, 0, 720, 725, 730, 750, 0,
1114
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1115
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1116
	/* 67 - 1280x720@30Hz 64:27 */
1117
	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1118
		   3080, 3300, 0, 720, 725, 730, 750, 0,
1119
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1120
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1121
	/* 68 - 1280x720@50Hz 64:27 */
1122
	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1123
		   1760, 1980, 0, 720, 725, 730, 750, 0,
1124
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1125
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1126
	/* 69 - 1280x720@60Hz 64:27 */
1127
	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1128
		   1430, 1650, 0, 720, 725, 730, 750, 0,
1129
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1130
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1131
	/* 70 - 1280x720@100Hz 64:27 */
1132
	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1133
		   1760, 1980, 0, 720, 725, 730, 750, 0,
1134
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1135
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1136
	/* 71 - 1280x720@120Hz 64:27 */
1137
	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1138
		   1430, 1650, 0, 720, 725, 730, 750, 0,
1139
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1140
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1141
	/* 72 - 1920x1080@24Hz 64:27 */
1142
	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1143
		   2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1144
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1145
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1146
	/* 73 - 1920x1080@25Hz 64:27 */
1147
	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1148
		   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1149
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1150
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1151
	/* 74 - 1920x1080@30Hz 64:27 */
1152
	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1153
		   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1154
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1155
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1156
	/* 75 - 1920x1080@50Hz 64:27 */
1157
	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1158
		   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1159
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1160
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1161
	/* 76 - 1920x1080@60Hz 64:27 */
1162
	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1163
		   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1164
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1165
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1166
	/* 77 - 1920x1080@100Hz 64:27 */
1167
	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1168
		   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1169
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1170
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1171
	/* 78 - 1920x1080@120Hz 64:27 */
1172
	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1173
		   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1174
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1175
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1176
	/* 79 - 1680x720@24Hz 64:27 */
1177
	{ DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1178
		   3080, 3300, 0, 720, 725, 730, 750, 0,
1179
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1180
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1181
	/* 80 - 1680x720@25Hz 64:27 */
1182
	{ DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1183
		   2948, 3168, 0, 720, 725, 730, 750, 0,
1184
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1185
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1186
	/* 81 - 1680x720@30Hz 64:27 */
1187
	{ DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1188
		   2420, 2640, 0, 720, 725, 730, 750, 0,
1189
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1190
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1191
	/* 82 - 1680x720@50Hz 64:27 */
1192
	{ DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1193
		   1980, 2200, 0, 720, 725, 730, 750, 0,
1194
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1195
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1196
	/* 83 - 1680x720@60Hz 64:27 */
1197
	{ DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1198
		   1980, 2200, 0, 720, 725, 730, 750, 0,
1199
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1200
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1201
	/* 84 - 1680x720@100Hz 64:27 */
1202
	{ DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1203
		   1780, 2000, 0, 720, 725, 730, 825, 0,
1204
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1205
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1206
	/* 85 - 1680x720@120Hz 64:27 */
1207
	{ DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1208
		   1780, 2000, 0, 720, 725, 730, 825, 0,
1209
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1210
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1211
	/* 86 - 2560x1080@24Hz 64:27 */
1212
	{ DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1213
		   3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1214
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1215
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1216
	/* 87 - 2560x1080@25Hz 64:27 */
1217
	{ DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1218
		   3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1219
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1220
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1221
	/* 88 - 2560x1080@30Hz 64:27 */
1222
	{ DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1223
		   3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1224
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1225
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1226
	/* 89 - 2560x1080@50Hz 64:27 */
1227
	{ DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1228
		   3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1229
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1230
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1231
	/* 90 - 2560x1080@60Hz 64:27 */
1232
	{ DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1233
		   2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1234
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1235
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1236
	/* 91 - 2560x1080@100Hz 64:27 */
1237
	{ DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1238
		   2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1239
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1240
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1241
	/* 92 - 2560x1080@120Hz 64:27 */
1242
	{ DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1243
		   3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1244
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1245
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1246
	/* 93 - 3840x2160@24Hz 16:9 */
1247
	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1248
		   5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1249
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1250
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1251
	/* 94 - 3840x2160@25Hz 16:9 */
1252
	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1253
		   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1254
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1255
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1256
	/* 95 - 3840x2160@30Hz 16:9 */
1257
	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1258
		   4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1259
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1260
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1261
	/* 96 - 3840x2160@50Hz 16:9 */
1262
	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1263
		   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1264
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1265
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1266
	/* 97 - 3840x2160@60Hz 16:9 */
1267
	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1268
		   4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1269
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1270
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1271
	/* 98 - 4096x2160@24Hz 256:135 */
1272
	{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1273
		   5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1274
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1275
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1276
	/* 99 - 4096x2160@25Hz 256:135 */
1277
	{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1278
		   5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1279
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1280
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1281
	/* 100 - 4096x2160@30Hz 256:135 */
1282
	{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1283
		   4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1284
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1285
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1286
	/* 101 - 4096x2160@50Hz 256:135 */
1287
	{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1288
		   5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1289
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1290
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1291
	/* 102 - 4096x2160@60Hz 256:135 */
1292
	{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1293
		   4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1294
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1295
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1296
	/* 103 - 3840x2160@24Hz 64:27 */
1297
	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1298
		   5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1299
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1300
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1301
	/* 104 - 3840x2160@25Hz 64:27 */
1302
	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1303
		   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1304
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1305
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1306
	/* 105 - 3840x2160@30Hz 64:27 */
1307
	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1308
		   4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1309
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1310
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1311
	/* 106 - 3840x2160@50Hz 64:27 */
1312
	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1313
		   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1314
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1315
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1316
	/* 107 - 3840x2160@60Hz 64:27 */
1317
	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1318
		   4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1319
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1320
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1321
	/* 108 - 1280x720@48Hz 16:9 */
1322
	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1323
		   2280, 2500, 0, 720, 725, 730, 750, 0,
1324
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1325
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1326
	/* 109 - 1280x720@48Hz 64:27 */
1327
	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1328
		   2280, 2500, 0, 720, 725, 730, 750, 0,
1329
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1330
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1331
	/* 110 - 1680x720@48Hz 64:27 */
1332
	{ DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1333
		   2530, 2750, 0, 720, 725, 730, 750, 0,
1334
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1335
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1336
	/* 111 - 1920x1080@48Hz 16:9 */
1337
	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1338
		   2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1339
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1340
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1341
	/* 112 - 1920x1080@48Hz 64:27 */
1342
	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1343
		   2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1344
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1345
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1346
	/* 113 - 2560x1080@48Hz 64:27 */
1347
	{ DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1348
		   3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1349
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1350
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1351
	/* 114 - 3840x2160@48Hz 16:9 */
1352
	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1353
		   5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1354
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1355
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1356
	/* 115 - 4096x2160@48Hz 256:135 */
1357
	{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1358
		   5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1359
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1360
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1361
	/* 116 - 3840x2160@48Hz 64:27 */
1362
	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1363
		   5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1364
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1365
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1366
	/* 117 - 3840x2160@100Hz 16:9 */
1367
	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1368
		   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1369
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1370
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1371
	/* 118 - 3840x2160@120Hz 16:9 */
1372
	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1373
		   4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1374
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1375
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1376
	/* 119 - 3840x2160@100Hz 64:27 */
1377
	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1378
		   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1379
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1380
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1381
	/* 120 - 3840x2160@120Hz 64:27 */
1382
	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1383
		   4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1384
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1385
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1386
	/* 121 - 5120x2160@24Hz 64:27 */
1387
	{ DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1388
		   7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1389
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1390
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1391
	/* 122 - 5120x2160@25Hz 64:27 */
1392
	{ DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1393
		   6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1394
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1395
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1396
	/* 123 - 5120x2160@30Hz 64:27 */
1397
	{ DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1398
		   5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1399
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1400
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1401
	/* 124 - 5120x2160@48Hz 64:27 */
1402
	{ DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1403
		   5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1404
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1405
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1406
	/* 125 - 5120x2160@50Hz 64:27 */
1407
	{ DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1408
		   6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1409
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1410
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1411
	/* 126 - 5120x2160@60Hz 64:27 */
1412
	{ DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1413
		   5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1414
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1415
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1416
	/* 127 - 5120x2160@100Hz 64:27 */
1417
	{ DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1418
		   6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1419
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1420
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1421
};
1422

1423
/*
1424
 * From CEA/CTA-861 spec.
1425
 *
1426
 * Do not access directly, instead always use cea_mode_for_vic().
1427
 */
1428
static const struct drm_display_mode edid_cea_modes_193[] = {
1429
	/* 193 - 5120x2160@120Hz 64:27 */
1430
	{ DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1431
		   5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1432
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1433
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1434
	/* 194 - 7680x4320@24Hz 16:9 */
1435
	{ DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1436
		   10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1437
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1438
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1439
	/* 195 - 7680x4320@25Hz 16:9 */
1440
	{ DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1441
		   10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1442
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1443
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1444
	/* 196 - 7680x4320@30Hz 16:9 */
1445
	{ DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1446
		   8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1447
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1448
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1449
	/* 197 - 7680x4320@48Hz 16:9 */
1450
	{ DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1451
		   10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1452
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1453
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1454
	/* 198 - 7680x4320@50Hz 16:9 */
1455
	{ DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1456
		   10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1457
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1458
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1459
	/* 199 - 7680x4320@60Hz 16:9 */
1460
	{ DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1461
		   8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1462
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1463
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1464
	/* 200 - 7680x4320@100Hz 16:9 */
1465
	{ DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1466
		   9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1467
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1468
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1469
	/* 201 - 7680x4320@120Hz 16:9 */
1470
	{ DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1471
		   8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1472
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1473
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1474
	/* 202 - 7680x4320@24Hz 64:27 */
1475
	{ DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1476
		   10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1477
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1478
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1479
	/* 203 - 7680x4320@25Hz 64:27 */
1480
	{ DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1481
		   10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1482
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1483
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1484
	/* 204 - 7680x4320@30Hz 64:27 */
1485
	{ DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1486
		   8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1487
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1488
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1489
	/* 205 - 7680x4320@48Hz 64:27 */
1490
	{ DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1491
		   10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1492
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1493
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1494
	/* 206 - 7680x4320@50Hz 64:27 */
1495
	{ DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1496
		   10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1497
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1498
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1499
	/* 207 - 7680x4320@60Hz 64:27 */
1500
	{ DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1501
		   8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1502
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1503
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1504
	/* 208 - 7680x4320@100Hz 64:27 */
1505
	{ DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1506
		   9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1507
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1508
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1509
	/* 209 - 7680x4320@120Hz 64:27 */
1510
	{ DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1511
		   8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1512
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1513
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1514
	/* 210 - 10240x4320@24Hz 64:27 */
1515
	{ DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1516
		   11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1517
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1518
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1519
	/* 211 - 10240x4320@25Hz 64:27 */
1520
	{ DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1521
		   12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1522
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1523
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1524
	/* 212 - 10240x4320@30Hz 64:27 */
1525
	{ DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1526
		   10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1527
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1528
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1529
	/* 213 - 10240x4320@48Hz 64:27 */
1530
	{ DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1531
		   11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1532
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1533
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1534
	/* 214 - 10240x4320@50Hz 64:27 */
1535
	{ DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1536
		   12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1537
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1538
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1539
	/* 215 - 10240x4320@60Hz 64:27 */
1540
	{ DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1541
		   10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1542
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1543
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1544
	/* 216 - 10240x4320@100Hz 64:27 */
1545
	{ DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1546
		   12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1547
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1548
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1549
	/* 217 - 10240x4320@120Hz 64:27 */
1550
	{ DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1551
		   10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1552
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1553
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1554
	/* 218 - 4096x2160@100Hz 256:135 */
1555
	{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1556
		   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1557
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1558
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1559
	/* 219 - 4096x2160@120Hz 256:135 */
1560
	{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1561
		   4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1562
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1563
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1564
};
1565

1566
/*
1567
 * HDMI 1.4 4k modes. Index using the VIC.
1568
 */
1569
static const struct drm_display_mode edid_4k_modes[] = {
1570
	/* 0 - dummy, VICs start at 1 */
1571
	{ },
1572
	/* 1 - 3840x2160@30Hz */
1573
	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1574
		   3840, 4016, 4104, 4400, 0,
1575
		   2160, 2168, 2178, 2250, 0,
1576
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1577
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1578
	/* 2 - 3840x2160@25Hz */
1579
	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1580
		   3840, 4896, 4984, 5280, 0,
1581
		   2160, 2168, 2178, 2250, 0,
1582
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1583
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1584
	/* 3 - 3840x2160@24Hz */
1585
	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1586
		   3840, 5116, 5204, 5500, 0,
1587
		   2160, 2168, 2178, 2250, 0,
1588
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1589
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1590
	/* 4 - 4096x2160@24Hz (SMPTE) */
1591
	{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1592
		   4096, 5116, 5204, 5500, 0,
1593
		   2160, 2168, 2178, 2250, 0,
1594
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1595
	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1596
};
1597

1598
/*** DDC fetch and block validation ***/
1599

1600
/*
1601
 * The opaque EDID type, internal to drm_edid.c.
1602
 */
1603
struct drm_edid {
1604
	/* Size allocated for edid */
1605
	size_t size;
1606
	const struct edid *edid;
1607
};
1608

1609
static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1610

1611
static int edid_hfeeodb_block_count(const struct edid *edid)
1612
{
1613
	int eeodb = edid_hfeeodb_extension_block_count(edid);
1614

1615
	return eeodb ? eeodb + 1 : 0;
1616
}
1617

1618
static int edid_extension_block_count(const struct edid *edid)
1619
{
1620
	return edid->extensions;
1621
}
1622

1623
static int edid_block_count(const struct edid *edid)
1624
{
1625
	return edid_extension_block_count(edid) + 1;
1626
}
1627

1628
static int edid_size_by_blocks(int num_blocks)
1629
{
1630
	return num_blocks * EDID_LENGTH;
1631
}
1632

1633
static int edid_size(const struct edid *edid)
1634
{
1635
	return edid_size_by_blocks(edid_block_count(edid));
1636
}
1637

1638
static const void *edid_block_data(const struct edid *edid, int index)
1639
{
1640
	BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1641

1642
	return edid + index;
1643
}
1644

1645
static const void *edid_extension_block_data(const struct edid *edid, int index)
1646
{
1647
	return edid_block_data(edid, index + 1);
1648
}
1649

1650
/* EDID block count indicated in EDID, may exceed allocated size */
1651
static int __drm_edid_block_count(const struct drm_edid *drm_edid)
1652
{
1653
	int num_blocks;
1654

1655
	/* Starting point */
1656
	num_blocks = edid_block_count(drm_edid->edid);
1657

1658
	/* HF-EEODB override */
1659
	if (drm_edid->size >= edid_size_by_blocks(2)) {
1660
		int eeodb;
1661

1662
		/*
1663
		 * Note: HF-EEODB may specify a smaller extension count than the
1664
		 * regular one. Unlike in buffer allocation, here we can use it.
1665
		 */
1666
		eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1667
		if (eeodb)
1668
			num_blocks = eeodb;
1669
	}
1670

1671
	return num_blocks;
1672
}
1673

1674
/* EDID block count, limited by allocated size */
1675
static int drm_edid_block_count(const struct drm_edid *drm_edid)
1676
{
1677
	/* Limit by allocated size */
1678
	return min(__drm_edid_block_count(drm_edid),
1679
		   (int)drm_edid->size / EDID_LENGTH);
1680
}
1681

1682
/* EDID extension block count, limited by allocated size */
1683
static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1684
{
1685
	return drm_edid_block_count(drm_edid) - 1;
1686
}
1687

1688
static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1689
{
1690
	return edid_block_data(drm_edid->edid, index);
1691
}
1692

1693
static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1694
						 int index)
1695
{
1696
	return edid_extension_block_data(drm_edid->edid, index);
1697
}
1698

1699
/*
1700
 * Initializer helper for legacy interfaces, where we have no choice but to
1701
 * trust edid size. Not for general purpose use.
1702
 */
1703
static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1704
						   const struct edid *edid)
1705
{
1706
	if (!edid)
1707
		return NULL;
1708

1709
	memset(drm_edid, 0, sizeof(*drm_edid));
1710

1711
	drm_edid->edid = edid;
1712
	drm_edid->size = edid_size(edid);
1713

1714
	return drm_edid;
1715
}
1716

1717
/*
1718
 * EDID base and extension block iterator.
1719
 *
1720
 * struct drm_edid_iter iter;
1721
 * const u8 *block;
1722
 *
1723
 * drm_edid_iter_begin(drm_edid, &iter);
1724
 * drm_edid_iter_for_each(block, &iter) {
1725
 *         // do stuff with block
1726
 * }
1727
 * drm_edid_iter_end(&iter);
1728
 */
1729
struct drm_edid_iter {
1730
	const struct drm_edid *drm_edid;
1731

1732
	/* Current block index. */
1733
	int index;
1734
};
1735

1736
static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
1737
				struct drm_edid_iter *iter)
1738
{
1739
	memset(iter, 0, sizeof(*iter));
1740

1741
	iter->drm_edid = drm_edid;
1742
}
1743

1744
static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1745
{
1746
	const void *block = NULL;
1747

1748
	if (!iter->drm_edid)
1749
		return NULL;
1750

1751
	if (iter->index < drm_edid_block_count(iter->drm_edid))
1752
		block = drm_edid_block_data(iter->drm_edid, iter->index++);
1753

1754
	return block;
1755
}
1756

1757
#define drm_edid_iter_for_each(__block, __iter)			\
1758
	while (((__block) = __drm_edid_iter_next(__iter)))
1759

1760
static void drm_edid_iter_end(struct drm_edid_iter *iter)
1761
{
1762
	memset(iter, 0, sizeof(*iter));
1763
}
1764

1765
static const u8 edid_header[] = {
1766
	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1767
};
1768

1769
static void edid_header_fix(void *edid)
1770
{
1771
	memcpy(edid, edid_header, sizeof(edid_header));
1772
}
1773

1774
/**
1775
 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1776
 * @_edid: pointer to raw base EDID block
1777
 *
1778
 * Sanity check the header of the base EDID block.
1779
 *
1780
 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1781
 */
1782
int drm_edid_header_is_valid(const void *_edid)
1783
{
1784
	const struct edid *edid = _edid;
1785
	int i, score = 0;
1786

1787
	for (i = 0; i < sizeof(edid_header); i++) {
1788
		if (edid->header[i] == edid_header[i])
1789
			score++;
1790
	}
1791

1792
	return score;
1793
}
1794
EXPORT_SYMBOL(drm_edid_header_is_valid);
1795

1796
static int edid_fixup __read_mostly = 6;
1797
module_param_named(edid_fixup, edid_fixup, int, 0400);
1798
MODULE_PARM_DESC(edid_fixup,
1799
		 "Minimum number of valid EDID header bytes (0-8, default 6)");
1800

1801
static int edid_block_compute_checksum(const void *_block)
1802
{
1803
	const u8 *block = _block;
1804
	int i;
1805
	u8 csum = 0, crc = 0;
1806

1807
	for (i = 0; i < EDID_LENGTH - 1; i++)
1808
		csum += block[i];
1809

1810
	crc = 0x100 - csum;
1811

1812
	return crc;
1813
}
1814

1815
static int edid_block_get_checksum(const void *_block)
1816
{
1817
	const struct edid *block = _block;
1818

1819
	return block->checksum;
1820
}
1821

1822
static int edid_block_tag(const void *_block)
1823
{
1824
	const u8 *block = _block;
1825

1826
	return block[0];
1827
}
1828

1829
static bool edid_block_is_zero(const void *edid)
1830
{
1831
	return mem_is_zero(edid, EDID_LENGTH);
1832
}
1833

1834
static bool drm_edid_eq(const struct drm_edid *drm_edid,
1835
			const void *raw_edid, size_t raw_edid_size)
1836
{
1837
	bool edid1_present = drm_edid && drm_edid->edid && drm_edid->size;
1838
	bool edid2_present = raw_edid && raw_edid_size;
1839

1840
	if (edid1_present != edid2_present)
1841
		return false;
1842

1843
	if (edid1_present) {
1844
		if (drm_edid->size != raw_edid_size)
1845
			return false;
1846

1847
		if (memcmp(drm_edid->edid, raw_edid, drm_edid->size))
1848
			return false;
1849
	}
1850

1851
	return true;
1852
}
1853

1854
enum edid_block_status {
1855
	EDID_BLOCK_OK = 0,
1856
	EDID_BLOCK_READ_FAIL,
1857
	EDID_BLOCK_NULL,
1858
	EDID_BLOCK_ZERO,
1859
	EDID_BLOCK_HEADER_CORRUPT,
1860
	EDID_BLOCK_HEADER_REPAIR,
1861
	EDID_BLOCK_HEADER_FIXED,
1862
	EDID_BLOCK_CHECKSUM,
1863
	EDID_BLOCK_VERSION,
1864
};
1865

1866
static enum edid_block_status edid_block_check(const void *_block,
1867
					       bool is_base_block)
1868
{
1869
	const struct edid *block = _block;
1870

1871
	if (!block)
1872
		return EDID_BLOCK_NULL;
1873

1874
	if (is_base_block) {
1875
		int score = drm_edid_header_is_valid(block);
1876

1877
		if (score < clamp(edid_fixup, 0, 8)) {
1878
			if (edid_block_is_zero(block))
1879
				return EDID_BLOCK_ZERO;
1880
			else
1881
				return EDID_BLOCK_HEADER_CORRUPT;
1882
		}
1883

1884
		if (score < 8)
1885
			return EDID_BLOCK_HEADER_REPAIR;
1886
	}
1887

1888
	if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1889
		if (edid_block_is_zero(block))
1890
			return EDID_BLOCK_ZERO;
1891
		else
1892
			return EDID_BLOCK_CHECKSUM;
1893
	}
1894

1895
	if (is_base_block) {
1896
		if (block->version != 1)
1897
			return EDID_BLOCK_VERSION;
1898
	}
1899

1900
	return EDID_BLOCK_OK;
1901
}
1902

1903
static bool edid_block_status_valid(enum edid_block_status status, int tag)
1904
{
1905
	return status == EDID_BLOCK_OK ||
1906
		status == EDID_BLOCK_HEADER_FIXED ||
1907
		(status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1908
}
1909

1910
static bool edid_block_valid(const void *block, bool base)
1911
{
1912
	return edid_block_status_valid(edid_block_check(block, base),
1913
				       edid_block_tag(block));
1914
}
1915

1916
static void edid_block_status_print(enum edid_block_status status,
1917
				    const struct edid *block,
1918
				    int block_num)
1919
{
1920
	switch (status) {
1921
	case EDID_BLOCK_OK:
1922
		break;
1923
	case EDID_BLOCK_READ_FAIL:
1924
		pr_debug("EDID block %d read failed\n", block_num);
1925
		break;
1926
	case EDID_BLOCK_NULL:
1927
		pr_debug("EDID block %d pointer is NULL\n", block_num);
1928
		break;
1929
	case EDID_BLOCK_ZERO:
1930
		pr_notice("EDID block %d is all zeroes\n", block_num);
1931
		break;
1932
	case EDID_BLOCK_HEADER_CORRUPT:
1933
		pr_notice("EDID has corrupt header\n");
1934
		break;
1935
	case EDID_BLOCK_HEADER_REPAIR:
1936
		pr_debug("EDID corrupt header needs repair\n");
1937
		break;
1938
	case EDID_BLOCK_HEADER_FIXED:
1939
		pr_debug("EDID corrupt header fixed\n");
1940
		break;
1941
	case EDID_BLOCK_CHECKSUM:
1942
		if (edid_block_status_valid(status, edid_block_tag(block))) {
1943
			pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1944
				 block_num, edid_block_tag(block),
1945
				 edid_block_compute_checksum(block));
1946
		} else {
1947
			pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1948
				  block_num, edid_block_tag(block),
1949
				  edid_block_compute_checksum(block));
1950
		}
1951
		break;
1952
	case EDID_BLOCK_VERSION:
1953
		pr_notice("EDID has major version %d, instead of 1\n",
1954
			  block->version);
1955
		break;
1956
	default:
1957
		WARN(1, "EDID block %d unknown edid block status code %d\n",
1958
		     block_num, status);
1959
		break;
1960
	}
1961
}
1962

1963
static void edid_block_dump(const char *level, const void *block, int block_num)
1964
{
1965
	enum edid_block_status status;
1966
	char prefix[20];
1967

1968
	status = edid_block_check(block, block_num == 0);
1969
	if (status == EDID_BLOCK_ZERO)
1970
		sprintf(prefix, "\t[%02x] ZERO ", block_num);
1971
	else if (!edid_block_status_valid(status, edid_block_tag(block)))
1972
		sprintf(prefix, "\t[%02x] BAD  ", block_num);
1973
	else
1974
		sprintf(prefix, "\t[%02x] GOOD ", block_num);
1975

1976
	print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1977
		       block, EDID_LENGTH, false);
1978
}
1979

1980
/*
1981
 * Validate a base or extension EDID block and optionally dump bad blocks to
1982
 * the console.
1983
 */
1984
static bool drm_edid_block_valid(void *_block, int block_num, bool print_bad_edid,
1985
				 bool *edid_corrupt)
1986
{
1987
	struct edid *block = _block;
1988
	enum edid_block_status status;
1989
	bool is_base_block = block_num == 0;
1990
	bool valid;
1991

1992
	if (WARN_ON(!block))
1993
		return false;
1994

1995
	status = edid_block_check(block, is_base_block);
1996
	if (status == EDID_BLOCK_HEADER_REPAIR) {
1997
		DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n");
1998
		edid_header_fix(block);
1999

2000
		/* Retry with fixed header, update status if that worked. */
2001
		status = edid_block_check(block, is_base_block);
2002
		if (status == EDID_BLOCK_OK)
2003
			status = EDID_BLOCK_HEADER_FIXED;
2004
	}
2005

2006
	if (edid_corrupt) {
2007
		/*
2008
		 * Unknown major version isn't corrupt but we can't use it. Only
2009
		 * the base block can reset edid_corrupt to false.
2010
		 */
2011
		if (is_base_block &&
2012
		    (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
2013
			*edid_corrupt = false;
2014
		else if (status != EDID_BLOCK_OK)
2015
			*edid_corrupt = true;
2016
	}
2017

2018
	edid_block_status_print(status, block, block_num);
2019

2020
	/* Determine whether we can use this block with this status. */
2021
	valid = edid_block_status_valid(status, edid_block_tag(block));
2022

2023
	if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2024
		pr_notice("Raw EDID:\n");
2025
		edid_block_dump(KERN_NOTICE, block, block_num);
2026
	}
2027

2028
	return valid;
2029
}
2030

2031
/**
2032
 * drm_edid_is_valid - sanity check EDID data
2033
 * @edid: EDID data
2034
 *
2035
 * Sanity-check an entire EDID record (including extensions)
2036
 *
2037
 * Return: True if the EDID data is valid, false otherwise.
2038
 */
2039
bool drm_edid_is_valid(struct edid *edid)
2040
{
2041
	int i;
2042

2043
	if (!edid)
2044
		return false;
2045

2046
	for (i = 0; i < edid_block_count(edid); i++) {
2047
		void *block = (void *)edid_block_data(edid, i);
2048

2049
		if (!drm_edid_block_valid(block, i, true, NULL))
2050
			return false;
2051
	}
2052

2053
	return true;
2054
}
2055
EXPORT_SYMBOL(drm_edid_is_valid);
2056

2057
/**
2058
 * drm_edid_valid - sanity check EDID data
2059
 * @drm_edid: EDID data
2060
 *
2061
 * Sanity check an EDID. Cross check block count against allocated size and
2062
 * checksum the blocks.
2063
 *
2064
 * Return: True if the EDID data is valid, false otherwise.
2065
 */
2066
bool drm_edid_valid(const struct drm_edid *drm_edid)
2067
{
2068
	int i;
2069

2070
	if (!drm_edid)
2071
		return false;
2072

2073
	if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size)
2074
		return false;
2075

2076
	for (i = 0; i < drm_edid_block_count(drm_edid); i++) {
2077
		const void *block = drm_edid_block_data(drm_edid, i);
2078

2079
		if (!edid_block_valid(block, i == 0))
2080
			return false;
2081
	}
2082

2083
	return true;
2084
}
2085
EXPORT_SYMBOL(drm_edid_valid);
2086

2087
static struct edid *edid_filter_invalid_blocks(struct edid *edid,
2088
					       size_t *alloc_size)
2089
{
2090
	struct edid *new;
2091
	int i, valid_blocks = 0;
2092

2093
	/*
2094
	 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2095
	 * back to regular extension count here. We don't want to start
2096
	 * modifying the HF-EEODB extension too.
2097
	 */
2098
	for (i = 0; i < edid_block_count(edid); i++) {
2099
		const void *src_block = edid_block_data(edid, i);
2100

2101
		if (edid_block_valid(src_block, i == 0)) {
2102
			void *dst_block = (void *)edid_block_data(edid, valid_blocks);
2103

2104
			memmove(dst_block, src_block, EDID_LENGTH);
2105
			valid_blocks++;
2106
		}
2107
	}
2108

2109
	/* We already trusted the base block to be valid here... */
2110
	if (WARN_ON(!valid_blocks)) {
2111
		kfree(edid);
2112
		return NULL;
2113
	}
2114

2115
	edid->extensions = valid_blocks - 1;
2116
	edid->checksum = edid_block_compute_checksum(edid);
2117

2118
	*alloc_size = edid_size_by_blocks(valid_blocks);
2119

2120
	new = krealloc(edid, *alloc_size, GFP_KERNEL);
2121
	if (!new)
2122
		kfree(edid);
2123

2124
	return new;
2125
}
2126

2127
#define DDC_SEGMENT_ADDR 0x30
2128
/**
2129
 * drm_do_probe_ddc_edid() - get EDID information via I2C
2130
 * @data: I2C device adapter
2131
 * @buf: EDID data buffer to be filled
2132
 * @block: 128 byte EDID block to start fetching from
2133
 * @len: EDID data buffer length to fetch
2134
 *
2135
 * Try to fetch EDID information by calling I2C driver functions.
2136
 *
2137
 * Return: 0 on success or -1 on failure.
2138
 */
2139
static int
2140
drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
2141
{
2142
	struct i2c_adapter *adapter = data;
2143
	unsigned char start = block * EDID_LENGTH;
2144
	unsigned char segment = block >> 1;
2145
	unsigned char xfers = segment ? 3 : 2;
2146
	int ret, retries = 5;
2147

2148
	/*
2149
	 * The core I2C driver will automatically retry the transfer if the
2150
	 * adapter reports EAGAIN. However, we find that bit-banging transfers
2151
	 * are susceptible to errors under a heavily loaded machine and
2152
	 * generate spurious NAKs and timeouts. Retrying the transfer
2153
	 * of the individual block a few times seems to overcome this.
2154
	 */
2155
	do {
2156
		struct i2c_msg msgs[] = {
2157
			{
2158
				.addr	= DDC_SEGMENT_ADDR,
2159
				.flags	= 0,
2160
				.len	= 1,
2161
				.buf	= &segment,
2162
			}, {
2163
				.addr	= DDC_ADDR,
2164
				.flags	= 0,
2165
				.len	= 1,
2166
				.buf	= &start,
2167
			}, {
2168
				.addr	= DDC_ADDR,
2169
				.flags	= I2C_M_RD,
2170
				.len	= len,
2171
				.buf	= buf,
2172
			}
2173
		};
2174

2175
		/*
2176
		 * Avoid sending the segment addr to not upset non-compliant
2177
		 * DDC monitors.
2178
		 */
2179
		ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2180

2181
		if (ret == -ENXIO) {
2182
			DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2183
					adapter->name);
2184
			break;
2185
		}
2186
	} while (ret != xfers && --retries);
2187

2188
	return ret == xfers ? 0 : -1;
2189
}
2190

2191
static void connector_bad_edid(struct drm_connector *connector,
2192
			       const struct edid *edid, int num_blocks)
2193
{
2194
	int i;
2195
	u8 last_block;
2196

2197
	/*
2198
	 * 0x7e in the EDID is the number of extension blocks. The EDID
2199
	 * is 1 (base block) + num_ext_blocks big. That means we can think
2200
	 * of 0x7e in the EDID of the _index_ of the last block in the
2201
	 * combined chunk of memory.
2202
	 */
2203
	last_block = edid->extensions;
2204

2205
	/* Calculate real checksum for the last edid extension block data */
2206
	if (last_block < num_blocks)
2207
		connector->real_edid_checksum =
2208
			edid_block_compute_checksum(edid + last_block);
2209

2210
	if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
2211
		return;
2212

2213
	drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n",
2214
		    connector->base.id, connector->name);
2215
	for (i = 0; i < num_blocks; i++)
2216
		edid_block_dump(KERN_DEBUG, edid + i, i);
2217
}
2218

2219
/* Get override or firmware EDID */
2220
static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector)
2221
{
2222
	const struct drm_edid *override = NULL;
2223

2224
	mutex_lock(&connector->edid_override_mutex);
2225

2226
	if (connector->edid_override)
2227
		override = drm_edid_dup(connector->edid_override);
2228

2229
	mutex_unlock(&connector->edid_override_mutex);
2230

2231
	if (!override)
2232
		override = drm_edid_load_firmware(connector);
2233

2234
	return IS_ERR(override) ? NULL : override;
2235
}
2236

2237
/* For debugfs edid_override implementation */
2238
int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m)
2239
{
2240
	const struct drm_edid *drm_edid;
2241

2242
	mutex_lock(&connector->edid_override_mutex);
2243

2244
	drm_edid = connector->edid_override;
2245
	if (drm_edid)
2246
		seq_write(m, drm_edid->edid, drm_edid->size);
2247

2248
	mutex_unlock(&connector->edid_override_mutex);
2249

2250
	return 0;
2251
}
2252

2253
/* For debugfs edid_override implementation */
2254
int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2255
			  size_t size)
2256
{
2257
	const struct drm_edid *drm_edid;
2258

2259
	drm_edid = drm_edid_alloc(edid, size);
2260
	if (!drm_edid_valid(drm_edid)) {
2261
		drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n",
2262
			    connector->base.id, connector->name);
2263
		drm_edid_free(drm_edid);
2264
		return -EINVAL;
2265
	}
2266

2267
	drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n",
2268
		    connector->base.id, connector->name);
2269

2270
	mutex_lock(&connector->edid_override_mutex);
2271

2272
	drm_edid_free(connector->edid_override);
2273
	connector->edid_override = drm_edid;
2274

2275
	mutex_unlock(&connector->edid_override_mutex);
2276

2277
	return 0;
2278
}
2279

2280
/* For debugfs edid_override implementation */
2281
int drm_edid_override_reset(struct drm_connector *connector)
2282
{
2283
	drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n",
2284
		    connector->base.id, connector->name);
2285

2286
	mutex_lock(&connector->edid_override_mutex);
2287

2288
	drm_edid_free(connector->edid_override);
2289
	connector->edid_override = NULL;
2290

2291
	mutex_unlock(&connector->edid_override_mutex);
2292

2293
	return 0;
2294
}
2295

2296
/**
2297
 * drm_edid_override_connector_update - add modes from override/firmware EDID
2298
 * @connector: connector we're probing
2299
 *
2300
 * Add modes from the override/firmware EDID, if available. Only to be used from
2301
 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2302
 * failed during drm_get_edid() and caused the override/firmware EDID to be
2303
 * skipped.
2304
 *
2305
 * Return: The number of modes added or 0 if we couldn't find any.
2306
 */
2307
int drm_edid_override_connector_update(struct drm_connector *connector)
2308
{
2309
	const struct drm_edid *override;
2310
	int num_modes = 0;
2311

2312
	override = drm_edid_override_get(connector);
2313
	if (override) {
2314
		if (drm_edid_connector_update(connector, override) == 0)
2315
			num_modes = drm_edid_connector_add_modes(connector);
2316

2317
		drm_edid_free(override);
2318

2319
		drm_dbg_kms(connector->dev,
2320
			    "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2321
			    connector->base.id, connector->name, num_modes);
2322
	}
2323

2324
	return num_modes;
2325
}
2326
EXPORT_SYMBOL(drm_edid_override_connector_update);
2327

2328
typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2329

2330
static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2331
					      read_block_fn read_block,
2332
					      void *context)
2333
{
2334
	enum edid_block_status status;
2335
	bool is_base_block = block_num == 0;
2336
	int try;
2337

2338
	for (try = 0; try < 4; try++) {
2339
		if (read_block(context, block, block_num, EDID_LENGTH))
2340
			return EDID_BLOCK_READ_FAIL;
2341

2342
		status = edid_block_check(block, is_base_block);
2343
		if (status == EDID_BLOCK_HEADER_REPAIR) {
2344
			edid_header_fix(block);
2345

2346
			/* Retry with fixed header, update status if that worked. */
2347
			status = edid_block_check(block, is_base_block);
2348
			if (status == EDID_BLOCK_OK)
2349
				status = EDID_BLOCK_HEADER_FIXED;
2350
		}
2351

2352
		if (edid_block_status_valid(status, edid_block_tag(block)))
2353
			break;
2354

2355
		/* Fail early for unrepairable base block all zeros. */
2356
		if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2357
			break;
2358
	}
2359

2360
	return status;
2361
}
2362

2363
static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2364
				     read_block_fn read_block, void *context,
2365
				     size_t *size)
2366
{
2367
	enum edid_block_status status;
2368
	int i, num_blocks, invalid_blocks = 0;
2369
	const struct drm_edid *override;
2370
	struct edid *edid, *new;
2371
	size_t alloc_size = EDID_LENGTH;
2372

2373
	override = drm_edid_override_get(connector);
2374
	if (override) {
2375
		alloc_size = override->size;
2376
		edid = kmemdup(override->edid, alloc_size, GFP_KERNEL);
2377
		drm_edid_free(override);
2378
		if (!edid)
2379
			return NULL;
2380
		goto ok;
2381
	}
2382

2383
	edid = kmalloc(alloc_size, GFP_KERNEL);
2384
	if (!edid)
2385
		return NULL;
2386

2387
	status = edid_block_read(edid, 0, read_block, context);
2388

2389
	edid_block_status_print(status, edid, 0);
2390

2391
	if (status == EDID_BLOCK_READ_FAIL)
2392
		goto fail;
2393

2394
	/* FIXME: Clarify what a corrupt EDID actually means. */
2395
	if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2396
		connector->edid_corrupt = false;
2397
	else
2398
		connector->edid_corrupt = true;
2399

2400
	if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2401
		if (status == EDID_BLOCK_ZERO)
2402
			connector->null_edid_counter++;
2403

2404
		connector_bad_edid(connector, edid, 1);
2405
		goto fail;
2406
	}
2407

2408
	if (!edid_extension_block_count(edid))
2409
		goto ok;
2410

2411
	alloc_size = edid_size(edid);
2412
	new = krealloc(edid, alloc_size, GFP_KERNEL);
2413
	if (!new)
2414
		goto fail;
2415
	edid = new;
2416

2417
	num_blocks = edid_block_count(edid);
2418
	for (i = 1; i < num_blocks; i++) {
2419
		void *block = (void *)edid_block_data(edid, i);
2420

2421
		status = edid_block_read(block, i, read_block, context);
2422

2423
		edid_block_status_print(status, block, i);
2424

2425
		if (!edid_block_status_valid(status, edid_block_tag(block))) {
2426
			if (status == EDID_BLOCK_READ_FAIL)
2427
				goto fail;
2428
			invalid_blocks++;
2429
		} else if (i == 1) {
2430
			/*
2431
			 * If the first EDID extension is a CTA extension, and
2432
			 * the first Data Block is HF-EEODB, override the
2433
			 * extension block count.
2434
			 *
2435
			 * Note: HF-EEODB could specify a smaller extension
2436
			 * count too, but we can't risk allocating a smaller
2437
			 * amount.
2438
			 */
2439
			int eeodb = edid_hfeeodb_block_count(edid);
2440

2441
			if (eeodb > num_blocks) {
2442
				num_blocks = eeodb;
2443
				alloc_size = edid_size_by_blocks(num_blocks);
2444
				new = krealloc(edid, alloc_size, GFP_KERNEL);
2445
				if (!new)
2446
					goto fail;
2447
				edid = new;
2448
			}
2449
		}
2450
	}
2451

2452
	if (invalid_blocks) {
2453
		connector_bad_edid(connector, edid, num_blocks);
2454

2455
		edid = edid_filter_invalid_blocks(edid, &alloc_size);
2456
	}
2457

2458
ok:
2459
	if (size)
2460
		*size = alloc_size;
2461

2462
	return edid;
2463

2464
fail:
2465
	kfree(edid);
2466
	return NULL;
2467
}
2468

2469
/**
2470
 * drm_edid_raw - Get a pointer to the raw EDID data.
2471
 * @drm_edid: drm_edid container
2472
 *
2473
 * Get a pointer to the raw EDID data.
2474
 *
2475
 * This is for transition only. Avoid using this like the plague.
2476
 *
2477
 * Return: Pointer to raw EDID data.
2478
 */
2479
const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2480
{
2481
	if (!drm_edid || !drm_edid->size)
2482
		return NULL;
2483

2484
	/*
2485
	 * Do not return pointers where relying on EDID extension count would
2486
	 * lead to buffer overflow.
2487
	 */
2488
	if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2489
		return NULL;
2490

2491
	return drm_edid->edid;
2492
}
2493
EXPORT_SYMBOL(drm_edid_raw);
2494

2495
/* Allocate struct drm_edid container *without* duplicating the edid data */
2496
static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2497
{
2498
	struct drm_edid *drm_edid;
2499

2500
	if (!edid || !size || size < EDID_LENGTH)
2501
		return NULL;
2502

2503
	drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2504
	if (drm_edid) {
2505
		drm_edid->edid = edid;
2506
		drm_edid->size = size;
2507
	}
2508

2509
	return drm_edid;
2510
}
2511

2512
/**
2513
 * drm_edid_alloc - Allocate a new drm_edid container
2514
 * @edid: Pointer to raw EDID data
2515
 * @size: Size of memory allocated for EDID
2516
 *
2517
 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2518
 * the actual size that has been allocated for the data. There is no validation
2519
 * of the raw EDID data against the size, but at least the EDID base block must
2520
 * fit in the buffer.
2521
 *
2522
 * The returned pointer must be freed using drm_edid_free().
2523
 *
2524
 * Return: drm_edid container, or NULL on errors
2525
 */
2526
const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2527
{
2528
	const struct drm_edid *drm_edid;
2529

2530
	if (!edid || !size || size < EDID_LENGTH)
2531
		return NULL;
2532

2533
	edid = kmemdup(edid, size, GFP_KERNEL);
2534
	if (!edid)
2535
		return NULL;
2536

2537
	drm_edid = _drm_edid_alloc(edid, size);
2538
	if (!drm_edid)
2539
		kfree(edid);
2540

2541
	return drm_edid;
2542
}
2543
EXPORT_SYMBOL(drm_edid_alloc);
2544

2545
/**
2546
 * drm_edid_dup - Duplicate a drm_edid container
2547
 * @drm_edid: EDID to duplicate
2548
 *
2549
 * The returned pointer must be freed using drm_edid_free().
2550
 *
2551
 * Returns: drm_edid container copy, or NULL on errors
2552
 */
2553
const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2554
{
2555
	if (!drm_edid)
2556
		return NULL;
2557

2558
	return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2559
}
2560
EXPORT_SYMBOL(drm_edid_dup);
2561

2562
/**
2563
 * drm_edid_free - Free the drm_edid container
2564
 * @drm_edid: EDID to free
2565
 */
2566
void drm_edid_free(const struct drm_edid *drm_edid)
2567
{
2568
	if (!drm_edid)
2569
		return;
2570

2571
	kfree(drm_edid->edid);
2572
	kfree(drm_edid);
2573
}
2574
EXPORT_SYMBOL(drm_edid_free);
2575

2576
/**
2577
 * drm_probe_ddc() - probe DDC presence
2578
 * @adapter: I2C adapter to probe
2579
 *
2580
 * Return: True on success, false on failure.
2581
 */
2582
bool
2583
drm_probe_ddc(struct i2c_adapter *adapter)
2584
{
2585
	unsigned char out;
2586

2587
	return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2588
}
2589
EXPORT_SYMBOL(drm_probe_ddc);
2590

2591
/**
2592
 * drm_get_edid - get EDID data, if available
2593
 * @connector: connector we're probing
2594
 * @adapter: I2C adapter to use for DDC
2595
 *
2596
 * Poke the given I2C channel to grab EDID data if possible.  If found,
2597
 * attach it to the connector.
2598
 *
2599
 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2600
 */
2601
struct edid *drm_get_edid(struct drm_connector *connector,
2602
			  struct i2c_adapter *adapter)
2603
{
2604
	struct edid *edid;
2605

2606
	if (connector->force == DRM_FORCE_OFF)
2607
		return NULL;
2608

2609
	if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2610
		return NULL;
2611

2612
	edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
2613
	drm_connector_update_edid_property(connector, edid);
2614
	return edid;
2615
}
2616
EXPORT_SYMBOL(drm_get_edid);
2617

2618
/**
2619
 * drm_edid_read_custom - Read EDID data using given EDID block read function
2620
 * @connector: Connector to use
2621
 * @read_block: EDID block read function
2622
 * @context: Private data passed to the block read function
2623
 *
2624
 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2625
 * exposes a different interface to read EDID blocks this function can be used
2626
 * to get EDID data using a custom block read function.
2627
 *
2628
 * As in the general case the DDC bus is accessible by the kernel at the I2C
2629
 * level, drivers must make all reasonable efforts to expose it as an I2C
2630
 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2631
 * this function.
2632
 *
2633
 * The EDID may be overridden using debugfs override_edid or firmware EDID
2634
 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2635
 * order. Having either of them bypasses actual EDID reads.
2636
 *
2637
 * The returned pointer must be freed using drm_edid_free().
2638
 *
2639
 * Return: Pointer to EDID, or NULL if probe/read failed.
2640
 */
2641
const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2642
					    read_block_fn read_block,
2643
					    void *context)
2644
{
2645
	const struct drm_edid *drm_edid;
2646
	struct edid *edid;
2647
	size_t size = 0;
2648

2649
	edid = _drm_do_get_edid(connector, read_block, context, &size);
2650
	if (!edid)
2651
		return NULL;
2652

2653
	/* Sanity check for now */
2654
	drm_WARN_ON(connector->dev, !size);
2655

2656
	drm_edid = _drm_edid_alloc(edid, size);
2657
	if (!drm_edid)
2658
		kfree(edid);
2659

2660
	return drm_edid;
2661
}
2662
EXPORT_SYMBOL(drm_edid_read_custom);
2663

2664
/**
2665
 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2666
 * @connector: Connector to use
2667
 * @adapter: I2C adapter to use for DDC
2668
 *
2669
 * Read EDID using the given I2C adapter.
2670
 *
2671
 * The EDID may be overridden using debugfs override_edid or firmware EDID
2672
 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2673
 * order. Having either of them bypasses actual EDID reads.
2674
 *
2675
 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2676
 * using drm_edid_read() instead of this function.
2677
 *
2678
 * The returned pointer must be freed using drm_edid_free().
2679
 *
2680
 * Return: Pointer to EDID, or NULL if probe/read failed.
2681
 */
2682
const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2683
					 struct i2c_adapter *adapter)
2684
{
2685
	const struct drm_edid *drm_edid;
2686

2687
	if (connector->force == DRM_FORCE_OFF)
2688
		return NULL;
2689

2690
	if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2691
		return NULL;
2692

2693
	drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2694

2695
	/* Note: Do *not* call connector updates here. */
2696

2697
	return drm_edid;
2698
}
2699
EXPORT_SYMBOL(drm_edid_read_ddc);
2700

2701
/**
2702
 * drm_edid_read - Read EDID data using connector's I2C adapter
2703
 * @connector: Connector to use
2704
 *
2705
 * Read EDID using the connector's I2C adapter.
2706
 *
2707
 * The EDID may be overridden using debugfs override_edid or firmware EDID
2708
 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2709
 * order. Having either of them bypasses actual EDID reads.
2710
 *
2711
 * The returned pointer must be freed using drm_edid_free().
2712
 *
2713
 * Return: Pointer to EDID, or NULL if probe/read failed.
2714
 */
2715
const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2716
{
2717
	if (drm_WARN_ON(connector->dev, !connector->ddc))
2718
		return NULL;
2719

2720
	return drm_edid_read_ddc(connector, connector->ddc);
2721
}
2722
EXPORT_SYMBOL(drm_edid_read);
2723

2724
/**
2725
 * drm_edid_get_product_id - Get the vendor and product identification
2726
 * @drm_edid: EDID
2727
 * @id: Where to place the product id
2728
 */
2729
void drm_edid_get_product_id(const struct drm_edid *drm_edid,
2730
			     struct drm_edid_product_id *id)
2731
{
2732
	if (drm_edid && drm_edid->edid && drm_edid->size >= EDID_LENGTH)
2733
		memcpy(id, &drm_edid->edid->product_id, sizeof(*id));
2734
	else
2735
		memset(id, 0, sizeof(*id));
2736
}
2737
EXPORT_SYMBOL(drm_edid_get_product_id);
2738

2739
static void decode_date(struct seq_buf *s, const struct drm_edid_product_id *id)
2740
{
2741
	int week = id->week_of_manufacture;
2742
	int year = id->year_of_manufacture + 1990;
2743

2744
	if (week == 0xff)
2745
		seq_buf_printf(s, "model year: %d", year);
2746
	else if (!week)
2747
		seq_buf_printf(s, "year of manufacture: %d", year);
2748
	else
2749
		seq_buf_printf(s, "week/year of manufacture: %d/%d", week, year);
2750
}
2751

2752
/**
2753
 * drm_edid_print_product_id - Print decoded product id to printer
2754
 * @p: drm printer
2755
 * @id: EDID product id
2756
 * @raw: If true, also print the raw hex
2757
 *
2758
 * See VESA E-EDID 1.4 section 3.4.
2759
 */
2760
void drm_edid_print_product_id(struct drm_printer *p,
2761
			       const struct drm_edid_product_id *id, bool raw)
2762
{
2763
	DECLARE_SEQ_BUF(date, 40);
2764
	char vend[4];
2765

2766
	drm_edid_decode_mfg_id(be16_to_cpu(id->manufacturer_name), vend);
2767

2768
	decode_date(&date, id);
2769

2770
	drm_printf(p, "manufacturer name: %s, product code: %u, serial number: %u, %s\n",
2771
		   vend, le16_to_cpu(id->product_code),
2772
		   le32_to_cpu(id->serial_number), seq_buf_str(&date));
2773

2774
	if (raw)
2775
		drm_printf(p, "raw product id: %*ph\n", (int)sizeof(*id), id);
2776

2777
	WARN_ON(seq_buf_has_overflowed(&date));
2778
}
2779
EXPORT_SYMBOL(drm_edid_print_product_id);
2780

2781
/**
2782
 * drm_edid_get_panel_id - Get a panel's ID from EDID
2783
 * @drm_edid: EDID that contains panel ID.
2784
 *
2785
 * This function uses the first block of the EDID of a panel and (assuming
2786
 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2787
 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2788
 * supposed to be different for each different modem of panel.
2789
 *
2790
 * Return: A 32-bit ID that should be different for each make/model of panel.
2791
 *         See the functions drm_edid_encode_panel_id() and
2792
 *         drm_edid_decode_panel_id() for some details on the structure of this
2793
 *         ID. Return 0 if the EDID size is less than a base block.
2794
 */
2795
u32 drm_edid_get_panel_id(const struct drm_edid *drm_edid)
2796
{
2797
	const struct edid *edid = drm_edid->edid;
2798

2799
	if (drm_edid->size < EDID_LENGTH)
2800
		return 0;
2801

2802
	/*
2803
	 * We represent the ID as a 32-bit number so it can easily be compared
2804
	 * with "==".
2805
	 *
2806
	 * NOTE that we deal with endianness differently for the top half
2807
	 * of this ID than for the bottom half. The bottom half (the product
2808
	 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2809
	 * that's how everyone seems to interpret it. The top half (the mfg_id)
2810
	 * gets stored as big endian because that makes
2811
	 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2812
	 * to write (it's easier to extract the ASCII). It doesn't really
2813
	 * matter, though, as long as the number here is unique.
2814
	 */
2815
	return (u32)edid->mfg_id[0] << 24   |
2816
	       (u32)edid->mfg_id[1] << 16   |
2817
	       (u32)EDID_PRODUCT_ID(edid);
2818
}
2819
EXPORT_SYMBOL(drm_edid_get_panel_id);
2820

2821
/**
2822
 * drm_edid_read_base_block - Get a panel's EDID base block
2823
 * @adapter: I2C adapter to use for DDC
2824
 *
2825
 * This function returns the drm_edid containing the first block of the EDID of
2826
 * a panel.
2827
 *
2828
 * This function is intended to be used during early probing on devices where
2829
 * more than one panel might be present. Because of its intended use it must
2830
 * assume that the EDID of the panel is correct, at least as far as the base
2831
 * block is concerned (in other words, we don't process any overrides here).
2832
 *
2833
 * Caller should call drm_edid_free() after use.
2834
 *
2835
 * NOTE: it's expected that this function and drm_do_get_edid() will both
2836
 * be read the EDID, but there is no caching between them. Since we're only
2837
 * reading the first block, hopefully this extra overhead won't be too big.
2838
 *
2839
 * WARNING: Only use this function when the connector is unknown. For example,
2840
 * during the early probe of panel. The EDID read from the function is temporary
2841
 * and should be replaced by the full EDID returned from other drm_edid_read.
2842
 *
2843
 * Return: Pointer to allocated EDID base block, or NULL on any failure.
2844
 */
2845
const struct drm_edid *drm_edid_read_base_block(struct i2c_adapter *adapter)
2846
{
2847
	enum edid_block_status status;
2848
	void *base_block;
2849

2850
	base_block = kzalloc(EDID_LENGTH, GFP_KERNEL);
2851
	if (!base_block)
2852
		return NULL;
2853

2854
	status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2855

2856
	edid_block_status_print(status, base_block, 0);
2857

2858
	if (!edid_block_status_valid(status, edid_block_tag(base_block))) {
2859
		edid_block_dump(KERN_NOTICE, base_block, 0);
2860
		kfree(base_block);
2861
		return NULL;
2862
	}
2863

2864
	return _drm_edid_alloc(base_block, EDID_LENGTH);
2865
}
2866
EXPORT_SYMBOL(drm_edid_read_base_block);
2867

2868
/**
2869
 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2870
 * @connector: connector we're probing
2871
 * @adapter: I2C adapter to use for DDC
2872
 *
2873
 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2874
 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2875
 * switch DDC to the GPU which is retrieving EDID.
2876
 *
2877
 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2878
 */
2879
struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2880
				     struct i2c_adapter *adapter)
2881
{
2882
	struct drm_device *dev = connector->dev;
2883
	struct pci_dev *pdev = to_pci_dev(dev->dev);
2884
	struct edid *edid;
2885

2886
	if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2887
		return NULL;
2888

2889
	vga_switcheroo_lock_ddc(pdev);
2890
	edid = drm_get_edid(connector, adapter);
2891
	vga_switcheroo_unlock_ddc(pdev);
2892

2893
	return edid;
2894
}
2895
EXPORT_SYMBOL(drm_get_edid_switcheroo);
2896

2897
/**
2898
 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output
2899
 * @connector: connector we're probing
2900
 * @adapter: I2C adapter to use for DDC
2901
 *
2902
 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set
2903
 * of outputs. The wrapper adds the requisite vga_switcheroo calls to
2904
 * temporarily switch DDC to the GPU which is retrieving EDID.
2905
 *
2906
 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2907
 */
2908
const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector,
2909
						struct i2c_adapter *adapter)
2910
{
2911
	struct drm_device *dev = connector->dev;
2912
	struct pci_dev *pdev = to_pci_dev(dev->dev);
2913
	const struct drm_edid *drm_edid;
2914

2915
	if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2916
		return NULL;
2917

2918
	vga_switcheroo_lock_ddc(pdev);
2919
	drm_edid = drm_edid_read_ddc(connector, adapter);
2920
	vga_switcheroo_unlock_ddc(pdev);
2921

2922
	return drm_edid;
2923
}
2924
EXPORT_SYMBOL(drm_edid_read_switcheroo);
2925

2926
/**
2927
 * drm_edid_duplicate - duplicate an EDID and the extensions
2928
 * @edid: EDID to duplicate
2929
 *
2930
 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2931
 */
2932
struct edid *drm_edid_duplicate(const struct edid *edid)
2933
{
2934
	if (!edid)
2935
		return NULL;
2936

2937
	return kmemdup(edid, edid_size(edid), GFP_KERNEL);
2938
}
2939
EXPORT_SYMBOL(drm_edid_duplicate);
2940

2941
/*** EDID parsing ***/
2942

2943
/**
2944
 * edid_get_quirks - return quirk flags for a given EDID
2945
 * @drm_edid: EDID to process
2946
 *
2947
 * This tells subsequent routines what fixes they need to apply.
2948
 *
2949
 * Return: A u32 represents the quirks to apply.
2950
 */
2951
static u32 edid_get_quirks(const struct drm_edid *drm_edid)
2952
{
2953
	const struct edid_quirk *quirk;
2954
	int i;
2955

2956
	for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2957
		quirk = &edid_quirk_list[i];
2958
		if (drm_edid_match(drm_edid, &quirk->ident))
2959
			return quirk->quirks;
2960
	}
2961

2962
	return 0;
2963
}
2964

2965
static bool drm_edid_has_internal_quirk(struct drm_connector *connector,
2966
					enum drm_edid_internal_quirk quirk)
2967
{
2968
	return connector->display_info.quirks & BIT(quirk);
2969
}
2970

2971
bool drm_edid_has_quirk(struct drm_connector *connector, enum drm_edid_quirk quirk)
2972
{
2973
	return connector->display_info.quirks & BIT(quirk);
2974
}
2975
EXPORT_SYMBOL(drm_edid_has_quirk);
2976

2977
#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2978
#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2979

2980
/*
2981
 * Walk the mode list for connector, clearing the preferred status on existing
2982
 * modes and setting it anew for the right mode ala quirks.
2983
 */
2984
static void edid_fixup_preferred(struct drm_connector *connector)
2985
{
2986
	struct drm_display_mode *t, *cur_mode, *preferred_mode;
2987
	int target_refresh = 0;
2988
	int cur_vrefresh, preferred_vrefresh;
2989

2990
	if (list_empty(&connector->probed_modes))
2991
		return;
2992

2993
	if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_PREFER_LARGE_60))
2994
		target_refresh = 60;
2995
	if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_PREFER_LARGE_75))
2996
		target_refresh = 75;
2997

2998
	preferred_mode = list_first_entry(&connector->probed_modes,
2999
					  struct drm_display_mode, head);
3000

3001
	list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
3002
		cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3003

3004
		if (cur_mode == preferred_mode)
3005
			continue;
3006

3007
		/* Largest mode is preferred */
3008
		if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
3009
			preferred_mode = cur_mode;
3010

3011
		cur_vrefresh = drm_mode_vrefresh(cur_mode);
3012
		preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
3013
		/* At a given size, try to get closest to target refresh */
3014
		if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
3015
		    MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
3016
		    MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
3017
			preferred_mode = cur_mode;
3018
		}
3019
	}
3020

3021
	preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
3022
}
3023

3024
static bool
3025
mode_is_rb(const struct drm_display_mode *mode)
3026
{
3027
	return (mode->htotal - mode->hdisplay == 160) &&
3028
	       (mode->hsync_end - mode->hdisplay == 80) &&
3029
	       (mode->hsync_end - mode->hsync_start == 32) &&
3030
	       (mode->vsync_start - mode->vdisplay == 3);
3031
}
3032

3033
/*
3034
 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
3035
 * @dev: Device to duplicate against
3036
 * @hsize: Mode width
3037
 * @vsize: Mode height
3038
 * @fresh: Mode refresh rate
3039
 * @rb: Mode reduced-blanking-ness
3040
 *
3041
 * Walk the DMT mode list looking for a match for the given parameters.
3042
 *
3043
 * Return: A newly allocated copy of the mode, or NULL if not found.
3044
 */
3045
struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
3046
					   int hsize, int vsize, int fresh,
3047
					   bool rb)
3048
{
3049
	int i;
3050

3051
	for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3052
		const struct drm_display_mode *ptr = &drm_dmt_modes[i];
3053

3054
		if (hsize != ptr->hdisplay)
3055
			continue;
3056
		if (vsize != ptr->vdisplay)
3057
			continue;
3058
		if (fresh != drm_mode_vrefresh(ptr))
3059
			continue;
3060
		if (rb != mode_is_rb(ptr))
3061
			continue;
3062

3063
		return drm_mode_duplicate(dev, ptr);
3064
	}
3065

3066
	return NULL;
3067
}
3068
EXPORT_SYMBOL(drm_mode_find_dmt);
3069

3070
static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
3071
{
3072
	BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3073
	BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
3074
	BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
3075

3076
	return descriptor->pixel_clock == 0 &&
3077
		descriptor->data.other_data.pad1 == 0 &&
3078
		descriptor->data.other_data.type == type;
3079
}
3080

3081
static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
3082
{
3083
	BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3084

3085
	return descriptor->pixel_clock != 0;
3086
}
3087

3088
typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
3089

3090
static void
3091
cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3092
{
3093
	int i, n;
3094
	u8 d = ext[0x02];
3095
	const u8 *det_base = ext + d;
3096

3097
	if (d < 4 || d > 127)
3098
		return;
3099

3100
	n = (127 - d) / 18;
3101
	for (i = 0; i < n; i++)
3102
		cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3103
}
3104

3105
static void
3106
vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3107
{
3108
	unsigned int i, n = min((int)ext[0x02], 6);
3109
	const u8 *det_base = ext + 5;
3110

3111
	if (ext[0x01] != 1)
3112
		return; /* unknown version */
3113

3114
	for (i = 0; i < n; i++)
3115
		cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3116
}
3117

3118
static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
3119
					detailed_cb *cb, void *closure)
3120
{
3121
	struct drm_edid_iter edid_iter;
3122
	const u8 *ext;
3123
	int i;
3124

3125
	if (!drm_edid)
3126
		return;
3127

3128
	for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
3129
		cb(&drm_edid->edid->detailed_timings[i], closure);
3130

3131
	drm_edid_iter_begin(drm_edid, &edid_iter);
3132
	drm_edid_iter_for_each(ext, &edid_iter) {
3133
		switch (*ext) {
3134
		case CEA_EXT:
3135
			cea_for_each_detailed_block(ext, cb, closure);
3136
			break;
3137
		case VTB_EXT:
3138
			vtb_for_each_detailed_block(ext, cb, closure);
3139
			break;
3140
		default:
3141
			break;
3142
		}
3143
	}
3144
	drm_edid_iter_end(&edid_iter);
3145
}
3146

3147
static void
3148
is_rb(const struct detailed_timing *descriptor, void *data)
3149
{
3150
	bool *res = data;
3151

3152
	if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3153
		return;
3154

3155
	BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3156
	BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
3157

3158
	if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
3159
	    descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
3160
		*res = true;
3161
}
3162

3163
/* EDID 1.4 defines this explicitly.  For EDID 1.3, we guess, badly. */
3164
static bool
3165
drm_monitor_supports_rb(const struct drm_edid *drm_edid)
3166
{
3167
	if (drm_edid->edid->revision >= 4) {
3168
		bool ret = false;
3169

3170
		drm_for_each_detailed_block(drm_edid, is_rb, &ret);
3171
		return ret;
3172
	}
3173

3174
	return drm_edid_is_digital(drm_edid);
3175
}
3176

3177
static void
3178
find_gtf2(const struct detailed_timing *descriptor, void *data)
3179
{
3180
	const struct detailed_timing **res = data;
3181

3182
	if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3183
		return;
3184

3185
	BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3186

3187
	if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
3188
		*res = descriptor;
3189
}
3190

3191
/* Secondary GTF curve kicks in above some break frequency */
3192
static int
3193
drm_gtf2_hbreak(const struct drm_edid *drm_edid)
3194
{
3195
	const struct detailed_timing *descriptor = NULL;
3196

3197
	drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3198

3199
	BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3200

3201
	return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
3202
}
3203

3204
static int
3205
drm_gtf2_2c(const struct drm_edid *drm_edid)
3206
{
3207
	const struct detailed_timing *descriptor = NULL;
3208

3209
	drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3210

3211
	BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
3212

3213
	return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
3214
}
3215

3216
static int
3217
drm_gtf2_m(const struct drm_edid *drm_edid)
3218
{
3219
	const struct detailed_timing *descriptor = NULL;
3220

3221
	drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3222

3223
	BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3224

3225
	return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
3226
}
3227

3228
static int
3229
drm_gtf2_k(const struct drm_edid *drm_edid)
3230
{
3231
	const struct detailed_timing *descriptor = NULL;
3232

3233
	drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3234

3235
	BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3236

3237
	return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
3238
}
3239

3240
static int
3241
drm_gtf2_2j(const struct drm_edid *drm_edid)
3242
{
3243
	const struct detailed_timing *descriptor = NULL;
3244

3245
	drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3246

3247
	BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
3248

3249
	return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
3250
}
3251

3252
static void
3253
get_timing_level(const struct detailed_timing *descriptor, void *data)
3254
{
3255
	int *res = data;
3256

3257
	if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3258
		return;
3259

3260
	BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3261

3262
	switch (descriptor->data.other_data.data.range.flags) {
3263
	case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3264
		*res = LEVEL_GTF;
3265
		break;
3266
	case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3267
		*res = LEVEL_GTF2;
3268
		break;
3269
	case DRM_EDID_CVT_SUPPORT_FLAG:
3270
		*res = LEVEL_CVT;
3271
		break;
3272
	default:
3273
		break;
3274
	}
3275
}
3276

3277
/* Get standard timing level (CVT/GTF/DMT). */
3278
static int standard_timing_level(const struct drm_edid *drm_edid)
3279
{
3280
	const struct edid *edid = drm_edid->edid;
3281

3282
	if (edid->revision >= 4) {
3283
		/*
3284
		 * If the range descriptor doesn't
3285
		 * indicate otherwise default to CVT
3286
		 */
3287
		int ret = LEVEL_CVT;
3288

3289
		drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
3290

3291
		return ret;
3292
	} else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
3293
		return LEVEL_GTF2;
3294
	} else if (edid->revision >= 2) {
3295
		return LEVEL_GTF;
3296
	} else {
3297
		return LEVEL_DMT;
3298
	}
3299
}
3300

3301
/*
3302
 * 0 is reserved.  The spec says 0x01 fill for unused timings.  Some old
3303
 * monitors fill with ascii space (0x20) instead.
3304
 */
3305
static int
3306
bad_std_timing(u8 a, u8 b)
3307
{
3308
	return (a == 0x00 && b == 0x00) ||
3309
	       (a == 0x01 && b == 0x01) ||
3310
	       (a == 0x20 && b == 0x20);
3311
}
3312

3313
static int drm_mode_hsync(const struct drm_display_mode *mode)
3314
{
3315
	if (mode->htotal <= 0)
3316
		return 0;
3317

3318
	return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3319
}
3320

3321
static struct drm_display_mode *
3322
drm_gtf2_mode(struct drm_device *dev,
3323
	      const struct drm_edid *drm_edid,
3324
	      int hsize, int vsize, int vrefresh_rate)
3325
{
3326
	struct drm_display_mode *mode;
3327

3328
	/*
3329
	 * This is potentially wrong if there's ever a monitor with
3330
	 * more than one ranges section, each claiming a different
3331
	 * secondary GTF curve.  Please don't do that.
3332
	 */
3333
	mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3334
	if (!mode)
3335
		return NULL;
3336

3337
	if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3338
		drm_mode_destroy(dev, mode);
3339
		mode = drm_gtf_mode_complex(dev, hsize, vsize,
3340
					    vrefresh_rate, 0, 0,
3341
					    drm_gtf2_m(drm_edid),
3342
					    drm_gtf2_2c(drm_edid),
3343
					    drm_gtf2_k(drm_edid),
3344
					    drm_gtf2_2j(drm_edid));
3345
	}
3346

3347
	return mode;
3348
}
3349

3350
/*
3351
 * Take the standard timing params (in this case width, aspect, and refresh)
3352
 * and convert them into a real mode using CVT/GTF/DMT.
3353
 */
3354
static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3355
					     const struct drm_edid *drm_edid,
3356
					     const struct std_timing *t)
3357
{
3358
	struct drm_device *dev = connector->dev;
3359
	struct drm_display_mode *m, *mode = NULL;
3360
	int hsize, vsize;
3361
	int vrefresh_rate;
3362
	unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3363
		>> EDID_TIMING_ASPECT_SHIFT;
3364
	unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3365
		>> EDID_TIMING_VFREQ_SHIFT;
3366
	int timing_level = standard_timing_level(drm_edid);
3367

3368
	if (bad_std_timing(t->hsize, t->vfreq_aspect))
3369
		return NULL;
3370

3371
	/* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3372
	hsize = t->hsize * 8 + 248;
3373
	/* vrefresh_rate = vfreq + 60 */
3374
	vrefresh_rate = vfreq + 60;
3375
	/* the vdisplay is calculated based on the aspect ratio */
3376
	if (aspect_ratio == 0) {
3377
		if (drm_edid->edid->revision < 3)
3378
			vsize = hsize;
3379
		else
3380
			vsize = (hsize * 10) / 16;
3381
	} else if (aspect_ratio == 1)
3382
		vsize = (hsize * 3) / 4;
3383
	else if (aspect_ratio == 2)
3384
		vsize = (hsize * 4) / 5;
3385
	else
3386
		vsize = (hsize * 9) / 16;
3387

3388
	/* HDTV hack, part 1 */
3389
	if (vrefresh_rate == 60 &&
3390
	    ((hsize == 1360 && vsize == 765) ||
3391
	     (hsize == 1368 && vsize == 769))) {
3392
		hsize = 1366;
3393
		vsize = 768;
3394
	}
3395

3396
	/*
3397
	 * If this connector already has a mode for this size and refresh
3398
	 * rate (because it came from detailed or CVT info), use that
3399
	 * instead.  This way we don't have to guess at interlace or
3400
	 * reduced blanking.
3401
	 */
3402
	list_for_each_entry(m, &connector->probed_modes, head)
3403
		if (m->hdisplay == hsize && m->vdisplay == vsize &&
3404
		    drm_mode_vrefresh(m) == vrefresh_rate)
3405
			return NULL;
3406

3407
	/* HDTV hack, part 2 */
3408
	if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3409
		mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
3410
				    false);
3411
		if (!mode)
3412
			return NULL;
3413
		mode->hdisplay = 1366;
3414
		mode->hsync_start = mode->hsync_start - 1;
3415
		mode->hsync_end = mode->hsync_end - 1;
3416
		return mode;
3417
	}
3418

3419
	/* check whether it can be found in default mode table */
3420
	if (drm_monitor_supports_rb(drm_edid)) {
3421
		mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3422
					 true);
3423
		if (mode)
3424
			return mode;
3425
	}
3426
	mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
3427
	if (mode)
3428
		return mode;
3429

3430
	/* okay, generate it */
3431
	switch (timing_level) {
3432
	case LEVEL_DMT:
3433
		break;
3434
	case LEVEL_GTF:
3435
		mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3436
		break;
3437
	case LEVEL_GTF2:
3438
		mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate);
3439
		break;
3440
	case LEVEL_CVT:
3441
		mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3442
				    false);
3443
		break;
3444
	}
3445
	return mode;
3446
}
3447

3448
/*
3449
 * EDID is delightfully ambiguous about how interlaced modes are to be
3450
 * encoded.  Our internal representation is of frame height, but some
3451
 * HDTV detailed timings are encoded as field height.
3452
 *
3453
 * The format list here is from CEA, in frame size.  Technically we
3454
 * should be checking refresh rate too.  Whatever.
3455
 */
3456
static void
3457
drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
3458
			    const struct detailed_pixel_timing *pt)
3459
{
3460
	int i;
3461
	static const struct {
3462
		int w, h;
3463
	} cea_interlaced[] = {
3464
		{ 1920, 1080 },
3465
		{  720,  480 },
3466
		{ 1440,  480 },
3467
		{ 2880,  480 },
3468
		{  720,  576 },
3469
		{ 1440,  576 },
3470
		{ 2880,  576 },
3471
	};
3472

3473
	if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3474
		return;
3475

3476
	for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
3477
		if ((mode->hdisplay == cea_interlaced[i].w) &&
3478
		    (mode->vdisplay == cea_interlaced[i].h / 2)) {
3479
			mode->vdisplay *= 2;
3480
			mode->vsync_start *= 2;
3481
			mode->vsync_end *= 2;
3482
			mode->vtotal *= 2;
3483
			mode->vtotal |= 1;
3484
		}
3485
	}
3486

3487
	mode->flags |= DRM_MODE_FLAG_INTERLACE;
3488
}
3489

3490
/*
3491
 * Create a new mode from an EDID detailed timing section. An EDID detailed
3492
 * timing block contains enough info for us to create and return a new struct
3493
 * drm_display_mode.
3494
 */
3495
static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector,
3496
						  const struct drm_edid *drm_edid,
3497
						  const struct detailed_timing *timing)
3498
{
3499
	struct drm_device *dev = connector->dev;
3500
	struct drm_display_mode *mode;
3501
	const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
3502
	unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3503
	unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3504
	unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3505
	unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
3506
	unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3507
	unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
3508
	unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
3509
	unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
3510

3511
	/* ignore tiny modes */
3512
	if (hactive < 64 || vactive < 64)
3513
		return NULL;
3514

3515
	if (pt->misc & DRM_EDID_PT_STEREO) {
3516
		drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n",
3517
			    connector->base.id, connector->name);
3518
		return NULL;
3519
	}
3520
	if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
3521
		drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n",
3522
			    connector->base.id, connector->name);
3523
	}
3524

3525
	/* it is incorrect if hsync/vsync width is zero */
3526
	if (!hsync_pulse_width || !vsync_pulse_width) {
3527
		drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n",
3528
			    connector->base.id, connector->name);
3529
		return NULL;
3530
	}
3531

3532
	if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_FORCE_REDUCED_BLANKING)) {
3533
		mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3534
		if (!mode)
3535
			return NULL;
3536

3537
		goto set_size;
3538
	}
3539

3540
	mode = drm_mode_create(dev);
3541
	if (!mode)
3542
		return NULL;
3543

3544
	if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_135_CLOCK_TOO_HIGH))
3545
		mode->clock = 1088 * 10;
3546
	else
3547
		mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
3548

3549
	mode->hdisplay = hactive;
3550
	mode->hsync_start = mode->hdisplay + hsync_offset;
3551
	mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3552
	mode->htotal = mode->hdisplay + hblank;
3553

3554
	mode->vdisplay = vactive;
3555
	mode->vsync_start = mode->vdisplay + vsync_offset;
3556
	mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3557
	mode->vtotal = mode->vdisplay + vblank;
3558

3559
	/* Some EDIDs have bogus h/vsync_end values */
3560
	if (mode->hsync_end > mode->htotal) {
3561
		drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n",
3562
			    connector->base.id, connector->name,
3563
			    mode->hsync_end, mode->htotal);
3564
		mode->hsync_end = mode->htotal;
3565
	}
3566
	if (mode->vsync_end > mode->vtotal) {
3567
		drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n",
3568
			    connector->base.id, connector->name,
3569
			    mode->vsync_end, mode->vtotal);
3570
		mode->vsync_end = mode->vtotal;
3571
	}
3572

3573
	drm_mode_do_interlace_quirk(mode, pt);
3574

3575
	if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_DETAILED_SYNC_PP)) {
3576
		mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3577
	} else {
3578
		mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3579
			DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3580
		mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3581
			DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3582
	}
3583

3584
set_size:
3585
	mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3586
	mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
3587

3588
	if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_DETAILED_IN_CM)) {
3589
		mode->width_mm *= 10;
3590
		mode->height_mm *= 10;
3591
	}
3592

3593
	if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE)) {
3594
		mode->width_mm = drm_edid->edid->width_cm * 10;
3595
		mode->height_mm = drm_edid->edid->height_cm * 10;
3596
	}
3597

3598
	mode->type = DRM_MODE_TYPE_DRIVER;
3599
	drm_mode_set_name(mode);
3600

3601
	return mode;
3602
}
3603

3604
static bool
3605
mode_in_hsync_range(const struct drm_display_mode *mode,
3606
		    const struct edid *edid, const u8 *t)
3607
{
3608
	int hsync, hmin, hmax;
3609

3610
	hmin = t[7];
3611
	if (edid->revision >= 4)
3612
	    hmin += ((t[4] & 0x04) ? 255 : 0);
3613
	hmax = t[8];
3614
	if (edid->revision >= 4)
3615
	    hmax += ((t[4] & 0x08) ? 255 : 0);
3616
	hsync = drm_mode_hsync(mode);
3617

3618
	return (hsync <= hmax && hsync >= hmin);
3619
}
3620

3621
static bool
3622
mode_in_vsync_range(const struct drm_display_mode *mode,
3623
		    const struct edid *edid, const u8 *t)
3624
{
3625
	int vsync, vmin, vmax;
3626

3627
	vmin = t[5];
3628
	if (edid->revision >= 4)
3629
	    vmin += ((t[4] & 0x01) ? 255 : 0);
3630
	vmax = t[6];
3631
	if (edid->revision >= 4)
3632
	    vmax += ((t[4] & 0x02) ? 255 : 0);
3633
	vsync = drm_mode_vrefresh(mode);
3634

3635
	return (vsync <= vmax && vsync >= vmin);
3636
}
3637

3638
static u32
3639
range_pixel_clock(const struct edid *edid, const u8 *t)
3640
{
3641
	/* unspecified */
3642
	if (t[9] == 0 || t[9] == 255)
3643
		return 0;
3644

3645
	/* 1.4 with CVT support gives us real precision, yay */
3646
	if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3647
		return (t[9] * 10000) - ((t[12] >> 2) * 250);
3648

3649
	/* 1.3 is pathetic, so fuzz up a bit */
3650
	return t[9] * 10000 + 5001;
3651
}
3652

3653
static bool mode_in_range(const struct drm_display_mode *mode,
3654
			  const struct drm_edid *drm_edid,
3655
			  const struct detailed_timing *timing)
3656
{
3657
	const struct edid *edid = drm_edid->edid;
3658
	u32 max_clock;
3659
	const u8 *t = (const u8 *)timing;
3660

3661
	if (!mode_in_hsync_range(mode, edid, t))
3662
		return false;
3663

3664
	if (!mode_in_vsync_range(mode, edid, t))
3665
		return false;
3666

3667
	max_clock = range_pixel_clock(edid, t);
3668
	if (max_clock)
3669
		if (mode->clock > max_clock)
3670
			return false;
3671

3672
	/* 1.4 max horizontal check */
3673
	if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3674
		if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3675
			return false;
3676

3677
	if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
3678
		return false;
3679

3680
	return true;
3681
}
3682

3683
static bool valid_inferred_mode(const struct drm_connector *connector,
3684
				const struct drm_display_mode *mode)
3685
{
3686
	const struct drm_display_mode *m;
3687
	bool ok = false;
3688

3689
	list_for_each_entry(m, &connector->probed_modes, head) {
3690
		if (mode->hdisplay == m->hdisplay &&
3691
		    mode->vdisplay == m->vdisplay &&
3692
		    drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3693
			return false; /* duplicated */
3694
		if (mode->hdisplay <= m->hdisplay &&
3695
		    mode->vdisplay <= m->vdisplay)
3696
			ok = true;
3697
	}
3698
	return ok;
3699
}
3700

3701
static int drm_dmt_modes_for_range(struct drm_connector *connector,
3702
				   const struct drm_edid *drm_edid,
3703
				   const struct detailed_timing *timing)
3704
{
3705
	int i, modes = 0;
3706
	struct drm_display_mode *newmode;
3707
	struct drm_device *dev = connector->dev;
3708

3709
	for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3710
		if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
3711
		    valid_inferred_mode(connector, drm_dmt_modes + i)) {
3712
			newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3713
			if (newmode) {
3714
				drm_mode_probed_add(connector, newmode);
3715
				modes++;
3716
			}
3717
		}
3718
	}
3719

3720
	return modes;
3721
}
3722

3723
/* fix up 1366x768 mode from 1368x768;
3724
 * GFT/CVT can't express 1366 width which isn't dividable by 8
3725
 */
3726
void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3727
{
3728
	if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3729
		mode->hdisplay = 1366;
3730
		mode->hsync_start--;
3731
		mode->hsync_end--;
3732
		drm_mode_set_name(mode);
3733
	}
3734
}
3735

3736
static int drm_gtf_modes_for_range(struct drm_connector *connector,
3737
				   const struct drm_edid *drm_edid,
3738
				   const struct detailed_timing *timing)
3739
{
3740
	int i, modes = 0;
3741
	struct drm_display_mode *newmode;
3742
	struct drm_device *dev = connector->dev;
3743

3744
	for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3745
		const struct minimode *m = &extra_modes[i];
3746

3747
		newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3748
		if (!newmode)
3749
			return modes;
3750

3751
		drm_mode_fixup_1366x768(newmode);
3752
		if (!mode_in_range(newmode, drm_edid, timing) ||
3753
		    !valid_inferred_mode(connector, newmode)) {
3754
			drm_mode_destroy(dev, newmode);
3755
			continue;
3756
		}
3757

3758
		drm_mode_probed_add(connector, newmode);
3759
		modes++;
3760
	}
3761

3762
	return modes;
3763
}
3764

3765
static int drm_gtf2_modes_for_range(struct drm_connector *connector,
3766
				    const struct drm_edid *drm_edid,
3767
				    const struct detailed_timing *timing)
3768
{
3769
	int i, modes = 0;
3770
	struct drm_display_mode *newmode;
3771
	struct drm_device *dev = connector->dev;
3772

3773
	for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3774
		const struct minimode *m = &extra_modes[i];
3775

3776
		newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
3777
		if (!newmode)
3778
			return modes;
3779

3780
		drm_mode_fixup_1366x768(newmode);
3781
		if (!mode_in_range(newmode, drm_edid, timing) ||
3782
		    !valid_inferred_mode(connector, newmode)) {
3783
			drm_mode_destroy(dev, newmode);
3784
			continue;
3785
		}
3786

3787
		drm_mode_probed_add(connector, newmode);
3788
		modes++;
3789
	}
3790

3791
	return modes;
3792
}
3793

3794
static int drm_cvt_modes_for_range(struct drm_connector *connector,
3795
				   const struct drm_edid *drm_edid,
3796
				   const struct detailed_timing *timing)
3797
{
3798
	int i, modes = 0;
3799
	struct drm_display_mode *newmode;
3800
	struct drm_device *dev = connector->dev;
3801
	bool rb = drm_monitor_supports_rb(drm_edid);
3802

3803
	for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3804
		const struct minimode *m = &extra_modes[i];
3805

3806
		newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3807
		if (!newmode)
3808
			return modes;
3809

3810
		drm_mode_fixup_1366x768(newmode);
3811
		if (!mode_in_range(newmode, drm_edid, timing) ||
3812
		    !valid_inferred_mode(connector, newmode)) {
3813
			drm_mode_destroy(dev, newmode);
3814
			continue;
3815
		}
3816

3817
		drm_mode_probed_add(connector, newmode);
3818
		modes++;
3819
	}
3820

3821
	return modes;
3822
}
3823

3824
static void
3825
do_inferred_modes(const struct detailed_timing *timing, void *c)
3826
{
3827
	struct detailed_mode_closure *closure = c;
3828
	const struct detailed_non_pixel *data = &timing->data.other_data;
3829
	const struct detailed_data_monitor_range *range = &data->data.range;
3830

3831
	if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3832
		return;
3833

3834
	closure->modes += drm_dmt_modes_for_range(closure->connector,
3835
						  closure->drm_edid,
3836
						  timing);
3837

3838
	if (closure->drm_edid->edid->revision < 2)
3839
		return; /* GTF not defined yet */
3840

3841
	switch (range->flags) {
3842
	case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3843
		closure->modes += drm_gtf2_modes_for_range(closure->connector,
3844
							   closure->drm_edid,
3845
							   timing);
3846
		break;
3847
	case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3848
		closure->modes += drm_gtf_modes_for_range(closure->connector,
3849
							  closure->drm_edid,
3850
							  timing);
3851
		break;
3852
	case DRM_EDID_CVT_SUPPORT_FLAG:
3853
		if (closure->drm_edid->edid->revision < 4)
3854
			break;
3855

3856
		closure->modes += drm_cvt_modes_for_range(closure->connector,
3857
							  closure->drm_edid,
3858
							  timing);
3859
		break;
3860
	case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
3861
	default:
3862
		break;
3863
	}
3864
}
3865

3866
static int add_inferred_modes(struct drm_connector *connector,
3867
			      const struct drm_edid *drm_edid)
3868
{
3869
	struct detailed_mode_closure closure = {
3870
		.connector = connector,
3871
		.drm_edid = drm_edid,
3872
	};
3873

3874
	if (drm_edid->edid->revision >= 1)
3875
		drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
3876

3877
	return closure.modes;
3878
}
3879

3880
static int
3881
drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3882
{
3883
	int i, j, m, modes = 0;
3884
	struct drm_display_mode *mode;
3885
	const u8 *est = ((const u8 *)timing) + 6;
3886

3887
	for (i = 0; i < 6; i++) {
3888
		for (j = 7; j >= 0; j--) {
3889
			m = (i * 8) + (7 - j);
3890
			if (m >= ARRAY_SIZE(est3_modes))
3891
				break;
3892
			if (est[i] & (1 << j)) {
3893
				mode = drm_mode_find_dmt(connector->dev,
3894
							 est3_modes[m].w,
3895
							 est3_modes[m].h,
3896
							 est3_modes[m].r,
3897
							 est3_modes[m].rb);
3898
				if (mode) {
3899
					drm_mode_probed_add(connector, mode);
3900
					modes++;
3901
				}
3902
			}
3903
		}
3904
	}
3905

3906
	return modes;
3907
}
3908

3909
static void
3910
do_established_modes(const struct detailed_timing *timing, void *c)
3911
{
3912
	struct detailed_mode_closure *closure = c;
3913

3914
	if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3915
		return;
3916

3917
	closure->modes += drm_est3_modes(closure->connector, timing);
3918
}
3919

3920
/*
3921
 * Get established modes from EDID and add them. Each EDID block contains a
3922
 * bitmap of the supported "established modes" list (defined above). Tease them
3923
 * out and add them to the global modes list.
3924
 */
3925
static int add_established_modes(struct drm_connector *connector,
3926
				 const struct drm_edid *drm_edid)
3927
{
3928
	struct drm_device *dev = connector->dev;
3929
	const struct edid *edid = drm_edid->edid;
3930
	unsigned long est_bits = edid->established_timings.t1 |
3931
		(edid->established_timings.t2 << 8) |
3932
		((edid->established_timings.mfg_rsvd & 0x80) << 9);
3933
	int i, modes = 0;
3934
	struct detailed_mode_closure closure = {
3935
		.connector = connector,
3936
		.drm_edid = drm_edid,
3937
	};
3938

3939
	for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3940
		if (est_bits & (1<<i)) {
3941
			struct drm_display_mode *newmode;
3942

3943
			newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3944
			if (newmode) {
3945
				drm_mode_probed_add(connector, newmode);
3946
				modes++;
3947
			}
3948
		}
3949
	}
3950

3951
	if (edid->revision >= 1)
3952
		drm_for_each_detailed_block(drm_edid, do_established_modes,
3953
					    &closure);
3954

3955
	return modes + closure.modes;
3956
}
3957

3958
static void
3959
do_standard_modes(const struct detailed_timing *timing, void *c)
3960
{
3961
	struct detailed_mode_closure *closure = c;
3962
	const struct detailed_non_pixel *data = &timing->data.other_data;
3963
	struct drm_connector *connector = closure->connector;
3964
	int i;
3965

3966
	if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3967
		return;
3968

3969
	for (i = 0; i < 6; i++) {
3970
		const struct std_timing *std = &data->data.timings[i];
3971
		struct drm_display_mode *newmode;
3972

3973
		newmode = drm_mode_std(connector, closure->drm_edid, std);
3974
		if (newmode) {
3975
			drm_mode_probed_add(connector, newmode);
3976
			closure->modes++;
3977
		}
3978
	}
3979
}
3980

3981
/*
3982
 * Get standard modes from EDID and add them. Standard modes can be calculated
3983
 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3984
 * add them to the list.
3985
 */
3986
static int add_standard_modes(struct drm_connector *connector,
3987
			      const struct drm_edid *drm_edid)
3988
{
3989
	int i, modes = 0;
3990
	struct detailed_mode_closure closure = {
3991
		.connector = connector,
3992
		.drm_edid = drm_edid,
3993
	};
3994

3995
	for (i = 0; i < EDID_STD_TIMINGS; i++) {
3996
		struct drm_display_mode *newmode;
3997

3998
		newmode = drm_mode_std(connector, drm_edid,
3999
				       &drm_edid->edid->standard_timings[i]);
4000
		if (newmode) {
4001
			drm_mode_probed_add(connector, newmode);
4002
			modes++;
4003
		}
4004
	}
4005

4006
	if (drm_edid->edid->revision >= 1)
4007
		drm_for_each_detailed_block(drm_edid, do_standard_modes,
4008
					    &closure);
4009

4010
	/* XXX should also look for standard codes in VTB blocks */
4011

4012
	return modes + closure.modes;
4013
}
4014

4015
static int drm_cvt_modes(struct drm_connector *connector,
4016
			 const struct detailed_timing *timing)
4017
{
4018
	int i, j, modes = 0;
4019
	struct drm_display_mode *newmode;
4020
	struct drm_device *dev = connector->dev;
4021
	const struct cvt_timing *cvt;
4022
	static const int rates[] = { 60, 85, 75, 60, 50 };
4023
	const u8 empty[3] = { 0, 0, 0 };
4024

4025
	for (i = 0; i < 4; i++) {
4026
		int width, height;
4027

4028
		cvt = &(timing->data.other_data.data.cvt[i]);
4029

4030
		if (!memcmp(cvt->code, empty, 3))
4031
			continue;
4032

4033
		height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
4034
		switch (cvt->code[1] & 0x0c) {
4035
		/* default - because compiler doesn't see that we've enumerated all cases */
4036
		default:
4037
		case 0x00:
4038
			width = height * 4 / 3;
4039
			break;
4040
		case 0x04:
4041
			width = height * 16 / 9;
4042
			break;
4043
		case 0x08:
4044
			width = height * 16 / 10;
4045
			break;
4046
		case 0x0c:
4047
			width = height * 15 / 9;
4048
			break;
4049
		}
4050

4051
		for (j = 1; j < 5; j++) {
4052
			if (cvt->code[2] & (1 << j)) {
4053
				newmode = drm_cvt_mode(dev, width, height,
4054
						       rates[j], j == 0,
4055
						       false, false);
4056
				if (newmode) {
4057
					drm_mode_probed_add(connector, newmode);
4058
					modes++;
4059
				}
4060
			}
4061
		}
4062
	}
4063

4064
	return modes;
4065
}
4066

4067
static void
4068
do_cvt_mode(const struct detailed_timing *timing, void *c)
4069
{
4070
	struct detailed_mode_closure *closure = c;
4071

4072
	if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
4073
		return;
4074

4075
	closure->modes += drm_cvt_modes(closure->connector, timing);
4076
}
4077

4078
static int
4079
add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
4080
{
4081
	struct detailed_mode_closure closure = {
4082
		.connector = connector,
4083
		.drm_edid = drm_edid,
4084
	};
4085

4086
	if (drm_edid->edid->revision >= 3)
4087
		drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
4088

4089
	/* XXX should also look for CVT codes in VTB blocks */
4090

4091
	return closure.modes;
4092
}
4093

4094
static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
4095
					  struct drm_display_mode *mode);
4096

4097
static void
4098
do_detailed_mode(const struct detailed_timing *timing, void *c)
4099
{
4100
	struct detailed_mode_closure *closure = c;
4101
	struct drm_display_mode *newmode;
4102

4103
	if (!is_detailed_timing_descriptor(timing))
4104
		return;
4105

4106
	newmode = drm_mode_detailed(closure->connector,
4107
				    closure->drm_edid, timing);
4108
	if (!newmode)
4109
		return;
4110

4111
	if (closure->preferred)
4112
		newmode->type |= DRM_MODE_TYPE_PREFERRED;
4113

4114
	/*
4115
	 * Detailed modes are limited to 10kHz pixel clock resolution,
4116
	 * so fix up anything that looks like CEA/HDMI mode, but the clock
4117
	 * is just slightly off.
4118
	 */
4119
	fixup_detailed_cea_mode_clock(closure->connector, newmode);
4120

4121
	drm_mode_probed_add(closure->connector, newmode);
4122
	closure->modes++;
4123
	closure->preferred = false;
4124
}
4125

4126
/*
4127
 * add_detailed_modes - Add modes from detailed timings
4128
 * @connector: attached connector
4129
 * @drm_edid: EDID block to scan
4130
 */
4131
static int add_detailed_modes(struct drm_connector *connector,
4132
			      const struct drm_edid *drm_edid)
4133
{
4134
	struct detailed_mode_closure closure = {
4135
		.connector = connector,
4136
		.drm_edid = drm_edid,
4137
	};
4138

4139
	if (drm_edid->edid->revision >= 4)
4140
		closure.preferred = true; /* first detailed timing is always preferred */
4141
	else
4142
		closure.preferred =
4143
			drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING;
4144

4145
	drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
4146

4147
	return closure.modes;
4148
}
4149

4150
/* CTA-861-H Table 60 - CTA Tag Codes */
4151
#define CTA_DB_AUDIO			1
4152
#define CTA_DB_VIDEO			2
4153
#define CTA_DB_VENDOR			3
4154
#define CTA_DB_SPEAKER			4
4155
#define CTA_DB_EXTENDED_TAG		7
4156

4157
/* CTA-861-H Table 62 - CTA Extended Tag Codes */
4158
#define CTA_EXT_DB_VIDEO_CAP		0
4159
#define CTA_EXT_DB_VENDOR		1
4160
#define CTA_EXT_DB_HDR_STATIC_METADATA	6
4161
#define CTA_EXT_DB_420_VIDEO_DATA	14
4162
#define CTA_EXT_DB_420_VIDEO_CAP_MAP	15
4163
#define CTA_EXT_DB_HF_EEODB		0x78
4164
#define CTA_EXT_DB_HF_SCDB		0x79
4165

4166
#define EDID_BASIC_AUDIO	(1 << 6)
4167
#define EDID_CEA_YCRCB444	(1 << 5)
4168
#define EDID_CEA_YCRCB422	(1 << 4)
4169
#define EDID_CEA_VCDB_QS	(1 << 6)
4170

4171
/*
4172
 * Search EDID for CEA extension block.
4173
 *
4174
 * FIXME: Prefer not returning pointers to raw EDID data.
4175
 */
4176
const u8 *drm_edid_find_extension(const struct drm_edid *drm_edid,
4177
				  int ext_id, int *ext_index)
4178
{
4179
	const u8 *edid_ext = NULL;
4180
	int i;
4181

4182
	/* No EDID or EDID extensions */
4183
	if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
4184
		return NULL;
4185

4186
	/* Find CEA extension */
4187
	for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
4188
		edid_ext = drm_edid_extension_block_data(drm_edid, i);
4189
		if (edid_block_tag(edid_ext) == ext_id)
4190
			break;
4191
	}
4192

4193
	if (i >= drm_edid_extension_block_count(drm_edid))
4194
		return NULL;
4195

4196
	*ext_index = i + 1;
4197

4198
	return edid_ext;
4199
}
4200

4201
/* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
4202
static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
4203
{
4204
	const struct displayid_block *block;
4205
	struct displayid_iter iter;
4206
	struct drm_edid_iter edid_iter;
4207
	const u8 *ext;
4208
	bool found = false;
4209

4210
	/* Look for a top level CEA extension block */
4211
	drm_edid_iter_begin(drm_edid, &edid_iter);
4212
	drm_edid_iter_for_each(ext, &edid_iter) {
4213
		if (ext[0] == CEA_EXT) {
4214
			found = true;
4215
			break;
4216
		}
4217
	}
4218
	drm_edid_iter_end(&edid_iter);
4219

4220
	if (found)
4221
		return true;
4222

4223
	/* CEA blocks can also be found embedded in a DisplayID block */
4224
	displayid_iter_edid_begin(drm_edid, &iter);
4225
	displayid_iter_for_each(block, &iter) {
4226
		if (block->tag == DATA_BLOCK_CTA) {
4227
			found = true;
4228
			break;
4229
		}
4230
	}
4231
	displayid_iter_end(&iter);
4232

4233
	return found;
4234
}
4235

4236
static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
4237
{
4238
	BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
4239
	BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
4240

4241
	if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
4242
		return &edid_cea_modes_1[vic - 1];
4243
	if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
4244
		return &edid_cea_modes_193[vic - 193];
4245
	return NULL;
4246
}
4247

4248
static u8 cea_num_vics(void)
4249
{
4250
	return 193 + ARRAY_SIZE(edid_cea_modes_193);
4251
}
4252

4253
static u8 cea_next_vic(u8 vic)
4254
{
4255
	if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
4256
		vic = 193;
4257
	return vic;
4258
}
4259

4260
/*
4261
 * Calculate the alternate clock for the CEA mode
4262
 * (60Hz vs. 59.94Hz etc.)
4263
 */
4264
static unsigned int
4265
cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4266
{
4267
	unsigned int clock = cea_mode->clock;
4268

4269
	if (drm_mode_vrefresh(cea_mode) % 6 != 0)
4270
		return clock;
4271

4272
	/*
4273
	 * edid_cea_modes contains the 59.94Hz
4274
	 * variant for 240 and 480 line modes,
4275
	 * and the 60Hz variant otherwise.
4276
	 */
4277
	if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
4278
		clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
4279
	else
4280
		clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
4281

4282
	return clock;
4283
}
4284

4285
static bool
4286
cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4287
{
4288
	/*
4289
	 * For certain VICs the spec allows the vertical
4290
	 * front porch to vary by one or two lines.
4291
	 *
4292
	 * cea_modes[] stores the variant with the shortest
4293
	 * vertical front porch. We can adjust the mode to
4294
	 * get the other variants by simply increasing the
4295
	 * vertical front porch length.
4296
	 */
4297
	BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4298
		     cea_mode_for_vic(9)->vtotal != 262 ||
4299
		     cea_mode_for_vic(12)->vtotal != 262 ||
4300
		     cea_mode_for_vic(13)->vtotal != 262 ||
4301
		     cea_mode_for_vic(23)->vtotal != 312 ||
4302
		     cea_mode_for_vic(24)->vtotal != 312 ||
4303
		     cea_mode_for_vic(27)->vtotal != 312 ||
4304
		     cea_mode_for_vic(28)->vtotal != 312);
4305

4306
	if (((vic == 8 || vic == 9 ||
4307
	      vic == 12 || vic == 13) && mode->vtotal < 263) ||
4308
	    ((vic == 23 || vic == 24 ||
4309
	      vic == 27 || vic == 28) && mode->vtotal < 314)) {
4310
		mode->vsync_start++;
4311
		mode->vsync_end++;
4312
		mode->vtotal++;
4313

4314
		return true;
4315
	}
4316

4317
	return false;
4318
}
4319

4320
static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4321
					     unsigned int clock_tolerance)
4322
{
4323
	unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4324
	u8 vic;
4325

4326
	if (!to_match->clock)
4327
		return 0;
4328

4329
	if (to_match->picture_aspect_ratio)
4330
		match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4331

4332
	for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4333
		struct drm_display_mode cea_mode;
4334
		unsigned int clock1, clock2;
4335

4336
		drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4337

4338
		/* Check both 60Hz and 59.94Hz */
4339
		clock1 = cea_mode.clock;
4340
		clock2 = cea_mode_alternate_clock(&cea_mode);
4341

4342
		if (abs(to_match->clock - clock1) > clock_tolerance &&
4343
		    abs(to_match->clock - clock2) > clock_tolerance)
4344
			continue;
4345

4346
		do {
4347
			if (drm_mode_match(to_match, &cea_mode, match_flags))
4348
				return vic;
4349
		} while (cea_mode_alternate_timings(vic, &cea_mode));
4350
	}
4351

4352
	return 0;
4353
}
4354

4355
/**
4356
 * drm_match_cea_mode - look for a CEA mode matching given mode
4357
 * @to_match: display mode
4358
 *
4359
 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
4360
 * mode.
4361
 */
4362
u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
4363
{
4364
	unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4365
	u8 vic;
4366

4367
	if (!to_match->clock)
4368
		return 0;
4369

4370
	if (to_match->picture_aspect_ratio)
4371
		match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4372

4373
	for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4374
		struct drm_display_mode cea_mode;
4375
		unsigned int clock1, clock2;
4376

4377
		drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4378

4379
		/* Check both 60Hz and 59.94Hz */
4380
		clock1 = cea_mode.clock;
4381
		clock2 = cea_mode_alternate_clock(&cea_mode);
4382

4383
		if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4384
		    KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4385
			continue;
4386

4387
		do {
4388
			if (drm_mode_match(to_match, &cea_mode, match_flags))
4389
				return vic;
4390
		} while (cea_mode_alternate_timings(vic, &cea_mode));
4391
	}
4392

4393
	return 0;
4394
}
4395
EXPORT_SYMBOL(drm_match_cea_mode);
4396

4397
static bool drm_valid_cea_vic(u8 vic)
4398
{
4399
	return cea_mode_for_vic(vic) != NULL;
4400
}
4401

4402
static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
4403
{
4404
	const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4405

4406
	if (mode)
4407
		return mode->picture_aspect_ratio;
4408

4409
	return HDMI_PICTURE_ASPECT_NONE;
4410
}
4411

4412
static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4413
{
4414
	return edid_4k_modes[video_code].picture_aspect_ratio;
4415
}
4416

4417
/*
4418
 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4419
 * specific block).
4420
 */
4421
static unsigned int
4422
hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4423
{
4424
	return cea_mode_alternate_clock(hdmi_mode);
4425
}
4426

4427
static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4428
					      unsigned int clock_tolerance)
4429
{
4430
	unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4431
	u8 vic;
4432

4433
	if (!to_match->clock)
4434
		return 0;
4435

4436
	if (to_match->picture_aspect_ratio)
4437
		match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4438

4439
	for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4440
		const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4441
		unsigned int clock1, clock2;
4442

4443
		/* Make sure to also match alternate clocks */
4444
		clock1 = hdmi_mode->clock;
4445
		clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4446

4447
		if (abs(to_match->clock - clock1) > clock_tolerance &&
4448
		    abs(to_match->clock - clock2) > clock_tolerance)
4449
			continue;
4450

4451
		if (drm_mode_match(to_match, hdmi_mode, match_flags))
4452
			return vic;
4453
	}
4454

4455
	return 0;
4456
}
4457

4458
/*
4459
 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4460
 * @to_match: display mode
4461
 *
4462
 * An HDMI mode is one defined in the HDMI vendor specific block.
4463
 *
4464
 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4465
 */
4466
static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4467
{
4468
	unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4469
	u8 vic;
4470

4471
	if (!to_match->clock)
4472
		return 0;
4473

4474
	if (to_match->picture_aspect_ratio)
4475
		match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4476

4477
	for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4478
		const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4479
		unsigned int clock1, clock2;
4480

4481
		/* Make sure to also match alternate clocks */
4482
		clock1 = hdmi_mode->clock;
4483
		clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4484

4485
		if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4486
		     KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4487
		    drm_mode_match(to_match, hdmi_mode, match_flags))
4488
			return vic;
4489
	}
4490
	return 0;
4491
}
4492

4493
static bool drm_valid_hdmi_vic(u8 vic)
4494
{
4495
	return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4496
}
4497

4498
static int add_alternate_cea_modes(struct drm_connector *connector,
4499
				   const struct drm_edid *drm_edid)
4500
{
4501
	struct drm_device *dev = connector->dev;
4502
	struct drm_display_mode *mode, *tmp;
4503
	LIST_HEAD(list);
4504
	int modes = 0;
4505

4506
	/* Don't add CTA modes if the CTA extension block is missing */
4507
	if (!drm_edid_has_cta_extension(drm_edid))
4508
		return 0;
4509

4510
	/*
4511
	 * Go through all probed modes and create a new mode
4512
	 * with the alternate clock for certain CEA modes.
4513
	 */
4514
	list_for_each_entry(mode, &connector->probed_modes, head) {
4515
		const struct drm_display_mode *cea_mode = NULL;
4516
		struct drm_display_mode *newmode;
4517
		u8 vic = drm_match_cea_mode(mode);
4518
		unsigned int clock1, clock2;
4519

4520
		if (drm_valid_cea_vic(vic)) {
4521
			cea_mode = cea_mode_for_vic(vic);
4522
			clock2 = cea_mode_alternate_clock(cea_mode);
4523
		} else {
4524
			vic = drm_match_hdmi_mode(mode);
4525
			if (drm_valid_hdmi_vic(vic)) {
4526
				cea_mode = &edid_4k_modes[vic];
4527
				clock2 = hdmi_mode_alternate_clock(cea_mode);
4528
			}
4529
		}
4530

4531
		if (!cea_mode)
4532
			continue;
4533

4534
		clock1 = cea_mode->clock;
4535

4536
		if (clock1 == clock2)
4537
			continue;
4538

4539
		if (mode->clock != clock1 && mode->clock != clock2)
4540
			continue;
4541

4542
		newmode = drm_mode_duplicate(dev, cea_mode);
4543
		if (!newmode)
4544
			continue;
4545

4546
		/* Carry over the stereo flags */
4547
		newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4548

4549
		/*
4550
		 * The current mode could be either variant. Make
4551
		 * sure to pick the "other" clock for the new mode.
4552
		 */
4553
		if (mode->clock != clock1)
4554
			newmode->clock = clock1;
4555
		else
4556
			newmode->clock = clock2;
4557

4558
		list_add_tail(&newmode->head, &list);
4559
	}
4560

4561
	list_for_each_entry_safe(mode, tmp, &list, head) {
4562
		list_del(&mode->head);
4563
		drm_mode_probed_add(connector, mode);
4564
		modes++;
4565
	}
4566

4567
	return modes;
4568
}
4569

4570
static u8 svd_to_vic(u8 svd)
4571
{
4572
	/* 0-6 bit vic, 7th bit native mode indicator */
4573
	if ((svd >= 1 &&  svd <= 64) || (svd >= 129 && svd <= 192))
4574
		return svd & 127;
4575

4576
	return svd;
4577
}
4578

4579
/*
4580
 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in
4581
 * the EDID, or NULL on errors.
4582
 */
4583
static struct drm_display_mode *
4584
drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index)
4585
{
4586
	const struct drm_display_info *info = &connector->display_info;
4587
	struct drm_device *dev = connector->dev;
4588

4589
	if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index])
4590
		return NULL;
4591

4592
	return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]);
4593
}
4594

4595
/*
4596
 * do_y420vdb_modes - Parse YCBCR 420 only modes
4597
 * @connector: connector corresponding to the HDMI sink
4598
 * @svds: start of the data block of CEA YCBCR 420 VDB
4599
 * @len: length of the CEA YCBCR 420 VDB
4600
 *
4601
 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4602
 * which contains modes which can be supported in YCBCR 420
4603
 * output format only.
4604
 */
4605
static int do_y420vdb_modes(struct drm_connector *connector,
4606
			    const u8 *svds, u8 svds_len)
4607
{
4608
	struct drm_device *dev = connector->dev;
4609
	int modes = 0, i;
4610

4611
	for (i = 0; i < svds_len; i++) {
4612
		u8 vic = svd_to_vic(svds[i]);
4613
		struct drm_display_mode *newmode;
4614

4615
		if (!drm_valid_cea_vic(vic))
4616
			continue;
4617

4618
		newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4619
		if (!newmode)
4620
			break;
4621
		drm_mode_probed_add(connector, newmode);
4622
		modes++;
4623
	}
4624

4625
	return modes;
4626
}
4627

4628
/**
4629
 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4630
 * @dev: DRM device
4631
 * @video_code: CEA VIC of the mode
4632
 *
4633
 * Creates a new mode matching the specified CEA VIC.
4634
 *
4635
 * Returns: A new drm_display_mode on success or NULL on failure
4636
 */
4637
struct drm_display_mode *
4638
drm_display_mode_from_cea_vic(struct drm_device *dev,
4639
			      u8 video_code)
4640
{
4641
	const struct drm_display_mode *cea_mode;
4642
	struct drm_display_mode *newmode;
4643

4644
	cea_mode = cea_mode_for_vic(video_code);
4645
	if (!cea_mode)
4646
		return NULL;
4647

4648
	newmode = drm_mode_duplicate(dev, cea_mode);
4649
	if (!newmode)
4650
		return NULL;
4651

4652
	return newmode;
4653
}
4654
EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4655

4656
/* Add modes based on VICs parsed in parse_cta_vdb() */
4657
static int add_cta_vdb_modes(struct drm_connector *connector)
4658
{
4659
	const struct drm_display_info *info = &connector->display_info;
4660
	int i, modes = 0;
4661

4662
	if (!info->vics)
4663
		return 0;
4664

4665
	for (i = 0; i < info->vics_len; i++) {
4666
		struct drm_display_mode *mode;
4667

4668
		mode = drm_display_mode_from_vic_index(connector, i);
4669
		if (mode) {
4670
			drm_mode_probed_add(connector, mode);
4671
			modes++;
4672
		}
4673
	}
4674

4675
	return modes;
4676
}
4677

4678
struct stereo_mandatory_mode {
4679
	int width, height, vrefresh;
4680
	unsigned int flags;
4681
};
4682

4683
static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4684
	{ 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4685
	{ 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4686
	{ 1920, 1080, 50,
4687
	  DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4688
	{ 1920, 1080, 60,
4689
	  DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4690
	{ 1280, 720,  50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4691
	{ 1280, 720,  50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4692
	{ 1280, 720,  60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4693
	{ 1280, 720,  60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4694
};
4695

4696
static bool
4697
stereo_match_mandatory(const struct drm_display_mode *mode,
4698
		       const struct stereo_mandatory_mode *stereo_mode)
4699
{
4700
	unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4701

4702
	return mode->hdisplay == stereo_mode->width &&
4703
	       mode->vdisplay == stereo_mode->height &&
4704
	       interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4705
	       drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4706
}
4707

4708
static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4709
{
4710
	struct drm_device *dev = connector->dev;
4711
	const struct drm_display_mode *mode;
4712
	struct list_head stereo_modes;
4713
	int modes = 0, i;
4714

4715
	INIT_LIST_HEAD(&stereo_modes);
4716

4717
	list_for_each_entry(mode, &connector->probed_modes, head) {
4718
		for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4719
			const struct stereo_mandatory_mode *mandatory;
4720
			struct drm_display_mode *new_mode;
4721

4722
			if (!stereo_match_mandatory(mode,
4723
						    &stereo_mandatory_modes[i]))
4724
				continue;
4725

4726
			mandatory = &stereo_mandatory_modes[i];
4727
			new_mode = drm_mode_duplicate(dev, mode);
4728
			if (!new_mode)
4729
				continue;
4730

4731
			new_mode->flags |= mandatory->flags;
4732
			list_add_tail(&new_mode->head, &stereo_modes);
4733
			modes++;
4734
		}
4735
	}
4736

4737
	list_splice_tail(&stereo_modes, &connector->probed_modes);
4738

4739
	return modes;
4740
}
4741

4742
static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4743
{
4744
	struct drm_device *dev = connector->dev;
4745
	struct drm_display_mode *newmode;
4746

4747
	if (!drm_valid_hdmi_vic(vic)) {
4748
		drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n",
4749
			connector->base.id, connector->name, vic);
4750
		return 0;
4751
	}
4752

4753
	newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4754
	if (!newmode)
4755
		return 0;
4756

4757
	drm_mode_probed_add(connector, newmode);
4758

4759
	return 1;
4760
}
4761

4762
static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4763
			       int vic_index)
4764
{
4765
	struct drm_display_mode *newmode;
4766
	int modes = 0;
4767

4768
	if (structure & (1 << 0)) {
4769
		newmode = drm_display_mode_from_vic_index(connector, vic_index);
4770
		if (newmode) {
4771
			newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4772
			drm_mode_probed_add(connector, newmode);
4773
			modes++;
4774
		}
4775
	}
4776
	if (structure & (1 << 6)) {
4777
		newmode = drm_display_mode_from_vic_index(connector, vic_index);
4778
		if (newmode) {
4779
			newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4780
			drm_mode_probed_add(connector, newmode);
4781
			modes++;
4782
		}
4783
	}
4784
	if (structure & (1 << 8)) {
4785
		newmode = drm_display_mode_from_vic_index(connector, vic_index);
4786
		if (newmode) {
4787
			newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4788
			drm_mode_probed_add(connector, newmode);
4789
			modes++;
4790
		}
4791
	}
4792

4793
	return modes;
4794
}
4795

4796
static bool hdmi_vsdb_latency_present(const u8 *db)
4797
{
4798
	return db[8] & BIT(7);
4799
}
4800

4801
static bool hdmi_vsdb_i_latency_present(const u8 *db)
4802
{
4803
	return hdmi_vsdb_latency_present(db) && db[8] & BIT(6);
4804
}
4805

4806
static int hdmi_vsdb_latency_length(const u8 *db)
4807
{
4808
	if (hdmi_vsdb_i_latency_present(db))
4809
		return 4;
4810
	else if (hdmi_vsdb_latency_present(db))
4811
		return 2;
4812
	else
4813
		return 0;
4814
}
4815

4816
/*
4817
 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4818
 * @connector: connector corresponding to the HDMI sink
4819
 * @db: start of the CEA vendor specific block
4820
 * @len: length of the CEA block payload, ie. one can access up to db[len]
4821
 *
4822
 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4823
 * also adds the stereo 3d modes when applicable.
4824
 */
4825
static int
4826
do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len)
4827
{
4828
	int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4829
	u8 vic_len, hdmi_3d_len = 0;
4830
	u16 mask;
4831
	u16 structure_all;
4832

4833
	if (len < 8)
4834
		goto out;
4835

4836
	/* no HDMI_Video_Present */
4837
	if (!(db[8] & (1 << 5)))
4838
		goto out;
4839

4840
	offset += hdmi_vsdb_latency_length(db);
4841

4842
	/* the declared length is not long enough for the 2 first bytes
4843
	 * of additional video format capabilities */
4844
	if (len < (8 + offset + 2))
4845
		goto out;
4846

4847
	/* 3D_Present */
4848
	offset++;
4849
	if (db[8 + offset] & (1 << 7)) {
4850
		modes += add_hdmi_mandatory_stereo_modes(connector);
4851

4852
		/* 3D_Multi_present */
4853
		multi_present = (db[8 + offset] & 0x60) >> 5;
4854
	}
4855

4856
	offset++;
4857
	vic_len = db[8 + offset] >> 5;
4858
	hdmi_3d_len = db[8 + offset] & 0x1f;
4859

4860
	for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4861
		u8 vic;
4862

4863
		vic = db[9 + offset + i];
4864
		modes += add_hdmi_mode(connector, vic);
4865
	}
4866
	offset += 1 + vic_len;
4867

4868
	if (multi_present == 1)
4869
		multi_len = 2;
4870
	else if (multi_present == 2)
4871
		multi_len = 4;
4872
	else
4873
		multi_len = 0;
4874

4875
	if (len < (8 + offset + hdmi_3d_len - 1))
4876
		goto out;
4877

4878
	if (hdmi_3d_len < multi_len)
4879
		goto out;
4880

4881
	if (multi_present == 1 || multi_present == 2) {
4882
		/* 3D_Structure_ALL */
4883
		structure_all = (db[8 + offset] << 8) | db[9 + offset];
4884

4885
		/* check if 3D_MASK is present */
4886
		if (multi_present == 2)
4887
			mask = (db[10 + offset] << 8) | db[11 + offset];
4888
		else
4889
			mask = 0xffff;
4890

4891
		for (i = 0; i < 16; i++) {
4892
			if (mask & (1 << i))
4893
				modes += add_3d_struct_modes(connector,
4894
							     structure_all, i);
4895
		}
4896
	}
4897

4898
	offset += multi_len;
4899

4900
	for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4901
		int vic_index;
4902
		struct drm_display_mode *newmode = NULL;
4903
		unsigned int newflag = 0;
4904
		bool detail_present;
4905

4906
		detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4907

4908
		if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4909
			break;
4910

4911
		/* 2D_VIC_order_X */
4912
		vic_index = db[8 + offset + i] >> 4;
4913

4914
		/* 3D_Structure_X */
4915
		switch (db[8 + offset + i] & 0x0f) {
4916
		case 0:
4917
			newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4918
			break;
4919
		case 6:
4920
			newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4921
			break;
4922
		case 8:
4923
			/* 3D_Detail_X */
4924
			if ((db[9 + offset + i] >> 4) == 1)
4925
				newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4926
			break;
4927
		}
4928

4929
		if (newflag != 0) {
4930
			newmode = drm_display_mode_from_vic_index(connector,
4931
								  vic_index);
4932

4933
			if (newmode) {
4934
				newmode->flags |= newflag;
4935
				drm_mode_probed_add(connector, newmode);
4936
				modes++;
4937
			}
4938
		}
4939

4940
		if (detail_present)
4941
			i++;
4942
	}
4943

4944
out:
4945
	return modes;
4946
}
4947

4948
static int
4949
cea_revision(const u8 *cea)
4950
{
4951
	/*
4952
	 * FIXME is this correct for the DispID variant?
4953
	 * The DispID spec doesn't really specify whether
4954
	 * this is the revision of the CEA extension or
4955
	 * the DispID CEA data block. And the only value
4956
	 * given as an example is 0.
4957
	 */
4958
	return cea[1];
4959
}
4960

4961
/*
4962
 * CTA Data Block iterator.
4963
 *
4964
 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4965
 * CTA Data Blocks.
4966
 *
4967
 * struct cea_db *db:
4968
 * struct cea_db_iter iter;
4969
 *
4970
 * cea_db_iter_edid_begin(edid, &iter);
4971
 * cea_db_iter_for_each(db, &iter) {
4972
 *         // do stuff with db
4973
 * }
4974
 * cea_db_iter_end(&iter);
4975
 */
4976
struct cea_db_iter {
4977
	struct drm_edid_iter edid_iter;
4978
	struct displayid_iter displayid_iter;
4979

4980
	/* Current Data Block Collection. */
4981
	const u8 *collection;
4982

4983
	/* Current Data Block index in current collection. */
4984
	int index;
4985

4986
	/* End index in current collection. */
4987
	int end;
4988
};
4989

4990
/* CTA-861-H section 7.4 CTA Data BLock Collection */
4991
struct cea_db {
4992
	u8 tag_length;
4993
	u8 data[];
4994
} __packed;
4995

4996
static int cea_db_tag(const struct cea_db *db)
4997
{
4998
	return db->tag_length >> 5;
4999
}
5000

5001
static int cea_db_payload_len(const void *_db)
5002
{
5003
	/* FIXME: Transition to passing struct cea_db * everywhere. */
5004
	const struct cea_db *db = _db;
5005

5006
	return db->tag_length & 0x1f;
5007
}
5008

5009
static const void *cea_db_data(const struct cea_db *db)
5010
{
5011
	return db->data;
5012
}
5013

5014
static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
5015
{
5016
	return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
5017
		cea_db_payload_len(db) >= 1 &&
5018
		db->data[0] == tag;
5019
}
5020

5021
static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
5022
{
5023
	const u8 *data = cea_db_data(db);
5024

5025
	return cea_db_tag(db) == CTA_DB_VENDOR &&
5026
		cea_db_payload_len(db) >= 3 &&
5027
		oui(data[2], data[1], data[0]) == vendor_oui;
5028
}
5029

5030
static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
5031
				   struct cea_db_iter *iter)
5032
{
5033
	memset(iter, 0, sizeof(*iter));
5034

5035
	drm_edid_iter_begin(drm_edid, &iter->edid_iter);
5036
	displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
5037
}
5038

5039
static const struct cea_db *
5040
__cea_db_iter_current_block(const struct cea_db_iter *iter)
5041
{
5042
	const struct cea_db *db;
5043

5044
	if (!iter->collection)
5045
		return NULL;
5046

5047
	db = (const struct cea_db *)&iter->collection[iter->index];
5048

5049
	if (iter->index + sizeof(*db) <= iter->end &&
5050
	    iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
5051
		return db;
5052

5053
	return NULL;
5054
}
5055

5056
/*
5057
 * References:
5058
 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5059
 */
5060
static int cea_db_collection_size(const u8 *cta)
5061
{
5062
	u8 d = cta[2];
5063

5064
	if (d < 4 || d > 127)
5065
		return 0;
5066

5067
	return d - 4;
5068
}
5069

5070
/*
5071
 * References:
5072
 * - VESA E-EDID v1.4
5073
 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5074
 */
5075
static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
5076
{
5077
	const u8 *ext;
5078

5079
	drm_edid_iter_for_each(ext, &iter->edid_iter) {
5080
		int size;
5081

5082
		/* Only support CTA Extension revision 3+ */
5083
		if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
5084
			continue;
5085

5086
		size = cea_db_collection_size(ext);
5087
		if (!size)
5088
			continue;
5089

5090
		iter->index = 4;
5091
		iter->end = iter->index + size;
5092

5093
		return ext;
5094
	}
5095

5096
	return NULL;
5097
}
5098

5099
/*
5100
 * References:
5101
 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
5102
 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
5103
 *
5104
 * Note that the above do not specify any connection between DisplayID Data
5105
 * Block revision and CTA Extension versions.
5106
 */
5107
static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
5108
{
5109
	const struct displayid_block *block;
5110

5111
	displayid_iter_for_each(block, &iter->displayid_iter) {
5112
		if (block->tag != DATA_BLOCK_CTA)
5113
			continue;
5114

5115
		/*
5116
		 * The displayid iterator has already verified the block bounds
5117
		 * in displayid_iter_block().
5118
		 */
5119
		iter->index = sizeof(*block);
5120
		iter->end = iter->index + block->num_bytes;
5121

5122
		return block;
5123
	}
5124

5125
	return NULL;
5126
}
5127

5128
static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
5129
{
5130
	const struct cea_db *db;
5131

5132
	if (iter->collection) {
5133
		/* Current collection should always be valid. */
5134
		db = __cea_db_iter_current_block(iter);
5135
		if (WARN_ON(!db)) {
5136
			iter->collection = NULL;
5137
			return NULL;
5138
		}
5139

5140
		/* Next block in CTA Data Block Collection */
5141
		iter->index += sizeof(*db) + cea_db_payload_len(db);
5142

5143
		db = __cea_db_iter_current_block(iter);
5144
		if (db)
5145
			return db;
5146
	}
5147

5148
	for (;;) {
5149
		/*
5150
		 * Find the next CTA Data Block Collection. First iterate all
5151
		 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
5152
		 *
5153
		 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
5154
		 * Extension, it's recommended that DisplayID extensions are
5155
		 * exposed after all of the CTA Extensions.
5156
		 */
5157
		iter->collection = __cea_db_iter_edid_next(iter);
5158
		if (!iter->collection)
5159
			iter->collection = __cea_db_iter_displayid_next(iter);
5160

5161
		if (!iter->collection)
5162
			return NULL;
5163

5164
		db = __cea_db_iter_current_block(iter);
5165
		if (db)
5166
			return db;
5167
	}
5168
}
5169

5170
#define cea_db_iter_for_each(__db, __iter) \
5171
	while (((__db) = __cea_db_iter_next(__iter)))
5172

5173
static void cea_db_iter_end(struct cea_db_iter *iter)
5174
{
5175
	displayid_iter_end(&iter->displayid_iter);
5176
	drm_edid_iter_end(&iter->edid_iter);
5177

5178
	memset(iter, 0, sizeof(*iter));
5179
}
5180

5181
static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
5182
{
5183
	return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
5184
		cea_db_payload_len(db) >= 5;
5185
}
5186

5187
static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
5188
{
5189
	return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
5190
		cea_db_payload_len(db) >= 7;
5191
}
5192

5193
static bool cea_db_is_hdmi_forum_eeodb(const void *db)
5194
{
5195
	return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
5196
		cea_db_payload_len(db) >= 2;
5197
}
5198

5199
static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
5200
{
5201
	return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
5202
		cea_db_payload_len(db) == 21;
5203
}
5204

5205
static bool cea_db_is_vcdb(const struct cea_db *db)
5206
{
5207
	return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
5208
		cea_db_payload_len(db) == 2;
5209
}
5210

5211
static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
5212
{
5213
	return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
5214
		cea_db_payload_len(db) >= 7;
5215
}
5216

5217
static bool cea_db_is_y420cmdb(const struct cea_db *db)
5218
{
5219
	return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
5220
}
5221

5222
static bool cea_db_is_y420vdb(const struct cea_db *db)
5223
{
5224
	return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5225
}
5226

5227
static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
5228
{
5229
	return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5230
		cea_db_payload_len(db) >= 3;
5231
}
5232

5233
/*
5234
 * Get the HF-EEODB override extension block count from EDID.
5235
 *
5236
 * The passed in EDID may be partially read, as long as it has at least two
5237
 * blocks (base block and one extension block) if EDID extension count is > 0.
5238
 *
5239
 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5240
 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5241
 * iterators instead.
5242
 *
5243
 * References:
5244
 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5245
 */
5246
static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5247
{
5248
	const u8 *cta;
5249

5250
	/* No extensions according to base block, no HF-EEODB. */
5251
	if (!edid_extension_block_count(edid))
5252
		return 0;
5253

5254
	/* HF-EEODB is always in the first EDID extension block only */
5255
	cta = edid_extension_block_data(edid, 0);
5256
	if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5257
		return 0;
5258

5259
	/* Need to have the data block collection, and at least 3 bytes. */
5260
	if (cea_db_collection_size(cta) < 3)
5261
		return 0;
5262

5263
	/*
5264
	 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5265
	 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5266
	 * through 6 of Block 1 of the E-EDID.
5267
	 */
5268
	if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5269
		return 0;
5270

5271
	return cta[4 + 2];
5272
}
5273

5274
/*
5275
 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB)
5276
 *
5277
 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB,
5278
 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444
5279
 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can
5280
 * support YCBCR420 output too.
5281
 */
5282
static void parse_cta_y420cmdb(struct drm_connector *connector,
5283
			       const struct cea_db *db, u64 *y420cmdb_map)
5284
{
5285
	struct drm_display_info *info = &connector->display_info;
5286
	int i, map_len = cea_db_payload_len(db) - 1;
5287
	const u8 *data = cea_db_data(db) + 1;
5288
	u64 map = 0;
5289

5290
	if (map_len == 0) {
5291
		/* All CEA modes support ycbcr420 sampling also.*/
5292
		map = U64_MAX;
5293
		goto out;
5294
	}
5295

5296
	/*
5297
	 * This map indicates which of the existing CEA block modes
5298
	 * from VDB can support YCBCR420 output too. So if bit=0 is
5299
	 * set, first mode from VDB can support YCBCR420 output too.
5300
	 * We will parse and keep this map, before parsing VDB itself
5301
	 * to avoid going through the same block again and again.
5302
	 *
5303
	 * Spec is not clear about max possible size of this block.
5304
	 * Clamping max bitmap block size at 8 bytes. Every byte can
5305
	 * address 8 CEA modes, in this way this map can address
5306
	 * 8*8 = first 64 SVDs.
5307
	 */
5308
	if (WARN_ON_ONCE(map_len > 8))
5309
		map_len = 8;
5310

5311
	for (i = 0; i < map_len; i++)
5312
		map |= (u64)data[i] << (8 * i);
5313

5314
out:
5315
	if (map)
5316
		info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5317

5318
	*y420cmdb_map = map;
5319
}
5320

5321
static int add_cea_modes(struct drm_connector *connector,
5322
			 const struct drm_edid *drm_edid)
5323
{
5324
	const struct cea_db *db;
5325
	struct cea_db_iter iter;
5326
	int modes;
5327

5328
	/* CTA VDB block VICs parsed earlier */
5329
	modes = add_cta_vdb_modes(connector);
5330

5331
	cea_db_iter_edid_begin(drm_edid, &iter);
5332
	cea_db_iter_for_each(db, &iter) {
5333
		if (cea_db_is_hdmi_vsdb(db)) {
5334
			modes += do_hdmi_vsdb_modes(connector, (const u8 *)db,
5335
						    cea_db_payload_len(db));
5336
		} else if (cea_db_is_y420vdb(db)) {
5337
			const u8 *vdb420 = cea_db_data(db) + 1;
5338

5339
			/* Add 4:2:0(only) modes present in EDID */
5340
			modes += do_y420vdb_modes(connector, vdb420,
5341
						  cea_db_payload_len(db) - 1);
5342
		}
5343
	}
5344
	cea_db_iter_end(&iter);
5345

5346
	return modes;
5347
}
5348

5349
static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
5350
					  struct drm_display_mode *mode)
5351
{
5352
	const struct drm_display_mode *cea_mode;
5353
	int clock1, clock2, clock;
5354
	u8 vic;
5355
	const char *type;
5356

5357
	/*
5358
	 * allow 5kHz clock difference either way to account for
5359
	 * the 10kHz clock resolution limit of detailed timings.
5360
	 */
5361
	vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5362
	if (drm_valid_cea_vic(vic)) {
5363
		type = "CEA";
5364
		cea_mode = cea_mode_for_vic(vic);
5365
		clock1 = cea_mode->clock;
5366
		clock2 = cea_mode_alternate_clock(cea_mode);
5367
	} else {
5368
		vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5369
		if (drm_valid_hdmi_vic(vic)) {
5370
			type = "HDMI";
5371
			cea_mode = &edid_4k_modes[vic];
5372
			clock1 = cea_mode->clock;
5373
			clock2 = hdmi_mode_alternate_clock(cea_mode);
5374
		} else {
5375
			return;
5376
		}
5377
	}
5378

5379
	/* pick whichever is closest */
5380
	if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5381
		clock = clock1;
5382
	else
5383
		clock = clock2;
5384

5385
	if (mode->clock == clock)
5386
		return;
5387

5388
	drm_dbg_kms(connector->dev,
5389
		    "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5390
		    connector->base.id, connector->name,
5391
		    type, vic, mode->clock, clock);
5392
	mode->clock = clock;
5393
}
5394

5395
static void drm_calculate_luminance_range(struct drm_connector *connector)
5396
{
5397
	const struct hdr_static_metadata *hdr_metadata =
5398
		&connector->display_info.hdr_sink_metadata.hdmi_type1;
5399
	struct drm_luminance_range_info *luminance_range =
5400
		&connector->display_info.luminance_range;
5401
	static const u8 pre_computed_values[] = {
5402
		50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5403
		71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5404
	};
5405
	u32 max_avg, min_cll, max, min, q, r;
5406

5407
	if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5408
		return;
5409

5410
	max_avg = hdr_metadata->max_fall;
5411
	min_cll = hdr_metadata->min_cll;
5412

5413
	/*
5414
	 * From the specification (CTA-861-G), for calculating the maximum
5415
	 * luminance we need to use:
5416
	 *	Luminance = 50*2**(CV/32)
5417
	 * Where CV is a one-byte value.
5418
	 * For calculating this expression we may need float point precision;
5419
	 * to avoid this complexity level, we take advantage that CV is divided
5420
	 * by a constant. From the Euclids division algorithm, we know that CV
5421
	 * can be written as: CV = 32*q + r. Next, we replace CV in the
5422
	 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5423
	 * need to pre-compute the value of r/32. For pre-computing the values
5424
	 * We just used the following Ruby line:
5425
	 *	(0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5426
	 * The results of the above expressions can be verified at
5427
	 * pre_computed_values.
5428
	 */
5429
	q = max_avg >> 5;
5430
	r = max_avg % 32;
5431
	max = (1 << q) * pre_computed_values[r];
5432

5433
	/* min luminance: maxLum * (CV/255)^2 / 100 */
5434
	q = DIV_ROUND_CLOSEST(min_cll, 255);
5435
	min = max * DIV_ROUND_CLOSEST((q * q), 100);
5436

5437
	luminance_range->min_luminance = min;
5438
	luminance_range->max_luminance = max;
5439
}
5440

5441
static uint8_t eotf_supported(const u8 *edid_ext)
5442
{
5443
	return edid_ext[2] &
5444
		(BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5445
		 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
5446
		 BIT(HDMI_EOTF_SMPTE_ST2084) |
5447
		 BIT(HDMI_EOTF_BT_2100_HLG));
5448
}
5449

5450
static uint8_t hdr_metadata_type(const u8 *edid_ext)
5451
{
5452
	return edid_ext[3] &
5453
		BIT(HDMI_STATIC_METADATA_TYPE1);
5454
}
5455

5456
static void
5457
drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5458
{
5459
	struct hdr_static_metadata *hdr_metadata =
5460
		&connector->display_info.hdr_sink_metadata.hdmi_type1;
5461
	u16 len;
5462

5463
	len = cea_db_payload_len(db);
5464

5465
	hdr_metadata->eotf = eotf_supported(db);
5466
	hdr_metadata->metadata_type = hdr_metadata_type(db);
5467

5468
	if (len >= 4)
5469
		hdr_metadata->max_cll = db[4];
5470
	if (len >= 5)
5471
		hdr_metadata->max_fall = db[5];
5472
	if (len >= 6) {
5473
		hdr_metadata->min_cll = db[6];
5474

5475
		/* Calculate only when all values are available */
5476
		drm_calculate_luminance_range(connector);
5477
	}
5478
}
5479

5480
/* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
5481
static void
5482
drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
5483
{
5484
	u8 len = cea_db_payload_len(db);
5485

5486
	if (len >= 6 && (db[6] & (1 << 7)))
5487
		connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
5488

5489
	if (len >= 10 && hdmi_vsdb_latency_present(db)) {
5490
		connector->latency_present[0] = true;
5491
		connector->video_latency[0] = db[9];
5492
		connector->audio_latency[0] = db[10];
5493
	}
5494

5495
	if (len >= 12 && hdmi_vsdb_i_latency_present(db)) {
5496
		connector->latency_present[1] = true;
5497
		connector->video_latency[1] = db[11];
5498
		connector->audio_latency[1] = db[12];
5499
	}
5500

5501
	drm_dbg_kms(connector->dev,
5502
		    "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n",
5503
		    connector->base.id, connector->name,
5504
		    connector->latency_present[0], connector->latency_present[1],
5505
		    connector->video_latency[0], connector->video_latency[1],
5506
		    connector->audio_latency[0], connector->audio_latency[1]);
5507
}
5508

5509
static void
5510
match_identity(const struct detailed_timing *timing, void *data)
5511
{
5512
	struct drm_edid_match_closure *closure = data;
5513
	unsigned int i;
5514
	const char *name = closure->ident->name;
5515
	unsigned int name_len = strlen(name);
5516
	const char *desc = timing->data.other_data.data.str.str;
5517
	unsigned int desc_len = ARRAY_SIZE(timing->data.other_data.data.str.str);
5518

5519
	if (name_len > desc_len ||
5520
	    !(is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME) ||
5521
	      is_display_descriptor(timing, EDID_DETAIL_MONITOR_STRING)))
5522
		return;
5523

5524
	if (strncmp(name, desc, name_len))
5525
		return;
5526

5527
	for (i = name_len; i < desc_len; i++) {
5528
		if (desc[i] == '\n')
5529
			break;
5530
		/* Allow white space before EDID string terminator. */
5531
		if (!isspace(desc[i]))
5532
			return;
5533
	}
5534

5535
	closure->matched = true;
5536
}
5537

5538
/**
5539
 * drm_edid_match - match drm_edid with given identity
5540
 * @drm_edid: EDID
5541
 * @ident: the EDID identity to match with
5542
 *
5543
 * Check if the EDID matches with the given identity.
5544
 *
5545
 * Return: True if the given identity matched with EDID, false otherwise.
5546
 */
5547
bool drm_edid_match(const struct drm_edid *drm_edid,
5548
		    const struct drm_edid_ident *ident)
5549
{
5550
	if (!drm_edid || drm_edid_get_panel_id(drm_edid) != ident->panel_id)
5551
		return false;
5552

5553
	/* Match with name only if it's not NULL. */
5554
	if (ident->name) {
5555
		struct drm_edid_match_closure closure = {
5556
			.ident = ident,
5557
			.matched = false,
5558
		};
5559

5560
		drm_for_each_detailed_block(drm_edid, match_identity, &closure);
5561

5562
		return closure.matched;
5563
	}
5564

5565
	return true;
5566
}
5567
EXPORT_SYMBOL(drm_edid_match);
5568

5569
static void
5570
monitor_name(const struct detailed_timing *timing, void *data)
5571
{
5572
	const char **res = data;
5573

5574
	if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
5575
		return;
5576

5577
	*res = timing->data.other_data.data.str.str;
5578
}
5579

5580
static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
5581
{
5582
	const char *edid_name = NULL;
5583
	int mnl;
5584

5585
	if (!drm_edid || !name)
5586
		return 0;
5587

5588
	drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
5589
	for (mnl = 0; edid_name && mnl < 13; mnl++) {
5590
		if (edid_name[mnl] == 0x0a)
5591
			break;
5592

5593
		name[mnl] = edid_name[mnl];
5594
	}
5595

5596
	return mnl;
5597
}
5598

5599
/**
5600
 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5601
 * @edid: monitor EDID information
5602
 * @name: pointer to a character array to hold the name of the monitor
5603
 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5604
 *
5605
 */
5606
void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
5607
{
5608
	int name_length = 0;
5609

5610
	if (bufsize <= 0)
5611
		return;
5612

5613
	if (edid) {
5614
		char buf[13];
5615
		struct drm_edid drm_edid = {
5616
			.edid = edid,
5617
			.size = edid_size(edid),
5618
		};
5619

5620
		name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5621
		memcpy(name, buf, name_length);
5622
	}
5623

5624
	name[name_length] = '\0';
5625
}
5626
EXPORT_SYMBOL(drm_edid_get_monitor_name);
5627

5628
static void clear_eld(struct drm_connector *connector)
5629
{
5630
	mutex_lock(&connector->eld_mutex);
5631
	memset(connector->eld, 0, sizeof(connector->eld));
5632
	mutex_unlock(&connector->eld_mutex);
5633

5634
	connector->latency_present[0] = false;
5635
	connector->latency_present[1] = false;
5636
	connector->video_latency[0] = 0;
5637
	connector->audio_latency[0] = 0;
5638
	connector->video_latency[1] = 0;
5639
	connector->audio_latency[1] = 0;
5640
}
5641

5642
/*
5643
 * Get 3-byte SAD buffer from struct cea_sad.
5644
 */
5645
void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad)
5646
{
5647
	sad[0] = cta_sad->format << 3 | cta_sad->channels;
5648
	sad[1] = cta_sad->freq;
5649
	sad[2] = cta_sad->byte2;
5650
}
5651

5652
/*
5653
 * Set struct cea_sad from 3-byte SAD buffer.
5654
 */
5655
void drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad)
5656
{
5657
	cta_sad->format = (sad[0] & 0x78) >> 3;
5658
	cta_sad->channels = sad[0] & 0x07;
5659
	cta_sad->freq = sad[1] & 0x7f;
5660
	cta_sad->byte2 = sad[2];
5661
}
5662

5663
/*
5664
 * drm_edid_to_eld - build ELD from EDID
5665
 * @connector: connector corresponding to the HDMI/DP sink
5666
 * @drm_edid: EDID to parse
5667
 *
5668
 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
5669
 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
5670
 */
5671
static void drm_edid_to_eld(struct drm_connector *connector,
5672
			    const struct drm_edid *drm_edid)
5673
{
5674
	const struct drm_display_info *info = &connector->display_info;
5675
	const struct cea_db *db;
5676
	struct cea_db_iter iter;
5677
	uint8_t *eld = connector->eld;
5678
	int total_sad_count = 0;
5679
	int mnl;
5680

5681
	if (!drm_edid)
5682
		return;
5683

5684
	mutex_lock(&connector->eld_mutex);
5685

5686
	mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
5687
	drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n",
5688
		    connector->base.id, connector->name,
5689
		    &eld[DRM_ELD_MONITOR_NAME_STRING]);
5690

5691
	eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
5692
	eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
5693

5694
	eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
5695

5696
	eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5697
	eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5698
	eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5699
	eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
5700

5701
	cea_db_iter_edid_begin(drm_edid, &iter);
5702
	cea_db_iter_for_each(db, &iter) {
5703
		const u8 *data = cea_db_data(db);
5704
		int len = cea_db_payload_len(db);
5705
		int sad_count;
5706

5707
		switch (cea_db_tag(db)) {
5708
		case CTA_DB_AUDIO:
5709
			/* Audio Data Block, contains SADs */
5710
			sad_count = min(len / 3, 15 - total_sad_count);
5711
			if (sad_count >= 1)
5712
				memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5713
				       data, sad_count * 3);
5714
			total_sad_count += sad_count;
5715
			break;
5716
		case CTA_DB_SPEAKER:
5717
			/* Speaker Allocation Data Block */
5718
			if (len >= 1)
5719
				eld[DRM_ELD_SPEAKER] = data[0];
5720
			break;
5721
		case CTA_DB_VENDOR:
5722
			/* HDMI Vendor-Specific Data Block */
5723
			if (cea_db_is_hdmi_vsdb(db))
5724
				drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5725
			break;
5726
		default:
5727
			break;
5728
		}
5729
	}
5730
	cea_db_iter_end(&iter);
5731

5732
	eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
5733

5734
	if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5735
	    connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5736
		eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5737
	else
5738
		eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
5739

5740
	eld[DRM_ELD_BASELINE_ELD_LEN] =
5741
		DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5742

5743
	drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n",
5744
		    connector->base.id, connector->name,
5745
		    drm_eld_size(eld), total_sad_count);
5746

5747
	mutex_unlock(&connector->eld_mutex);
5748
}
5749

5750
static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5751
			    struct cea_sad **psads)
5752
{
5753
	const struct cea_db *db;
5754
	struct cea_db_iter iter;
5755
	int count = 0;
5756

5757
	cea_db_iter_edid_begin(drm_edid, &iter);
5758
	cea_db_iter_for_each(db, &iter) {
5759
		if (cea_db_tag(db) == CTA_DB_AUDIO) {
5760
			struct cea_sad *sads;
5761
			int i;
5762

5763
			count = cea_db_payload_len(db) / 3; /* SAD is 3B */
5764
			sads = kcalloc(count, sizeof(*sads), GFP_KERNEL);
5765
			*psads = sads;
5766
			if (!sads)
5767
				return -ENOMEM;
5768
			for (i = 0; i < count; i++)
5769
				drm_edid_cta_sad_set(&sads[i], &db->data[i * 3]);
5770
			break;
5771
		}
5772
	}
5773
	cea_db_iter_end(&iter);
5774

5775
	DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
5776

5777
	return count;
5778
}
5779

5780
/**
5781
 * drm_edid_to_sad - extracts SADs from EDID
5782
 * @edid: EDID to parse
5783
 * @sads: pointer that will be set to the extracted SADs
5784
 *
5785
 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5786
 *
5787
 * Note: The returned pointer needs to be freed using kfree().
5788
 *
5789
 * Return: The number of found SADs or negative number on error.
5790
 */
5791
int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5792
{
5793
	struct drm_edid drm_edid;
5794

5795
	return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5796
}
5797
EXPORT_SYMBOL(drm_edid_to_sad);
5798

5799
static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5800
					   u8 **sadb)
5801
{
5802
	const struct cea_db *db;
5803
	struct cea_db_iter iter;
5804
	int count = 0;
5805

5806
	cea_db_iter_edid_begin(drm_edid, &iter);
5807
	cea_db_iter_for_each(db, &iter) {
5808
		if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5809
		    cea_db_payload_len(db) == 3) {
5810
			*sadb = kmemdup(db->data, cea_db_payload_len(db),
5811
					GFP_KERNEL);
5812
			if (!*sadb)
5813
				return -ENOMEM;
5814
			count = cea_db_payload_len(db);
5815
			break;
5816
		}
5817
	}
5818
	cea_db_iter_end(&iter);
5819

5820
	DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
5821

5822
	return count;
5823
}
5824

5825
/**
5826
 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5827
 * @edid: EDID to parse
5828
 * @sadb: pointer to the speaker block
5829
 *
5830
 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5831
 *
5832
 * Note: The returned pointer needs to be freed using kfree().
5833
 *
5834
 * Return: The number of found Speaker Allocation Blocks or negative number on
5835
 * error.
5836
 */
5837
int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5838
{
5839
	struct drm_edid drm_edid;
5840

5841
	return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5842
					       sadb);
5843
}
5844
EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5845

5846
/**
5847
 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
5848
 * @connector: connector associated with the HDMI/DP sink
5849
 * @mode: the display mode
5850
 *
5851
 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5852
 * the sink doesn't support audio or video.
5853
 */
5854
int drm_av_sync_delay(struct drm_connector *connector,
5855
		      const struct drm_display_mode *mode)
5856
{
5857
	int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5858
	int a, v;
5859

5860
	if (!connector->latency_present[0])
5861
		return 0;
5862
	if (!connector->latency_present[1])
5863
		i = 0;
5864

5865
	a = connector->audio_latency[i];
5866
	v = connector->video_latency[i];
5867

5868
	/*
5869
	 * HDMI/DP sink doesn't support audio or video?
5870
	 */
5871
	if (a == 255 || v == 255)
5872
		return 0;
5873

5874
	/*
5875
	 * Convert raw EDID values to millisecond.
5876
	 * Treat unknown latency as 0ms.
5877
	 */
5878
	if (a)
5879
		a = min(2 * (a - 1), 500);
5880
	if (v)
5881
		v = min(2 * (v - 1), 500);
5882

5883
	return max(v - a, 0);
5884
}
5885
EXPORT_SYMBOL(drm_av_sync_delay);
5886

5887
static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
5888
{
5889
	const struct cea_db *db;
5890
	struct cea_db_iter iter;
5891
	bool hdmi = false;
5892

5893
	/*
5894
	 * Because HDMI identifier is in Vendor Specific Block,
5895
	 * search it from all data blocks of CEA extension.
5896
	 */
5897
	cea_db_iter_edid_begin(drm_edid, &iter);
5898
	cea_db_iter_for_each(db, &iter) {
5899
		if (cea_db_is_hdmi_vsdb(db)) {
5900
			hdmi = true;
5901
			break;
5902
		}
5903
	}
5904
	cea_db_iter_end(&iter);
5905

5906
	return hdmi;
5907
}
5908

5909
/**
5910
 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5911
 * @edid: monitor EDID information
5912
 *
5913
 * Parse the CEA extension according to CEA-861-B.
5914
 *
5915
 * Drivers that have added the modes parsed from EDID to drm_display_info
5916
 * should use &drm_display_info.is_hdmi instead of calling this function.
5917
 *
5918
 * Return: True if the monitor is HDMI, false if not or unknown.
5919
 */
5920
bool drm_detect_hdmi_monitor(const struct edid *edid)
5921
{
5922
	struct drm_edid drm_edid;
5923

5924
	return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5925
}
5926
EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5927

5928
static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
5929
{
5930
	struct drm_edid_iter edid_iter;
5931
	const struct cea_db *db;
5932
	struct cea_db_iter iter;
5933
	const u8 *edid_ext;
5934
	bool has_audio = false;
5935

5936
	drm_edid_iter_begin(drm_edid, &edid_iter);
5937
	drm_edid_iter_for_each(edid_ext, &edid_iter) {
5938
		if (edid_ext[0] == CEA_EXT) {
5939
			has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5940
			if (has_audio)
5941
				break;
5942
		}
5943
	}
5944
	drm_edid_iter_end(&edid_iter);
5945

5946
	if (has_audio) {
5947
		DRM_DEBUG_KMS("Monitor has basic audio support\n");
5948
		goto end;
5949
	}
5950

5951
	cea_db_iter_edid_begin(drm_edid, &iter);
5952
	cea_db_iter_for_each(db, &iter) {
5953
		if (cea_db_tag(db) == CTA_DB_AUDIO) {
5954
			const u8 *data = cea_db_data(db);
5955
			int i;
5956

5957
			for (i = 0; i < cea_db_payload_len(db); i += 3)
5958
				DRM_DEBUG_KMS("CEA audio format %d\n",
5959
					      (data[i] >> 3) & 0xf);
5960
			has_audio = true;
5961
			break;
5962
		}
5963
	}
5964
	cea_db_iter_end(&iter);
5965

5966
end:
5967
	return has_audio;
5968
}
5969

5970
/**
5971
 * drm_detect_monitor_audio - check monitor audio capability
5972
 * @edid: EDID block to scan
5973
 *
5974
 * Monitor should have CEA extension block.
5975
 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5976
 * audio' only. If there is any audio extension block and supported
5977
 * audio format, assume at least 'basic audio' support, even if 'basic
5978
 * audio' is not defined in EDID.
5979
 *
5980
 * Return: True if the monitor supports audio, false otherwise.
5981
 */
5982
bool drm_detect_monitor_audio(const struct edid *edid)
5983
{
5984
	struct drm_edid drm_edid;
5985

5986
	return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5987
}
5988
EXPORT_SYMBOL(drm_detect_monitor_audio);
5989

5990

5991
/**
5992
 * drm_default_rgb_quant_range - default RGB quantization range
5993
 * @mode: display mode
5994
 *
5995
 * Determine the default RGB quantization range for the mode,
5996
 * as specified in CEA-861.
5997
 *
5998
 * Return: The default RGB quantization range for the mode
5999
 */
6000
enum hdmi_quantization_range
6001
drm_default_rgb_quant_range(const struct drm_display_mode *mode)
6002
{
6003
	/* All CEA modes other than VIC 1 use limited quantization range. */
6004
	return drm_match_cea_mode(mode) > 1 ?
6005
		HDMI_QUANTIZATION_RANGE_LIMITED :
6006
		HDMI_QUANTIZATION_RANGE_FULL;
6007
}
6008
EXPORT_SYMBOL(drm_default_rgb_quant_range);
6009

6010
/* CTA-861 Video Data Block (CTA VDB) */
6011
static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db)
6012
{
6013
	struct drm_display_info *info = &connector->display_info;
6014
	int i, vic_index, len = cea_db_payload_len(db);
6015
	const u8 *svds = cea_db_data(db);
6016
	u8 *vics;
6017

6018
	if (!len)
6019
		return;
6020

6021
	/* Gracefully handle multiple VDBs, however unlikely that is */
6022
	vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL);
6023
	if (!vics)
6024
		return;
6025

6026
	vic_index = info->vics_len;
6027
	info->vics_len += len;
6028
	info->vics = vics;
6029

6030
	for (i = 0; i < len; i++) {
6031
		u8 vic = svd_to_vic(svds[i]);
6032

6033
		if (!drm_valid_cea_vic(vic))
6034
			vic = 0;
6035

6036
		info->vics[vic_index++] = vic;
6037
	}
6038
}
6039

6040
/*
6041
 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB.
6042
 *
6043
 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed
6044
 * using the VICs themselves.
6045
 */
6046
static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map)
6047
{
6048
	struct drm_display_info *info = &connector->display_info;
6049
	struct drm_hdmi_info *hdmi = &info->hdmi;
6050
	int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map));
6051

6052
	for (i = 0; i < len; i++) {
6053
		u8 vic = info->vics[i];
6054

6055
		if (vic && y420cmdb_map & BIT_ULL(i))
6056
			bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
6057
	}
6058
}
6059

6060
static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic)
6061
{
6062
	const struct drm_display_info *info = &connector->display_info;
6063
	int i;
6064

6065
	if (!vic || !info->vics)
6066
		return false;
6067

6068
	for (i = 0; i < info->vics_len; i++) {
6069
		if (info->vics[i] == vic)
6070
			return true;
6071
	}
6072

6073
	return false;
6074
}
6075

6076
/* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */
6077
static void parse_cta_y420vdb(struct drm_connector *connector,
6078
			      const struct cea_db *db)
6079
{
6080
	struct drm_display_info *info = &connector->display_info;
6081
	struct drm_hdmi_info *hdmi = &info->hdmi;
6082
	const u8 *svds = cea_db_data(db) + 1;
6083
	int i;
6084

6085
	for (i = 0; i < cea_db_payload_len(db) - 1; i++) {
6086
		u8 vic = svd_to_vic(svds[i]);
6087

6088
		if (!drm_valid_cea_vic(vic))
6089
			continue;
6090

6091
		bitmap_set(hdmi->y420_vdb_modes, vic, 1);
6092
		info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
6093
	}
6094
}
6095

6096
static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
6097
{
6098
	struct drm_display_info *info = &connector->display_info;
6099

6100
	drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n",
6101
		    connector->base.id, connector->name, db[2]);
6102

6103
	if (db[2] & EDID_CEA_VCDB_QS)
6104
		info->rgb_quant_range_selectable = true;
6105
}
6106

6107
static
6108
void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
6109
{
6110
	switch (max_frl_rate) {
6111
	case 1:
6112
		*max_lanes = 3;
6113
		*max_rate_per_lane = 3;
6114
		break;
6115
	case 2:
6116
		*max_lanes = 3;
6117
		*max_rate_per_lane = 6;
6118
		break;
6119
	case 3:
6120
		*max_lanes = 4;
6121
		*max_rate_per_lane = 6;
6122
		break;
6123
	case 4:
6124
		*max_lanes = 4;
6125
		*max_rate_per_lane = 8;
6126
		break;
6127
	case 5:
6128
		*max_lanes = 4;
6129
		*max_rate_per_lane = 10;
6130
		break;
6131
	case 6:
6132
		*max_lanes = 4;
6133
		*max_rate_per_lane = 12;
6134
		break;
6135
	case 0:
6136
	default:
6137
		*max_lanes = 0;
6138
		*max_rate_per_lane = 0;
6139
	}
6140
}
6141

6142
static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
6143
					       const u8 *db)
6144
{
6145
	u8 dc_mask;
6146
	struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
6147

6148
	dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
6149
	hdmi->y420_dc_modes = dc_mask;
6150
}
6151

6152
static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
6153
			       const u8 *hf_scds)
6154
{
6155
	hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
6156

6157
	if (!hdmi_dsc->v_1p2)
6158
		return;
6159

6160
	hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
6161
	hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
6162

6163
	if (hf_scds[11] & DRM_EDID_DSC_16BPC)
6164
		hdmi_dsc->bpc_supported = 16;
6165
	else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
6166
		hdmi_dsc->bpc_supported = 12;
6167
	else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
6168
		hdmi_dsc->bpc_supported = 10;
6169
	else
6170
		/* Supports min 8 BPC if DSC 1.2 is supported*/
6171
		hdmi_dsc->bpc_supported = 8;
6172

6173
	if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) {
6174
		u8 dsc_max_slices;
6175
		u8 dsc_max_frl_rate;
6176

6177
		dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
6178
		drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
6179
				     &hdmi_dsc->max_frl_rate_per_lane);
6180

6181
		dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
6182

6183
		switch (dsc_max_slices) {
6184
		case 1:
6185
			hdmi_dsc->max_slices = 1;
6186
			hdmi_dsc->clk_per_slice = 340;
6187
			break;
6188
		case 2:
6189
			hdmi_dsc->max_slices = 2;
6190
			hdmi_dsc->clk_per_slice = 340;
6191
			break;
6192
		case 3:
6193
			hdmi_dsc->max_slices = 4;
6194
			hdmi_dsc->clk_per_slice = 340;
6195
			break;
6196
		case 4:
6197
			hdmi_dsc->max_slices = 8;
6198
			hdmi_dsc->clk_per_slice = 340;
6199
			break;
6200
		case 5:
6201
			hdmi_dsc->max_slices = 8;
6202
			hdmi_dsc->clk_per_slice = 400;
6203
			break;
6204
		case 6:
6205
			hdmi_dsc->max_slices = 12;
6206
			hdmi_dsc->clk_per_slice = 400;
6207
			break;
6208
		case 7:
6209
			hdmi_dsc->max_slices = 16;
6210
			hdmi_dsc->clk_per_slice = 400;
6211
			break;
6212
		case 0:
6213
		default:
6214
			hdmi_dsc->max_slices = 0;
6215
			hdmi_dsc->clk_per_slice = 0;
6216
		}
6217
	}
6218

6219
	if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13])
6220
		hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
6221
}
6222

6223
/* Sink Capability Data Structure */
6224
static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
6225
				      const u8 *hf_scds)
6226
{
6227
	struct drm_display_info *info = &connector->display_info;
6228
	struct drm_hdmi_info *hdmi = &info->hdmi;
6229
	struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
6230
	int max_tmds_clock = 0;
6231
	u8 max_frl_rate = 0;
6232
	bool dsc_support = false;
6233

6234
	info->has_hdmi_infoframe = true;
6235

6236
	if (hf_scds[6] & 0x80) {
6237
		hdmi->scdc.supported = true;
6238
		if (hf_scds[6] & 0x40)
6239
			hdmi->scdc.read_request = true;
6240
	}
6241

6242
	/*
6243
	 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
6244
	 * And as per the spec, three factors confirm this:
6245
	 * * Availability of a HF-VSDB block in EDID (check)
6246
	 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
6247
	 * * SCDC support available (let's check)
6248
	 * Lets check it out.
6249
	 */
6250

6251
	if (hf_scds[5]) {
6252
		struct drm_scdc *scdc = &hdmi->scdc;
6253

6254
		/* max clock is 5000 KHz times block value */
6255
		max_tmds_clock = hf_scds[5] * 5000;
6256

6257
		if (max_tmds_clock > 340000) {
6258
			info->max_tmds_clock = max_tmds_clock;
6259
		}
6260

6261
		if (scdc->supported) {
6262
			scdc->scrambling.supported = true;
6263

6264
			/* Few sinks support scrambling for clocks < 340M */
6265
			if ((hf_scds[6] & 0x8))
6266
				scdc->scrambling.low_rates = true;
6267
		}
6268
	}
6269

6270
	if (hf_scds[7]) {
6271
		max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
6272
		drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
6273
				     &hdmi->max_frl_rate_per_lane);
6274
	}
6275

6276
	drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
6277

6278
	if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
6279
		drm_parse_dsc_info(hdmi_dsc, hf_scds);
6280
		dsc_support = true;
6281
	}
6282

6283
	drm_dbg_kms(connector->dev,
6284
		    "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
6285
		    connector->base.id, connector->name,
6286
		    max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
6287
}
6288

6289
static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
6290
					   const u8 *hdmi)
6291
{
6292
	struct drm_display_info *info = &connector->display_info;
6293
	unsigned int dc_bpc = 0;
6294

6295
	/* HDMI supports at least 8 bpc */
6296
	info->bpc = 8;
6297

6298
	if (cea_db_payload_len(hdmi) < 6)
6299
		return;
6300

6301
	if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
6302
		dc_bpc = 10;
6303
		info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
6304
		drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n",
6305
			    connector->base.id, connector->name);
6306
	}
6307

6308
	if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
6309
		dc_bpc = 12;
6310
		info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
6311
		drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n",
6312
			    connector->base.id, connector->name);
6313
	}
6314

6315
	if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
6316
		dc_bpc = 16;
6317
		info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
6318
		drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n",
6319
			    connector->base.id, connector->name);
6320
	}
6321

6322
	if (dc_bpc == 0) {
6323
		drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n",
6324
			    connector->base.id, connector->name);
6325
		return;
6326
	}
6327

6328
	drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n",
6329
		    connector->base.id, connector->name, dc_bpc);
6330
	info->bpc = dc_bpc;
6331

6332
	/* YCRCB444 is optional according to spec. */
6333
	if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
6334
		info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
6335
		drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n",
6336
			    connector->base.id, connector->name);
6337
	}
6338

6339
	/*
6340
	 * Spec says that if any deep color mode is supported at all,
6341
	 * then deep color 36 bit must be supported.
6342
	 */
6343
	if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
6344
		drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n",
6345
			    connector->base.id, connector->name);
6346
	}
6347
}
6348

6349
/* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
6350
static void
6351
drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
6352
{
6353
	struct drm_display_info *info = &connector->display_info;
6354
	u8 len = cea_db_payload_len(db);
6355

6356
	info->is_hdmi = true;
6357

6358
	info->source_physical_address = (db[4] << 8) | db[5];
6359

6360
	if (len >= 6)
6361
		info->dvi_dual = db[6] & 1;
6362
	if (len >= 7)
6363
		info->max_tmds_clock = db[7] * 5000;
6364

6365
	/*
6366
	 * Try to infer whether the sink supports HDMI infoframes.
6367
	 *
6368
	 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink
6369
	 * supports infoframes if HDMI_Video_present is set.
6370
	 */
6371
	if (len >= 8 && db[8] & BIT(5))
6372
		info->has_hdmi_infoframe = true;
6373

6374
	drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n",
6375
		    connector->base.id, connector->name,
6376
		    info->dvi_dual, info->max_tmds_clock);
6377

6378
	drm_parse_hdmi_deep_color_info(connector, db);
6379
}
6380

6381
/*
6382
 * See EDID extension for head-mounted and specialized monitors, specified at:
6383
 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
6384
 */
6385
static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
6386
				     const u8 *db)
6387
{
6388
	struct drm_display_info *info = &connector->display_info;
6389
	u8 version = db[4];
6390
	bool desktop_usage = db[5] & BIT(6);
6391

6392
	/* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
6393
	if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
6394
		info->non_desktop = true;
6395

6396
	drm_dbg_kms(connector->dev,
6397
		    "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n",
6398
		    connector->base.id, connector->name, version, db[5]);
6399
}
6400

6401
static void drm_parse_cea_ext(struct drm_connector *connector,
6402
			      const struct drm_edid *drm_edid)
6403
{
6404
	struct drm_display_info *info = &connector->display_info;
6405
	struct drm_edid_iter edid_iter;
6406
	const struct cea_db *db;
6407
	struct cea_db_iter iter;
6408
	const u8 *edid_ext;
6409
	u64 y420cmdb_map = 0;
6410

6411
	drm_edid_iter_begin(drm_edid, &edid_iter);
6412
	drm_edid_iter_for_each(edid_ext, &edid_iter) {
6413
		if (edid_ext[0] != CEA_EXT)
6414
			continue;
6415

6416
		if (!info->cea_rev)
6417
			info->cea_rev = edid_ext[1];
6418

6419
		if (info->cea_rev != edid_ext[1])
6420
			drm_dbg_kms(connector->dev,
6421
				    "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n",
6422
				    connector->base.id, connector->name,
6423
				    info->cea_rev, edid_ext[1]);
6424

6425
		/* The existence of a CTA extension should imply RGB support */
6426
		info->color_formats = DRM_COLOR_FORMAT_RGB444;
6427
		if (edid_ext[3] & EDID_CEA_YCRCB444)
6428
			info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6429
		if (edid_ext[3] & EDID_CEA_YCRCB422)
6430
			info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6431
		if (edid_ext[3] & EDID_BASIC_AUDIO)
6432
			info->has_audio = true;
6433

6434
	}
6435
	drm_edid_iter_end(&edid_iter);
6436

6437
	cea_db_iter_edid_begin(drm_edid, &iter);
6438
	cea_db_iter_for_each(db, &iter) {
6439
		/* FIXME: convert parsers to use struct cea_db */
6440
		const u8 *data = (const u8 *)db;
6441

6442
		if (cea_db_is_hdmi_vsdb(db))
6443
			drm_parse_hdmi_vsdb_video(connector, data);
6444
		else if (cea_db_is_hdmi_forum_vsdb(db) ||
6445
			 cea_db_is_hdmi_forum_scdb(db))
6446
			drm_parse_hdmi_forum_scds(connector, data);
6447
		else if (cea_db_is_microsoft_vsdb(db))
6448
			drm_parse_microsoft_vsdb(connector, data);
6449
		else if (cea_db_is_y420cmdb(db))
6450
			parse_cta_y420cmdb(connector, db, &y420cmdb_map);
6451
		else if (cea_db_is_y420vdb(db))
6452
			parse_cta_y420vdb(connector, db);
6453
		else if (cea_db_is_vcdb(db))
6454
			drm_parse_vcdb(connector, data);
6455
		else if (cea_db_is_hdmi_hdr_metadata_block(db))
6456
			drm_parse_hdr_metadata_block(connector, data);
6457
		else if (cea_db_tag(db) == CTA_DB_VIDEO)
6458
			parse_cta_vdb(connector, db);
6459
		else if (cea_db_tag(db) == CTA_DB_AUDIO)
6460
			info->has_audio = true;
6461
	}
6462
	cea_db_iter_end(&iter);
6463

6464
	if (y420cmdb_map)
6465
		update_cta_y420cmdb(connector, y420cmdb_map);
6466
}
6467

6468
static
6469
void get_monitor_range(const struct detailed_timing *timing, void *c)
6470
{
6471
	struct detailed_mode_closure *closure = c;
6472
	struct drm_display_info *info = &closure->connector->display_info;
6473
	struct drm_monitor_range_info *monitor_range = &info->monitor_range;
6474
	const struct detailed_non_pixel *data = &timing->data.other_data;
6475
	const struct detailed_data_monitor_range *range = &data->data.range;
6476
	const struct edid *edid = closure->drm_edid->edid;
6477

6478
	if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
6479
		return;
6480

6481
	/*
6482
	 * These limits are used to determine the VRR refresh
6483
	 * rate range. Only the "range limits only" variant
6484
	 * of the range descriptor seems to guarantee that
6485
	 * any and all timings are accepted by the sink, as
6486
	 * opposed to just timings conforming to the indicated
6487
	 * formula (GTF/GTF2/CVT). Thus other variants of the
6488
	 * range descriptor are not accepted here.
6489
	 */
6490
	if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6491
		return;
6492

6493
	monitor_range->min_vfreq = range->min_vfreq;
6494
	monitor_range->max_vfreq = range->max_vfreq;
6495

6496
	if (edid->revision >= 4) {
6497
		if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6498
			monitor_range->min_vfreq += 255;
6499
		if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6500
			monitor_range->max_vfreq += 255;
6501
	}
6502
}
6503

6504
static void drm_get_monitor_range(struct drm_connector *connector,
6505
				  const struct drm_edid *drm_edid)
6506
{
6507
	const struct drm_display_info *info = &connector->display_info;
6508
	struct detailed_mode_closure closure = {
6509
		.connector = connector,
6510
		.drm_edid = drm_edid,
6511
	};
6512

6513
	if (drm_edid->edid->revision < 4)
6514
		return;
6515

6516
	if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
6517
		return;
6518

6519
	drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
6520

6521
	drm_dbg_kms(connector->dev,
6522
		    "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6523
		    connector->base.id, connector->name,
6524
		    info->monitor_range.min_vfreq, info->monitor_range.max_vfreq);
6525
}
6526

6527
static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6528
				    const struct displayid_block *block)
6529
{
6530
	struct displayid_vesa_vendor_specific_block *vesa =
6531
		(struct displayid_vesa_vendor_specific_block *)block;
6532
	struct drm_display_info *info = &connector->display_info;
6533

6534
	if (block->num_bytes < 3) {
6535
		drm_dbg_kms(connector->dev,
6536
			    "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n",
6537
			    connector->base.id, connector->name, block->num_bytes);
6538
		return;
6539
	}
6540

6541
	if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6542
		return;
6543

6544
	if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
6545
		drm_dbg_kms(connector->dev,
6546
			    "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
6547
			    connector->base.id, connector->name);
6548
		return;
6549
	}
6550

6551
	switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6552
	default:
6553
		drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
6554
			    connector->base.id, connector->name);
6555
		fallthrough;
6556
	case 0:
6557
		info->mso_stream_count = 0;
6558
		break;
6559
	case 1:
6560
		info->mso_stream_count = 2; /* 2 or 4 links */
6561
		break;
6562
	case 2:
6563
		info->mso_stream_count = 4; /* 4 links */
6564
		break;
6565
	}
6566

6567
	if (!info->mso_stream_count) {
6568
		info->mso_pixel_overlap = 0;
6569
		return;
6570
	}
6571

6572
	info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6573
	if (info->mso_pixel_overlap > 8) {
6574
		drm_dbg_kms(connector->dev,
6575
			    "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
6576
			    connector->base.id, connector->name,
6577
			    info->mso_pixel_overlap);
6578
		info->mso_pixel_overlap = 8;
6579
	}
6580

6581
	drm_dbg_kms(connector->dev,
6582
		    "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
6583
		    connector->base.id, connector->name,
6584
		    info->mso_stream_count, info->mso_pixel_overlap);
6585
}
6586

6587
static void drm_update_mso(struct drm_connector *connector,
6588
			   const struct drm_edid *drm_edid)
6589
{
6590
	const struct displayid_block *block;
6591
	struct displayid_iter iter;
6592

6593
	displayid_iter_edid_begin(drm_edid, &iter);
6594
	displayid_iter_for_each(block, &iter) {
6595
		if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6596
			drm_parse_vesa_mso_data(connector, block);
6597
	}
6598
	displayid_iter_end(&iter);
6599
}
6600

6601
/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6602
 * all of the values which would have been set from EDID
6603
 */
6604
static void drm_reset_display_info(struct drm_connector *connector)
6605
{
6606
	struct drm_display_info *info = &connector->display_info;
6607

6608
	info->width_mm = 0;
6609
	info->height_mm = 0;
6610

6611
	info->bpc = 0;
6612
	info->color_formats = 0;
6613
	info->cea_rev = 0;
6614
	info->max_tmds_clock = 0;
6615
	info->dvi_dual = false;
6616
	info->is_hdmi = false;
6617
	info->has_audio = false;
6618
	info->has_hdmi_infoframe = false;
6619
	info->rgb_quant_range_selectable = false;
6620
	memset(&info->hdmi, 0, sizeof(info->hdmi));
6621
	memset(&info->hdr_sink_metadata, 0, sizeof(info->hdr_sink_metadata));
6622

6623
	info->edid_hdmi_rgb444_dc_modes = 0;
6624
	info->edid_hdmi_ycbcr444_dc_modes = 0;
6625

6626
	info->non_desktop = 0;
6627
	memset(&info->monitor_range, 0, sizeof(info->monitor_range));
6628
	memset(&info->luminance_range, 0, sizeof(info->luminance_range));
6629

6630
	info->mso_stream_count = 0;
6631
	info->mso_pixel_overlap = 0;
6632
	info->max_dsc_bpp = 0;
6633

6634
	kfree(info->vics);
6635
	info->vics = NULL;
6636
	info->vics_len = 0;
6637

6638
	info->quirks = 0;
6639

6640
	info->source_physical_address = CEC_PHYS_ADDR_INVALID;
6641
}
6642

6643
static void update_displayid_info(struct drm_connector *connector,
6644
				  const struct drm_edid *drm_edid)
6645
{
6646
	struct drm_display_info *info = &connector->display_info;
6647
	const struct displayid_block *block;
6648
	struct displayid_iter iter;
6649

6650
	displayid_iter_edid_begin(drm_edid, &iter);
6651
	displayid_iter_for_each(block, &iter) {
6652
		drm_dbg_kms(connector->dev,
6653
			    "[CONNECTOR:%d:%s] DisplayID extension version 0x%02x, primary use 0x%02x\n",
6654
			    connector->base.id, connector->name,
6655
			    displayid_version(&iter),
6656
			    displayid_primary_use(&iter));
6657
		if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
6658
		    (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR ||
6659
		     displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR))
6660
			info->non_desktop = true;
6661

6662
		/*
6663
		 * We're only interested in the base section here, no need to
6664
		 * iterate further.
6665
		 */
6666
		break;
6667
	}
6668
	displayid_iter_end(&iter);
6669
}
6670

6671
static void update_display_info(struct drm_connector *connector,
6672
				const struct drm_edid *drm_edid)
6673
{
6674
	struct drm_display_info *info = &connector->display_info;
6675
	const struct edid *edid;
6676

6677
	drm_reset_display_info(connector);
6678
	clear_eld(connector);
6679

6680
	if (!drm_edid)
6681
		return;
6682

6683
	edid = drm_edid->edid;
6684

6685
	info->quirks = edid_get_quirks(drm_edid);
6686

6687
	info->width_mm = edid->width_cm * 10;
6688
	info->height_mm = edid->height_cm * 10;
6689

6690
	drm_get_monitor_range(connector, drm_edid);
6691

6692
	if (edid->revision < 3)
6693
		goto out;
6694

6695
	if (!drm_edid_is_digital(drm_edid))
6696
		goto out;
6697

6698
	info->color_formats |= DRM_COLOR_FORMAT_RGB444;
6699
	drm_parse_cea_ext(connector, drm_edid);
6700

6701
	update_displayid_info(connector, drm_edid);
6702

6703
	/*
6704
	 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6705
	 *
6706
	 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6707
	 * tells us to assume 8 bpc color depth if the EDID doesn't have
6708
	 * extensions which tell otherwise.
6709
	 */
6710
	if (info->bpc == 0 && edid->revision == 3 &&
6711
	    edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
6712
		info->bpc = 8;
6713
		drm_dbg_kms(connector->dev,
6714
			    "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n",
6715
			    connector->base.id, connector->name, info->bpc);
6716
	}
6717

6718
	/* Only defined for 1.4 with digital displays */
6719
	if (edid->revision < 4)
6720
		goto out;
6721

6722
	switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6723
	case DRM_EDID_DIGITAL_DEPTH_6:
6724
		info->bpc = 6;
6725
		break;
6726
	case DRM_EDID_DIGITAL_DEPTH_8:
6727
		info->bpc = 8;
6728
		break;
6729
	case DRM_EDID_DIGITAL_DEPTH_10:
6730
		info->bpc = 10;
6731
		break;
6732
	case DRM_EDID_DIGITAL_DEPTH_12:
6733
		info->bpc = 12;
6734
		break;
6735
	case DRM_EDID_DIGITAL_DEPTH_14:
6736
		info->bpc = 14;
6737
		break;
6738
	case DRM_EDID_DIGITAL_DEPTH_16:
6739
		info->bpc = 16;
6740
		break;
6741
	case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6742
	default:
6743
		info->bpc = 0;
6744
		break;
6745
	}
6746

6747
	drm_dbg_kms(connector->dev,
6748
		    "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6749
		    connector->base.id, connector->name, info->bpc);
6750

6751
	if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
6752
		info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6753
	if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
6754
		info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6755

6756
	drm_update_mso(connector, drm_edid);
6757

6758
out:
6759
	if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_NON_DESKTOP)) {
6760
		drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n",
6761
			    connector->base.id, connector->name,
6762
			    info->non_desktop ? " (redundant quirk)" : "");
6763
		info->non_desktop = true;
6764
	}
6765

6766
	if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_CAP_DSC_15BPP))
6767
		info->max_dsc_bpp = 15;
6768

6769
	if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_FORCE_6BPC))
6770
		info->bpc = 6;
6771

6772
	if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_FORCE_8BPC))
6773
		info->bpc = 8;
6774

6775
	if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_FORCE_10BPC))
6776
		info->bpc = 10;
6777

6778
	if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_FORCE_12BPC))
6779
		info->bpc = 12;
6780

6781
	/* Depends on info->cea_rev set by drm_parse_cea_ext() above */
6782
	drm_edid_to_eld(connector, drm_edid);
6783
}
6784

6785
static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
6786
							    const struct displayid_detailed_timings_1 *timings,
6787
							    bool type_7)
6788
{
6789
	struct drm_display_mode *mode;
6790
	unsigned int pixel_clock = (timings->pixel_clock[0] |
6791
				    (timings->pixel_clock[1] << 8) |
6792
				    (timings->pixel_clock[2] << 16)) + 1;
6793
	unsigned int hactive = le16_to_cpu(timings->hactive) + 1;
6794
	unsigned int hblank = le16_to_cpu(timings->hblank) + 1;
6795
	unsigned int hsync = (le16_to_cpu(timings->hsync) & 0x7fff) + 1;
6796
	unsigned int hsync_width = le16_to_cpu(timings->hsw) + 1;
6797
	unsigned int vactive = le16_to_cpu(timings->vactive) + 1;
6798
	unsigned int vblank = le16_to_cpu(timings->vblank) + 1;
6799
	unsigned int vsync = (le16_to_cpu(timings->vsync) & 0x7fff) + 1;
6800
	unsigned int vsync_width = le16_to_cpu(timings->vsw) + 1;
6801
	bool hsync_positive = le16_to_cpu(timings->hsync) & (1 << 15);
6802
	bool vsync_positive = le16_to_cpu(timings->vsync) & (1 << 15);
6803

6804
	mode = drm_mode_create(dev);
6805
	if (!mode)
6806
		return NULL;
6807

6808
	/* resolution is kHz for type VII, and 10 kHz for type I */
6809
	mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
6810
	mode->hdisplay = hactive;
6811
	mode->hsync_start = mode->hdisplay + hsync;
6812
	mode->hsync_end = mode->hsync_start + hsync_width;
6813
	mode->htotal = mode->hdisplay + hblank;
6814

6815
	mode->vdisplay = vactive;
6816
	mode->vsync_start = mode->vdisplay + vsync;
6817
	mode->vsync_end = mode->vsync_start + vsync_width;
6818
	mode->vtotal = mode->vdisplay + vblank;
6819

6820
	mode->flags = 0;
6821
	mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6822
	mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6823
	mode->type = DRM_MODE_TYPE_DRIVER;
6824

6825
	if (timings->flags & 0x80)
6826
		mode->type |= DRM_MODE_TYPE_PREFERRED;
6827
	drm_mode_set_name(mode);
6828

6829
	return mode;
6830
}
6831

6832
static int add_displayid_detailed_1_modes(struct drm_connector *connector,
6833
					  const struct displayid_block *block)
6834
{
6835
	struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6836
	int i;
6837
	int num_timings;
6838
	struct drm_display_mode *newmode;
6839
	int num_modes = 0;
6840
	bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
6841
	/* blocks must be multiple of 20 bytes length */
6842
	if (block->num_bytes % 20)
6843
		return 0;
6844

6845
	num_timings = block->num_bytes / 20;
6846
	for (i = 0; i < num_timings; i++) {
6847
		struct displayid_detailed_timings_1 *timings = &det->timings[i];
6848

6849
		newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
6850
		if (!newmode)
6851
			continue;
6852

6853
		drm_mode_probed_add(connector, newmode);
6854
		num_modes++;
6855
	}
6856
	return num_modes;
6857
}
6858

6859
static struct drm_display_mode *drm_mode_displayid_formula(struct drm_device *dev,
6860
							   const struct displayid_formula_timings_9 *timings,
6861
							   bool type_10)
6862
{
6863
	struct drm_display_mode *mode;
6864
	u16 hactive = le16_to_cpu(timings->hactive) + 1;
6865
	u16 vactive = le16_to_cpu(timings->vactive) + 1;
6866
	u8 timing_formula = timings->flags & 0x7;
6867

6868
	/* TODO: support RB-v2 & RB-v3 */
6869
	if (timing_formula > 1)
6870
		return NULL;
6871

6872
	/* TODO: support video-optimized refresh rate */
6873
	if (timings->flags & (1 << 4))
6874
		drm_dbg_kms(dev, "Fractional vrefresh is not implemented, proceeding with non-video-optimized refresh rate");
6875

6876
	mode = drm_cvt_mode(dev, hactive, vactive, timings->vrefresh + 1, timing_formula == 1, false, false);
6877
	if (!mode)
6878
		return NULL;
6879

6880
	/* TODO: interpret S3D flags */
6881

6882
	mode->type = DRM_MODE_TYPE_DRIVER;
6883
	drm_mode_set_name(mode);
6884

6885
	return mode;
6886
}
6887

6888
static int add_displayid_formula_modes(struct drm_connector *connector,
6889
				       const struct displayid_block *block)
6890
{
6891
	const struct displayid_formula_timing_block *formula_block = (struct displayid_formula_timing_block *)block;
6892
	int num_timings;
6893
	struct drm_display_mode *newmode;
6894
	int num_modes = 0;
6895
	bool type_10 = block->tag == DATA_BLOCK_2_TYPE_10_FORMULA_TIMING;
6896
	int timing_size = 6 + ((formula_block->base.rev & 0x70) >> 4);
6897

6898
	/* extended blocks are not supported yet */
6899
	if (timing_size != 6)
6900
		return 0;
6901

6902
	if (block->num_bytes % timing_size)
6903
		return 0;
6904

6905
	num_timings = block->num_bytes / timing_size;
6906
	for (int i = 0; i < num_timings; i++) {
6907
		const struct displayid_formula_timings_9 *timings = &formula_block->timings[i];
6908

6909
		newmode = drm_mode_displayid_formula(connector->dev, timings, type_10);
6910
		if (!newmode)
6911
			continue;
6912

6913
		drm_mode_probed_add(connector, newmode);
6914
		num_modes++;
6915
	}
6916
	return num_modes;
6917
}
6918

6919
static int add_displayid_detailed_modes(struct drm_connector *connector,
6920
					const struct drm_edid *drm_edid)
6921
{
6922
	const struct displayid_block *block;
6923
	struct displayid_iter iter;
6924
	int num_modes = 0;
6925

6926
	displayid_iter_edid_begin(drm_edid, &iter);
6927
	displayid_iter_for_each(block, &iter) {
6928
		if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6929
		    block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
6930
			num_modes += add_displayid_detailed_1_modes(connector, block);
6931
		else if (block->tag == DATA_BLOCK_2_TYPE_9_FORMULA_TIMING ||
6932
			 block->tag == DATA_BLOCK_2_TYPE_10_FORMULA_TIMING)
6933
			num_modes += add_displayid_formula_modes(connector, block);
6934
	}
6935
	displayid_iter_end(&iter);
6936

6937
	return num_modes;
6938
}
6939

6940
static int _drm_edid_connector_add_modes(struct drm_connector *connector,
6941
					 const struct drm_edid *drm_edid)
6942
{
6943
	int num_modes = 0;
6944

6945
	if (!drm_edid)
6946
		return 0;
6947

6948
	/*
6949
	 * EDID spec says modes should be preferred in this order:
6950
	 * - preferred detailed mode
6951
	 * - other detailed modes from base block
6952
	 * - detailed modes from extension blocks
6953
	 * - CVT 3-byte code modes
6954
	 * - standard timing codes
6955
	 * - established timing codes
6956
	 * - modes inferred from GTF or CVT range information
6957
	 *
6958
	 * We get this pretty much right.
6959
	 *
6960
	 * XXX order for additional mode types in extension blocks?
6961
	 */
6962
	num_modes += add_detailed_modes(connector, drm_edid);
6963
	num_modes += add_cvt_modes(connector, drm_edid);
6964
	num_modes += add_standard_modes(connector, drm_edid);
6965
	num_modes += add_established_modes(connector, drm_edid);
6966
	num_modes += add_cea_modes(connector, drm_edid);
6967
	num_modes += add_alternate_cea_modes(connector, drm_edid);
6968
	num_modes += add_displayid_detailed_modes(connector, drm_edid);
6969
	if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
6970
		num_modes += add_inferred_modes(connector, drm_edid);
6971

6972
	if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_PREFER_LARGE_60) ||
6973
	    drm_edid_has_internal_quirk(connector, EDID_QUIRK_PREFER_LARGE_75))
6974
		edid_fixup_preferred(connector);
6975

6976
	return num_modes;
6977
}
6978

6979
static void _drm_update_tile_info(struct drm_connector *connector,
6980
				  const struct drm_edid *drm_edid);
6981

6982
static int _drm_edid_connector_property_update(struct drm_connector *connector,
6983
					       const struct drm_edid *drm_edid)
6984
{
6985
	struct drm_device *dev = connector->dev;
6986
	int ret;
6987

6988
	if (connector->edid_blob_ptr) {
6989
		const void *old_edid = connector->edid_blob_ptr->data;
6990
		size_t old_edid_size = connector->edid_blob_ptr->length;
6991

6992
		if (old_edid && !drm_edid_eq(drm_edid, old_edid, old_edid_size)) {
6993
			connector->epoch_counter++;
6994
			drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6995
				    connector->base.id, connector->name,
6996
				    connector->epoch_counter);
6997
		}
6998
	}
6999

7000
	ret = drm_property_replace_global_blob(dev,
7001
					       &connector->edid_blob_ptr,
7002
					       drm_edid ? drm_edid->size : 0,
7003
					       drm_edid ? drm_edid->edid : NULL,
7004
					       &connector->base,
7005
					       dev->mode_config.edid_property);
7006
	if (ret) {
7007
		drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
7008
			    connector->base.id, connector->name, ret);
7009
		goto out;
7010
	}
7011

7012
	ret = drm_object_property_set_value(&connector->base,
7013
					    dev->mode_config.non_desktop_property,
7014
					    connector->display_info.non_desktop);
7015
	if (ret) {
7016
		drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
7017
			    connector->base.id, connector->name, ret);
7018
		goto out;
7019
	}
7020

7021
	ret = drm_connector_set_tile_property(connector);
7022
	if (ret) {
7023
		drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
7024
			    connector->base.id, connector->name, ret);
7025
		goto out;
7026
	}
7027

7028
out:
7029
	return ret;
7030
}
7031

7032
/* For sysfs edid show implementation */
7033
ssize_t drm_edid_connector_property_show(struct drm_connector *connector,
7034
					 char *buf, loff_t off, size_t count)
7035
{
7036
	const void *edid;
7037
	size_t size;
7038
	ssize_t ret = 0;
7039

7040
	mutex_lock(&connector->dev->mode_config.mutex);
7041

7042
	if (!connector->edid_blob_ptr)
7043
		goto unlock;
7044

7045
	edid = connector->edid_blob_ptr->data;
7046
	size = connector->edid_blob_ptr->length;
7047
	if (!edid)
7048
		goto unlock;
7049

7050
	if (off >= size)
7051
		goto unlock;
7052

7053
	if (off + count > size)
7054
		count = size - off;
7055

7056
	memcpy(buf, edid + off, count);
7057

7058
	ret = count;
7059
unlock:
7060
	mutex_unlock(&connector->dev->mode_config.mutex);
7061

7062
	return ret;
7063
}
7064

7065
/**
7066
 * drm_edid_connector_update - Update connector information from EDID
7067
 * @connector: Connector
7068
 * @drm_edid: EDID
7069
 *
7070
 * Update the connector display info, ELD, HDR metadata, relevant properties,
7071
 * etc. from the passed in EDID.
7072
 *
7073
 * If EDID is NULL, reset the information.
7074
 *
7075
 * Must be called before calling drm_edid_connector_add_modes().
7076
 *
7077
 * Return: 0 on success, negative error on errors.
7078
 */
7079
int drm_edid_connector_update(struct drm_connector *connector,
7080
			      const struct drm_edid *drm_edid)
7081
{
7082
	update_display_info(connector, drm_edid);
7083

7084
	_drm_update_tile_info(connector, drm_edid);
7085

7086
	return _drm_edid_connector_property_update(connector, drm_edid);
7087
}
7088
EXPORT_SYMBOL(drm_edid_connector_update);
7089

7090
/**
7091
 * drm_edid_connector_add_modes - Update probed modes from the EDID property
7092
 * @connector: Connector
7093
 *
7094
 * Add the modes from the previously updated EDID property to the connector
7095
 * probed modes list.
7096
 *
7097
 * drm_edid_connector_update() must have been called before this to update the
7098
 * EDID property.
7099
 *
7100
 * Return: The number of modes added, or 0 if we couldn't find any.
7101
 */
7102
int drm_edid_connector_add_modes(struct drm_connector *connector)
7103
{
7104
	const struct drm_edid *drm_edid = NULL;
7105
	int count;
7106

7107
	if (connector->edid_blob_ptr)
7108
		drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data,
7109
					  connector->edid_blob_ptr->length);
7110

7111
	count = _drm_edid_connector_add_modes(connector, drm_edid);
7112

7113
	drm_edid_free(drm_edid);
7114

7115
	return count;
7116
}
7117
EXPORT_SYMBOL(drm_edid_connector_add_modes);
7118

7119
/**
7120
 * drm_connector_update_edid_property - update the edid property of a connector
7121
 * @connector: drm connector
7122
 * @edid: new value of the edid property
7123
 *
7124
 * This function creates a new blob modeset object and assigns its id to the
7125
 * connector's edid property.
7126
 * Since we also parse tile information from EDID's displayID block, we also
7127
 * set the connector's tile property here. See drm_connector_set_tile_property()
7128
 * for more details.
7129
 *
7130
 * This function is deprecated. Use drm_edid_connector_update() instead.
7131
 *
7132
 * Returns:
7133
 * Zero on success, negative errno on failure.
7134
 */
7135
int drm_connector_update_edid_property(struct drm_connector *connector,
7136
				       const struct edid *edid)
7137
{
7138
	struct drm_edid drm_edid;
7139

7140
	return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid));
7141
}
7142
EXPORT_SYMBOL(drm_connector_update_edid_property);
7143

7144
/**
7145
 * drm_add_edid_modes - add modes from EDID data, if available
7146
 * @connector: connector we're probing
7147
 * @edid: EDID data
7148
 *
7149
 * Add the specified modes to the connector's mode list. Also fills out the
7150
 * &drm_display_info structure and ELD in @connector with any information which
7151
 * can be derived from the edid.
7152
 *
7153
 * This function is deprecated. Use drm_edid_connector_add_modes() instead.
7154
 *
7155
 * Return: The number of modes added or 0 if we couldn't find any.
7156
 */
7157
int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
7158
{
7159
	struct drm_edid _drm_edid;
7160
	const struct drm_edid *drm_edid;
7161

7162
	if (edid && !drm_edid_is_valid(edid)) {
7163
		drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n",
7164
			 connector->base.id, connector->name);
7165
		edid = NULL;
7166
	}
7167

7168
	drm_edid = drm_edid_legacy_init(&_drm_edid, edid);
7169

7170
	update_display_info(connector, drm_edid);
7171

7172
	return _drm_edid_connector_add_modes(connector, drm_edid);
7173
}
7174
EXPORT_SYMBOL(drm_add_edid_modes);
7175

7176
/**
7177
 * drm_add_modes_noedid - add modes for the connectors without EDID
7178
 * @connector: connector we're probing
7179
 * @hdisplay: the horizontal display limit
7180
 * @vdisplay: the vertical display limit
7181
 *
7182
 * Add the specified modes to the connector's mode list. Only when the
7183
 * hdisplay/vdisplay is not beyond the given limit, it will be added.
7184
 *
7185
 * Return: The number of modes added or 0 if we couldn't find any.
7186
 */
7187
int drm_add_modes_noedid(struct drm_connector *connector,
7188
			 unsigned int hdisplay, unsigned int vdisplay)
7189
{
7190
	int i, count = ARRAY_SIZE(drm_dmt_modes), num_modes = 0;
7191
	struct drm_display_mode *mode;
7192
	struct drm_device *dev = connector->dev;
7193

7194
	for (i = 0; i < count; i++) {
7195
		const struct drm_display_mode *ptr = &drm_dmt_modes[i];
7196

7197
		if (hdisplay && vdisplay) {
7198
			/*
7199
			 * Only when two are valid, they will be used to check
7200
			 * whether the mode should be added to the mode list of
7201
			 * the connector.
7202
			 */
7203
			if (ptr->hdisplay > hdisplay ||
7204
					ptr->vdisplay > vdisplay)
7205
				continue;
7206
		}
7207
		if (drm_mode_vrefresh(ptr) > 61)
7208
			continue;
7209
		mode = drm_mode_duplicate(dev, ptr);
7210
		if (mode) {
7211
			drm_mode_probed_add(connector, mode);
7212
			num_modes++;
7213
		}
7214
	}
7215
	return num_modes;
7216
}
7217
EXPORT_SYMBOL(drm_add_modes_noedid);
7218

7219
static bool is_hdmi2_sink(const struct drm_connector *connector)
7220
{
7221
	/*
7222
	 * FIXME: sil-sii8620 doesn't have a connector around when
7223
	 * we need one, so we have to be prepared for a NULL connector.
7224
	 */
7225
	if (!connector)
7226
		return true;
7227

7228
	return connector->display_info.hdmi.scdc.supported ||
7229
		connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
7230
}
7231

7232
static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
7233
			    const struct drm_display_mode *mode)
7234
{
7235
	bool has_hdmi_infoframe = connector ?
7236
		connector->display_info.has_hdmi_infoframe : false;
7237

7238
	if (!has_hdmi_infoframe)
7239
		return 0;
7240

7241
	/* No HDMI VIC when signalling 3D video format */
7242
	if (mode->flags & DRM_MODE_FLAG_3D_MASK)
7243
		return 0;
7244

7245
	return drm_match_hdmi_mode(mode);
7246
}
7247

7248
static u8 drm_mode_cea_vic(const struct drm_connector *connector,
7249
			   const struct drm_display_mode *mode)
7250
{
7251
	/*
7252
	 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
7253
	 * we should send its VIC in vendor infoframes, else send the
7254
	 * VIC in AVI infoframes. Lets check if this mode is present in
7255
	 * HDMI 1.4b 4K modes
7256
	 */
7257
	if (drm_mode_hdmi_vic(connector, mode))
7258
		return 0;
7259

7260
	return drm_match_cea_mode(mode);
7261
}
7262

7263
/*
7264
 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that
7265
 * conform to HDMI 1.4.
7266
 *
7267
 * HDMI 1.4 (CTA-861-D) VIC range: [1..64]
7268
 * HDMI 2.0 (CTA-861-F) VIC range: [1..107]
7269
 *
7270
 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI
7271
 * version.
7272
 */
7273
static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic)
7274
{
7275
	if (!is_hdmi2_sink(connector) && vic > 64 &&
7276
	    !cta_vdb_has_vic(connector, vic))
7277
		return 0;
7278

7279
	return vic;
7280
}
7281

7282
/**
7283
 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
7284
 *                                              data from a DRM display mode
7285
 * @frame: HDMI AVI infoframe
7286
 * @connector: the connector
7287
 * @mode: DRM display mode
7288
 *
7289
 * Return: 0 on success or a negative error code on failure.
7290
 */
7291
int
7292
drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
7293
					 const struct drm_connector *connector,
7294
					 const struct drm_display_mode *mode)
7295
{
7296
	enum hdmi_picture_aspect picture_aspect;
7297
	u8 vic, hdmi_vic;
7298

7299
	if (!frame || !mode)
7300
		return -EINVAL;
7301

7302
	hdmi_avi_infoframe_init(frame);
7303

7304
	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
7305
		frame->pixel_repeat = 1;
7306

7307
	vic = drm_mode_cea_vic(connector, mode);
7308
	hdmi_vic = drm_mode_hdmi_vic(connector, mode);
7309

7310
	frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7311

7312
	/*
7313
	 * As some drivers don't support atomic, we can't use connector state.
7314
	 * So just initialize the frame with default values, just the same way
7315
	 * as it's done with other properties here.
7316
	 */
7317
	frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
7318
	frame->itc = 0;
7319

7320
	/*
7321
	 * Populate picture aspect ratio from either
7322
	 * user input (if specified) or from the CEA/HDMI mode lists.
7323
	 */
7324
	picture_aspect = mode->picture_aspect_ratio;
7325
	if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
7326
		if (vic)
7327
			picture_aspect = drm_get_cea_aspect_ratio(vic);
7328
		else if (hdmi_vic)
7329
			picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
7330
	}
7331

7332
	/*
7333
	 * The infoframe can't convey anything but none, 4:3
7334
	 * and 16:9, so if the user has asked for anything else
7335
	 * we can only satisfy it by specifying the right VIC.
7336
	 */
7337
	if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
7338
		if (vic) {
7339
			if (picture_aspect != drm_get_cea_aspect_ratio(vic))
7340
				return -EINVAL;
7341
		} else if (hdmi_vic) {
7342
			if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
7343
				return -EINVAL;
7344
		} else {
7345
			return -EINVAL;
7346
		}
7347

7348
		picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7349
	}
7350

7351
	frame->video_code = vic_for_avi_infoframe(connector, vic);
7352
	frame->picture_aspect = picture_aspect;
7353
	frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
7354
	frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
7355

7356
	return 0;
7357
}
7358
EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
7359

7360
/**
7361
 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
7362
 *                                        quantization range information
7363
 * @frame: HDMI AVI infoframe
7364
 * @connector: the connector
7365
 * @mode: DRM display mode
7366
 * @rgb_quant_range: RGB quantization range (Q)
7367
 */
7368
void
7369
drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
7370
				   const struct drm_connector *connector,
7371
				   const struct drm_display_mode *mode,
7372
				   enum hdmi_quantization_range rgb_quant_range)
7373
{
7374
	const struct drm_display_info *info = &connector->display_info;
7375

7376
	/*
7377
	 * CEA-861:
7378
	 * "A Source shall not send a non-zero Q value that does not correspond
7379
	 *  to the default RGB Quantization Range for the transmitted Picture
7380
	 *  unless the Sink indicates support for the Q bit in a Video
7381
	 *  Capabilities Data Block."
7382
	 *
7383
	 * HDMI 2.0 recommends sending non-zero Q when it does match the
7384
	 * default RGB quantization range for the mode, even when QS=0.
7385
	 */
7386
	if (info->rgb_quant_range_selectable ||
7387
	    rgb_quant_range == drm_default_rgb_quant_range(mode))
7388
		frame->quantization_range = rgb_quant_range;
7389
	else
7390
		frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
7391

7392
	/*
7393
	 * CEA-861-F:
7394
	 * "When transmitting any RGB colorimetry, the Source should set the
7395
	 *  YQ-field to match the RGB Quantization Range being transmitted
7396
	 *  (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
7397
	 *  set YQ=1) and the Sink shall ignore the YQ-field."
7398
	 *
7399
	 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
7400
	 * by non-zero YQ when receiving RGB. There doesn't seem to be any
7401
	 * good way to tell which version of CEA-861 the sink supports, so
7402
	 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
7403
	 * on CEA-861-F.
7404
	 */
7405
	if (!is_hdmi2_sink(connector) ||
7406
	    rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
7407
		frame->ycc_quantization_range =
7408
			HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
7409
	else
7410
		frame->ycc_quantization_range =
7411
			HDMI_YCC_QUANTIZATION_RANGE_FULL;
7412
}
7413
EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
7414

7415
static enum hdmi_3d_structure
7416
s3d_structure_from_display_mode(const struct drm_display_mode *mode)
7417
{
7418
	u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
7419

7420
	switch (layout) {
7421
	case DRM_MODE_FLAG_3D_FRAME_PACKING:
7422
		return HDMI_3D_STRUCTURE_FRAME_PACKING;
7423
	case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
7424
		return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
7425
	case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
7426
		return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
7427
	case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
7428
		return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
7429
	case DRM_MODE_FLAG_3D_L_DEPTH:
7430
		return HDMI_3D_STRUCTURE_L_DEPTH;
7431
	case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
7432
		return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
7433
	case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
7434
		return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
7435
	case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
7436
		return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
7437
	default:
7438
		return HDMI_3D_STRUCTURE_INVALID;
7439
	}
7440
}
7441

7442
/**
7443
 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
7444
 * data from a DRM display mode
7445
 * @frame: HDMI vendor infoframe
7446
 * @connector: the connector
7447
 * @mode: DRM display mode
7448
 *
7449
 * Note that there's is a need to send HDMI vendor infoframes only when using a
7450
 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
7451
 * function will return -EINVAL, error that can be safely ignored.
7452
 *
7453
 * Return: 0 on success or a negative error code on failure.
7454
 */
7455
int
7456
drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
7457
					    const struct drm_connector *connector,
7458
					    const struct drm_display_mode *mode)
7459
{
7460
	/*
7461
	 * FIXME: sil-sii8620 doesn't have a connector around when
7462
	 * we need one, so we have to be prepared for a NULL connector.
7463
	 */
7464
	bool has_hdmi_infoframe = connector ?
7465
		connector->display_info.has_hdmi_infoframe : false;
7466
	int err;
7467

7468
	if (!frame || !mode)
7469
		return -EINVAL;
7470

7471
	if (!has_hdmi_infoframe)
7472
		return -EINVAL;
7473

7474
	err = hdmi_vendor_infoframe_init(frame);
7475
	if (err < 0)
7476
		return err;
7477

7478
	/*
7479
	 * Even if it's not absolutely necessary to send the infoframe
7480
	 * (ie.vic==0 and s3d_struct==0) we will still send it if we
7481
	 * know that the sink can handle it. This is based on a
7482
	 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
7483
	 * have trouble realizing that they should switch from 3D to 2D
7484
	 * mode if the source simply stops sending the infoframe when
7485
	 * it wants to switch from 3D to 2D.
7486
	 */
7487
	frame->vic = drm_mode_hdmi_vic(connector, mode);
7488
	frame->s3d_struct = s3d_structure_from_display_mode(mode);
7489

7490
	return 0;
7491
}
7492
EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
7493

7494
static void drm_parse_tiled_block(struct drm_connector *connector,
7495
				  const struct displayid_block *block)
7496
{
7497
	const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
7498
	u16 w, h;
7499
	u8 tile_v_loc, tile_h_loc;
7500
	u8 num_v_tile, num_h_tile;
7501
	struct drm_tile_group *tg;
7502

7503
	w = tile->tile_size[0] | tile->tile_size[1] << 8;
7504
	h = tile->tile_size[2] | tile->tile_size[3] << 8;
7505

7506
	num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7507
	num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
7508
	tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
7509
	tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
7510

7511
	connector->has_tile = true;
7512
	if (tile->tile_cap & 0x80)
7513
		connector->tile_is_single_monitor = true;
7514

7515
	connector->num_h_tile = num_h_tile + 1;
7516
	connector->num_v_tile = num_v_tile + 1;
7517
	connector->tile_h_loc = tile_h_loc;
7518
	connector->tile_v_loc = tile_v_loc;
7519
	connector->tile_h_size = w + 1;
7520
	connector->tile_v_size = h + 1;
7521

7522
	drm_dbg_kms(connector->dev,
7523
		    "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c",
7524
		    connector->base.id, connector->name,
7525
		    tile->tile_cap,
7526
		    connector->tile_h_size, connector->tile_v_size,
7527
		    connector->num_h_tile, connector->num_v_tile,
7528
		    connector->tile_h_loc, connector->tile_v_loc,
7529
		    tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
7530

7531
	tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
7532
	if (!tg)
7533
		tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
7534
	if (!tg)
7535
		return;
7536

7537
	if (connector->tile_group != tg) {
7538
		/* if we haven't got a pointer,
7539
		   take the reference, drop ref to old tile group */
7540
		if (connector->tile_group)
7541
			drm_mode_put_tile_group(connector->dev, connector->tile_group);
7542
		connector->tile_group = tg;
7543
	} else {
7544
		/* if same tile group, then release the ref we just took. */
7545
		drm_mode_put_tile_group(connector->dev, tg);
7546
	}
7547
}
7548

7549
static bool displayid_is_tiled_block(const struct displayid_iter *iter,
7550
				     const struct displayid_block *block)
7551
{
7552
	return (displayid_version(iter) < DISPLAY_ID_STRUCTURE_VER_20 &&
7553
		block->tag == DATA_BLOCK_TILED_DISPLAY) ||
7554
		(displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
7555
		 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY);
7556
}
7557

7558
static void _drm_update_tile_info(struct drm_connector *connector,
7559
				  const struct drm_edid *drm_edid)
7560
{
7561
	const struct displayid_block *block;
7562
	struct displayid_iter iter;
7563

7564
	connector->has_tile = false;
7565

7566
	displayid_iter_edid_begin(drm_edid, &iter);
7567
	displayid_iter_for_each(block, &iter) {
7568
		if (displayid_is_tiled_block(&iter, block))
7569
			drm_parse_tiled_block(connector, block);
7570
	}
7571
	displayid_iter_end(&iter);
7572

7573
	if (!connector->has_tile && connector->tile_group) {
7574
		drm_mode_put_tile_group(connector->dev, connector->tile_group);
7575
		connector->tile_group = NULL;
7576
	}
7577
}
7578

7579
/**
7580
 * drm_edid_is_digital - is digital?
7581
 * @drm_edid: The EDID
7582
 *
7583
 * Return true if input is digital.
7584
 */
7585
bool drm_edid_is_digital(const struct drm_edid *drm_edid)
7586
{
7587
	return drm_edid && drm_edid->edid &&
7588
		drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL;
7589
}
7590
EXPORT_SYMBOL(drm_edid_is_digital);
7591

7592
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