Path: blob/master/drivers/gpu/host1x/hw/hw_host1x01_channel.h
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/* SPDX-License-Identifier: GPL-2.0-only */1/*2* Copyright (c) 2012-2013, NVIDIA Corporation.3*/45/*6* Function naming determines intended use:7*8* <x>_r(void) : Returns the offset for register <x>.9*10* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.11*12* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.13*14* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted15* and masked to place it at field <y> of register <x>. This value16* can be |'d with others to produce a full register value for17* register <x>.18*19* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This20* value can be ~'d and then &'d to clear the value of field <y> for21* register <x>.22*23* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted24* to place it at field <y> of register <x>. This value can be |'d25* with others to produce a full register value for <x>.26*27* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register28* <x> value 'r' after being shifted to place its LSB at bit 0.29* This value is suitable for direct comparison with other unshifted30* values appropriate for use in field <y> of register <x>.31*32* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for33* field <y> of register <x>. This value is suitable for direct34* comparison with unshifted values appropriate for use in field <y>35* of register <x>.36*/3738#ifndef __hw_host1x_channel_host1x_h__39#define __hw_host1x_channel_host1x_h__4041static inline u32 host1x_channel_fifostat_r(void)42{43return 0x0;44}45#define HOST1X_CHANNEL_FIFOSTAT \46host1x_channel_fifostat_r()47static inline u32 host1x_channel_fifostat_cfempty_v(u32 r)48{49return (r >> 10) & 0x1;50}51#define HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_V(r) \52host1x_channel_fifostat_cfempty_v(r)53static inline u32 host1x_channel_dmastart_r(void)54{55return 0x14;56}57#define HOST1X_CHANNEL_DMASTART \58host1x_channel_dmastart_r()59static inline u32 host1x_channel_dmaput_r(void)60{61return 0x18;62}63#define HOST1X_CHANNEL_DMAPUT \64host1x_channel_dmaput_r()65static inline u32 host1x_channel_dmaget_r(void)66{67return 0x1c;68}69#define HOST1X_CHANNEL_DMAGET \70host1x_channel_dmaget_r()71static inline u32 host1x_channel_dmaend_r(void)72{73return 0x20;74}75#define HOST1X_CHANNEL_DMAEND \76host1x_channel_dmaend_r()77static inline u32 host1x_channel_dmactrl_r(void)78{79return 0x24;80}81#define HOST1X_CHANNEL_DMACTRL \82host1x_channel_dmactrl_r()83static inline u32 host1x_channel_dmactrl_dmastop(void)84{85return 1 << 0;86}87#define HOST1X_CHANNEL_DMACTRL_DMASTOP \88host1x_channel_dmactrl_dmastop()89static inline u32 host1x_channel_dmactrl_dmastop_v(u32 r)90{91return (r >> 0) & 0x1;92}93#define HOST1X_CHANNEL_DMACTRL_DMASTOP_V(r) \94host1x_channel_dmactrl_dmastop_v(r)95static inline u32 host1x_channel_dmactrl_dmagetrst(void)96{97return 1 << 1;98}99#define HOST1X_CHANNEL_DMACTRL_DMAGETRST \100host1x_channel_dmactrl_dmagetrst()101static inline u32 host1x_channel_dmactrl_dmainitget(void)102{103return 1 << 2;104}105#define HOST1X_CHANNEL_DMACTRL_DMAINITGET \106host1x_channel_dmactrl_dmainitget()107#endif108109110